HOME UP PREV NEXT (Mixed Analog/Digital Simulation: An interesting problem attributable to Zeno?)

Mixed Analog/Digital Simulation (Verilog-AMS)

Hybrid System simulations: typically a digital (embedded) controller interacts with analogue plant.

Example: Vehicle hybrid power system and automatic braking system.

We need to be able to combine digital (event-driven) simulation with analogue models, such as fluid-flow nodal analysis and FDTD modelling.

Cyberphysical tends: »Cyberphysical Functional Mock Up Interface

Relevant tools: Verilog-AMS, VHDL-AMS, Modelica, Simulink and FMI. »Wikipedia: Verilog-AMS

Verilog Analogue and Mixed Signal (AMS) extends RTL to support:

Signals of both analogue and digital types can be declared in the same module.
Initial, always and analogue procedural blocks can appear in the same module.
Digital signal values can be set (write operations) from any context outside of an analogue procedural block
Analogue potentials and flows can only receive contributions (write operations) from inside an analogue procedural block
An analog initial begin ... end statement sets up initial voltages on capacitors or levels in a fuel tank.
A new sensitivity enables triggering actions always @(cross(Vt1 - 2.5)) begin ... end .

Examples:

// Three 1.5 cells in series make a 4.5 volt battery.
module Battery4V5(input voltage anode, output voltage cathode);
  voltage t1, t2;
  analog begin 
    V(anode) <+ 1.5 + V(t2);
    V(t2) <+ 1.5 + V(t1);
    V(t2) <+ 1.5 + V(cathode);
  end
endmodule

module resistor (inout electrical a, inout electrical b);
  parameter real R = 4700;
  analog V(a,b) <+ R * I(a,b);
endmodule

Verilog simulation cycle extended to support solving nodal flow equations.

When we potentially de-queue a time-advancing event from EDS queue we first roll forward the FDTD simulations which themselves may contain `cross' and similar sensitivity that insert new events on the EDS queue.