Hazards

»Definitions (some authors vary slightly):

• WaW hazard - write-after-write: one write must occur after another otherwise the wrong answer persists,
• RaW or WaR hazard - write and read of a location are accidentally permuted,
• Other Data hazard - when an operand simply has not arrived in time for use,
• Control hazard - when it is not yet clear whether the results of operation should be committed (computation might still start speculatively),
• Name Alias hazard - we do not know if two array subscripts are equal,
• Structural hazard - insufficient physical resources to do everything at once.

(Where the address to a register file has not yet arrived we have a data hazard on the address itself, but this could be regarded as a control hazard for the register file operation itself (read or write).)

We have a structural hazard when an operation cannot proceed because a resource is already in use.

Resources that might present structural hazards are:

• Memories and register files with insufficient ports,
• Memories with variable latency, especially DRAM,
• Insufficient number of ALUs for all the arithmetic to be schedulled in current clock tick,
• Anything non-fully pipelined i.e. something that goes busy, such as long multiplication (e.g. »Booth Multiplier or division or a floating point unit).

A fully-pipelined component can start a new operation on every clock cycle. It will have fixed latency (pipeline delay). These are commonly encounted and are easiest to form schedules around.

A non-fully pipelined components generally have handshake wires that start it and inform the client logic when it is busy. This is needed for computations better performed with variable latency.

Another form that is non-fully pipelined has a reinitiation inverval greater than one: for example, it might accept new data every third clock cycle, but still be fixed-latency.

Synchronous RAMs, and most complex ALUs excluding divide, are generally fully pipelined and fixed-latency.

39: (C) 2008-18, DJ Greaves, University of Cambridge, Computer Laboratory.

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