Non-synth continued.

Another common source of non-synthesisable RTL code is testbenches. Testbenches commonly uses delays:

  // Typical RTL testbench contents:

  // Set the time in seconds for each clock unit.
  `timescale 1 ns

  reg clk, reset;
  initial begin clk=0; forever #5 clk = !clk; end   // Clock source 100 MHz
  initial begin reset = 1; # 125 reset = 0; end     // Power-on reset generator

Take-away summary: The industry has essentially zeroed-in on a very narrow synthesisable RTL subset. Behavioural input forms are essentially `syntactic sugar' that are mapped down to pure RTL before logic minimisation and gate mapping.

25: (C) 2008-18, DJ Greaves, University of Cambridge, Computer Laboratory.

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