The mainstream VLSI technology in the period 2004-2008 was 90 nm. This had low leakage and very high wafer yields.
Now the industry is using 22 nanometer and smaller.
Parameters from a 90 nanometer standard cell library:
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Typical processor core: 200k gates + 4 RAMs: one square millimeter.
Typical SoC chip area is 50-100 mm² → 20-40 million gates (semi-custom/standard cell).
Actual gate and transistor counts are higher owing to full-custom blocks (RAMs mainly).
» Moore's Law » Transistor Count »Dennard Scaling
»Dimension Increase in Metal-Oxide-Semiconductor Memories and Transistors
Dennard's Rule stated that as transistors get smaller, their power density stays constant, so that the power use stays in proportion with area: both voltage and current scale (downward) with length.
This meant that no new heat extraction technology was needed as VLSI capabilities improved.
But once a supply voltage of 1 volt was reached, silicon CMOS cannot be run at much lower voltages without leakage (static power) greatly increasing.
Typical modern datasheet rubric: "The Xilinx Kintex UltraScaleTM FPGAs are available in -3, -2, -1, and -1L speed grades, with -3 having the highest performance. The -1L devices can operate at either of two VCCINT voltages, 0.95V and 0.90V and are screened for lower maximum static power. When operated at VCCINT = 0.95V, the speed specification of a -1L device is the same as the -1 speed grade. When operated at VCCINT = 0.90V, the -1L performance and static and dynamic power is reduced."
26: (C) 2008-18, DJ Greaves, University of Cambridge, Computer Laboratory. |