Basic bus illustration: one initiator and three targets.
No tri-states are used: address and write data outputs use wire joints or buffers; read data uses multiplexors.
No bus arbitration is needed.
Max throughput is unity (i.e. one word per clock tick).
Typical SoC bus capacity: 32 bits × 200 MHz = 6.4 Gb/s.
The interrupt wiring is not shown. If device 1 is a processor, it might have a dedicated interrupt wire from each other device.
| 28: (C) 2008-18, DJ Greaves, University of Cambridge, Computer Laboratory. |