Bus Bridge

Cycles slaved on one side are mastered on the other.
Need not be symmetric, or have flat address space.
Busses can be dissimilar.
Writes can be 'posted' (using internal FIFO).
(On SoC, the `busses' on each side use multiplexors and not tri-states.)
System bandwidth ranges from 1.0 to 2.0 bus bandwidth: in inverse proportion to the fraction of bridge crossing cycles.