// CBG Orangepath HPR L/S System // Verilog output file generated at 26/08/2016 18:51:47 // Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 2.16a : 25th-August-2016 Linux/X86_64:koo // /home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/kiwic.exe -give-backtrace -vnl-rootmodname=DUT -vnl=lu-decomp.v lu-decomp.exe -vnl-resets=synchronous -kiwic-cil-dump=combined -kiwic-kcode-dump=enable -res2-loadstore-port-count=0 -vnl-roundtrip=disable -max_no_int_divs=10 -max_no_fp_divs=10 -max_no_int_muls=10 -max_no_fp_muls=10 -int_fl_limit_mul=20 -bevelab-default-pause-mode=soft -bevelab-soft-pause-threshold=5 -kiwic-register-colours=1 `timescale 1ns/1ns module DUT(output reg [639:0] KppWaypoint0, output [639:0] KppWaypoint1, input clk, input reset); function signed [31:0] rtl_signed_bitextract0; input [63:0] arg; rtl_signed_bitextract0 = $signed(arg[31:0]); endfunction function [63:0] rtl_unsigned_extend1; input [31:0] arg; rtl_unsigned_extend1 = { 32'b0, arg[31:0] }; endfunction wire [63:0] tnow; reg [63:0] TMm1_V_1_GP; integer TMm1_V_2_GP; integer TMp1_V_0_GP; reg [63:0] Tlge0_9_V_4; integer lTMTMaV_1_GP; wire [63:0] A_FPD_CC_SCALbx44_ARG0_RDD0; reg [5:0] A_FPD_CC_SCALbx44_ARG0_AD0; reg A_FPD_CC_SCALbx44_ARG0_WEN0; reg A_FPD_CC_SCALbx44_ARG0_REN0; reg [63:0] A_FPD_CC_SCALbx44_ARG0_WRD0; wire [63:0] CVFPADDER10_FPRR; reg [63:0] CVFPADDER10_A0; reg [63:0] CVFPADDER10_A1; wire CVFPADDER10_fail; wire [63:0] CVFPADDER12_FPRR; reg [63:0] CVFPADDER12_A0; reg [63:0] CVFPADDER12_A1; wire CVFPADDER12_fail; wire [63:0] CVFPADDER14_FPRR; reg [63:0] CVFPADDER14_A0; reg [63:0] CVFPADDER14_A1; wire CVFPADDER14_fail; wire [63:0] CVFPADDER16_FPRR; reg [63:0] CVFPADDER16_A0; reg [63:0] CVFPADDER16_A1; wire CVFPADDER16_fail; wire [63:0] CVFPADDER18_FPRR; reg [63:0] CVFPADDER18_A0; reg [63:0] CVFPADDER18_A1; wire CVFPADDER18_fail; wire [63:0] CVFPADDER20_FPRR; reg [63:0] CVFPADDER20_A0; reg [63:0] CVFPADDER20_A1; wire CVFPADDER20_fail; wire [63:0] A_FPD_CC_SCALbx34_ARB0_RDD0; reg [5:0] A_FPD_CC_SCALbx34_ARB0_AD0; reg A_FPD_CC_SCALbx34_ARB0_WEN0; reg A_FPD_CC_SCALbx34_ARB0_REN0; reg [63:0] A_FPD_CC_SCALbx34_ARB0_WRD0; wire [63:0] A_FPD_CC_SCALbx32_ARA0_RDD0; reg [5:0] A_FPD_CC_SCALbx32_ARA0_AD0; reg A_FPD_CC_SCALbx32_ARA0_WEN0; reg A_FPD_CC_SCALbx32_ARA0_REN0; reg [63:0] A_FPD_CC_SCALbx32_ARA0_WRD0; wire [63:0] A_FPD_CC_SCALbx38_ARD0_RDD0; reg [2:0] A_FPD_CC_SCALbx38_ARD0_AD0; reg A_FPD_CC_SCALbx38_ARD0_WEN0; reg A_FPD_CC_SCALbx38_ARD0_REN0; reg [63:0] A_FPD_CC_SCALbx38_ARD0_WRD0; wire [63:0] fpcvt10_result; reg signed [31:0] fpcvt10_arg; wire fpcvt10_fail; wire [63:0] CVFPMULTIPLIER10_FPRR; reg [63:0] CVFPMULTIPLIER10_A0; reg [63:0] CVFPMULTIPLIER10_A1; wire CVFPMULTIPLIER10_fail; wire [63:0] fpcvt12_result; reg signed [31:0] fpcvt12_arg; wire fpcvt12_fail; wire [63:0] CVFPMULTIPLIER12_FPRR; reg [63:0] CVFPMULTIPLIER12_A0; reg [63:0] CVFPMULTIPLIER12_A1; wire CVFPMULTIPLIER12_fail; wire [63:0] A_FPD_CC_SCALbx40_ARE0_RDD0; reg [2:0] A_FPD_CC_SCALbx40_ARE0_AD0; reg A_FPD_CC_SCALbx40_ARE0_WEN0; reg A_FPD_CC_SCALbx40_ARE0_REN0; reg [63:0] A_FPD_CC_SCALbx40_ARE0_WRD0; wire [63:0] A_FPD_CC_SCALbx42_ARF0_RDD0; reg [2:0] A_FPD_CC_SCALbx42_ARF0_AD0; reg A_FPD_CC_SCALbx42_ARF0_WEN0; reg A_FPD_CC_SCALbx42_ARF0_REN0; reg [63:0] A_FPD_CC_SCALbx42_ARF0_WRD0; wire [63:0] A_FPD_CC_SCALbx46_ARH0_RDD0; reg [2:0] A_FPD_CC_SCALbx46_ARH0_AD0; reg A_FPD_CC_SCALbx46_ARH0_WEN0; reg A_FPD_CC_SCALbx46_ARH0_REN0; reg [63:0] A_FPD_CC_SCALbx46_ARH0_WRD0; wire [63:0] CVFPMULTIPLIER14_FPRR; reg [63:0] CVFPMULTIPLIER14_A0; reg [63:0] CVFPMULTIPLIER14_A1; wire CVFPMULTIPLIER14_fail; wire [63:0] CVFPMULTIPLIER16_FPRR; reg [63:0] CVFPMULTIPLIER16_A0; reg [63:0] CVFPMULTIPLIER16_A1; wire CVFPMULTIPLIER16_fail; wire [63:0] CVFPDIVIDER10_FPRR; reg [63:0] CVFPDIVIDER10_NN; reg [63:0] CVFPDIVIDER10_DD; wire CVFPDIVIDER10_fail; wire [63:0] CVFPMULTIPLIER18_FPRR; reg [63:0] CVFPMULTIPLIER18_A0; reg [63:0] CVFPMULTIPLIER18_A1; wire CVFPMULTIPLIER18_fail; wire [63:0] CVFPDIVIDER12_FPRR; reg [63:0] CVFPDIVIDER12_NN; reg [63:0] CVFPDIVIDER12_DD; wire CVFPDIVIDER12_fail; wire [63:0] CVFPMULTIPLIER20_FPRR; reg [63:0] CVFPMULTIPLIER20_A0; reg [63:0] CVFPMULTIPLIER20_A1; wire CVFPMULTIPLIER20_fail; wire [63:0] CVFPMULTIPLIER22_FPRR; reg [63:0] CVFPMULTIPLIER22_A0; reg [63:0] CVFPMULTIPLIER22_A1; wire CVFPMULTIPLIER22_fail; wire [63:0] CVFPMULTIPLIER24_FPRR; reg [63:0] CVFPMULTIPLIER24_A0; reg [63:0] CVFPMULTIPLIER24_A1; wire CVFPMULTIPLIER24_fail; wire [63:0] fpcvt14_result; reg signed [31:0] fpcvt14_arg; wire fpcvt14_fail; wire [63:0] CVFPMULTIPLIER26_FPRR; reg [63:0] CVFPMULTIPLIER26_A0; reg [63:0] CVFPMULTIPLIER26_A1; wire CVFPMULTIPLIER26_fail; wire [63:0] fpcvt16_result; reg signed [31:0] fpcvt16_arg; wire fpcvt16_fail; wire [63:0] CVFPMULTIPLIER28_FPRR; reg [63:0] CVFPMULTIPLIER28_A0; reg [63:0] CVFPMULTIPLIER28_A1; wire CVFPMULTIPLIER28_fail; wire [63:0] A_FPD_CC_SCALbx36_ARC0_RDD0; reg [5:0] A_FPD_CC_SCALbx36_ARC0_AD0; reg A_FPD_CC_SCALbx36_ARC0_WEN0; reg A_FPD_CC_SCALbx36_ARC0_REN0; reg [63:0] A_FPD_CC_SCALbx36_ARC0_WRD0; wire [63:0] CVFPDIVIDER14_FPRR; reg [63:0] CVFPDIVIDER14_NN; reg [63:0] CVFPDIVIDER14_DD; wire CVFPDIVIDER14_fail; wire [63:0] CVFPDIVIDER16_FPRR; reg [63:0] CVFPDIVIDER16_NN; reg [63:0] CVFPDIVIDER16_DD; wire CVFPDIVIDER16_fail; reg [63:0] CVFPDIVIDER16RRh10hold; reg CVFPDIVIDER16RRh10shot0; reg CVFPDIVIDER16RRh10shot1; reg CVFPDIVIDER16RRh10shot2; reg CVFPDIVIDER16RRh10shot3; reg CVFPDIVIDER16RRh10shot4; reg [63:0] CVFPDIVIDER14RRh10hold; reg CVFPDIVIDER14RRh10shot0; reg CVFPDIVIDER14RRh10shot1; reg CVFPDIVIDER14RRh10shot2; reg CVFPDIVIDER14RRh10shot3; reg CVFPDIVIDER14RRh10shot4; reg [63:0] FPDCCSCALbx34ARB0RRh12hold; reg FPDCCSCALbx34ARB0RRh12shot0; reg [63:0] FPDCCSCALbx36ARC0RRh10hold; reg FPDCCSCALbx36ARC0RRh10shot0; reg [63:0] CVFPMULTIPLIER28RRh10hold; reg CVFPMULTIPLIER28RRh10shot0; reg CVFPMULTIPLIER28RRh10shot1; reg CVFPMULTIPLIER28RRh10shot2; reg [63:0] CVFPMULTIPLIER26RRh10hold; reg CVFPMULTIPLIER26RRh10shot0; reg CVFPMULTIPLIER26RRh10shot1; reg CVFPMULTIPLIER26RRh10shot2; reg [63:0] fpcvt16RRh10hold; reg fpcvt16RRh10shot0; reg fpcvt16RRh10shot1; reg [63:0] fpcvt14RRh10hold; reg fpcvt14RRh10shot0; reg fpcvt14RRh10shot1; reg [63:0] CVFPMULTIPLIER24RRh10hold; reg CVFPMULTIPLIER24RRh10shot0; reg CVFPMULTIPLIER24RRh10shot1; reg CVFPMULTIPLIER24RRh10shot2; reg [63:0] CVFPMULTIPLIER22RRh10hold; reg CVFPMULTIPLIER22RRh10shot0; reg CVFPMULTIPLIER22RRh10shot1; reg CVFPMULTIPLIER22RRh10shot2; reg [63:0] FPDCCSCALbx32ARA0RRh10hold; reg FPDCCSCALbx32ARA0RRh10shot0; reg [63:0] CVFPDIVIDER12RRh10hold; reg CVFPDIVIDER12RRh10shot0; reg CVFPDIVIDER12RRh10shot1; reg CVFPDIVIDER12RRh10shot2; reg CVFPDIVIDER12RRh10shot3; reg CVFPDIVIDER12RRh10shot4; reg [63:0] CVFPMULTIPLIER20RRh10hold; reg CVFPMULTIPLIER20RRh10shot0; reg CVFPMULTIPLIER20RRh10shot1; reg CVFPMULTIPLIER20RRh10shot2; reg [63:0] CVFPDIVIDER10RRh10hold; reg CVFPDIVIDER10RRh10shot0; reg CVFPDIVIDER10RRh10shot1; reg CVFPDIVIDER10RRh10shot2; reg CVFPDIVIDER10RRh10shot3; reg CVFPDIVIDER10RRh10shot4; reg [63:0] CVFPMULTIPLIER18RRh10hold; reg CVFPMULTIPLIER18RRh10shot0; reg CVFPMULTIPLIER18RRh10shot1; reg CVFPMULTIPLIER18RRh10shot2; reg [63:0] CVFPMULTIPLIER16RRh10hold; reg CVFPMULTIPLIER16RRh10shot0; reg CVFPMULTIPLIER16RRh10shot1; reg CVFPMULTIPLIER16RRh10shot2; reg [63:0] CVFPMULTIPLIER14RRh10hold; reg CVFPMULTIPLIER14RRh10shot0; reg CVFPMULTIPLIER14RRh10shot1; reg CVFPMULTIPLIER14RRh10shot2; reg [63:0] FPDCCSCALbx46ARH0RRh10hold; reg FPDCCSCALbx46ARH0RRh10shot0; reg [63:0] FPDCCSCALbx42ARF0RRh10hold; reg FPDCCSCALbx42ARF0RRh10shot0; reg [63:0] FPDCCSCALbx40ARE0RRh10hold; reg FPDCCSCALbx40ARE0RRh10shot0; reg [63:0] FPDCCSCALbx38ARD0RRh10hold; reg FPDCCSCALbx38ARD0RRh10shot0; reg [63:0] CVFPMULTIPLIER12RRh10hold; reg CVFPMULTIPLIER12RRh10shot0; reg CVFPMULTIPLIER12RRh10shot1; reg CVFPMULTIPLIER12RRh10shot2; reg [63:0] CVFPMULTIPLIER10RRh10hold; reg CVFPMULTIPLIER10RRh10shot0; reg CVFPMULTIPLIER10RRh10shot1; reg CVFPMULTIPLIER10RRh10shot2; reg [63:0] fpcvt12RRh10hold; reg fpcvt12RRh10shot0; reg fpcvt12RRh10shot1; reg [63:0] fpcvt10RRh10hold; reg fpcvt10RRh10shot0; reg fpcvt10RRh10shot1; reg [63:0] FPDCCSCALbx34ARB0RRh10hold; reg FPDCCSCALbx34ARB0RRh10shot0; reg [63:0] CVFPADDER20RRh10hold; reg CVFPADDER20RRh10shot0; reg CVFPADDER20RRh10shot1; reg CVFPADDER20RRh10shot2; reg CVFPADDER20RRh10shot3; reg [63:0] CVFPADDER18RRh10hold; reg CVFPADDER18RRh10shot0; reg CVFPADDER18RRh10shot1; reg CVFPADDER18RRh10shot2; reg CVFPADDER18RRh10shot3; reg [63:0] CVFPADDER16RRh10hold; reg CVFPADDER16RRh10shot0; reg CVFPADDER16RRh10shot1; reg CVFPADDER16RRh10shot2; reg CVFPADDER16RRh10shot3; reg [63:0] CVFPADDER14RRh10hold; reg CVFPADDER14RRh10shot0; reg CVFPADDER14RRh10shot1; reg CVFPADDER14RRh10shot2; reg CVFPADDER14RRh10shot3; reg [63:0] CVFPADDER12RRh10hold; reg CVFPADDER12RRh10shot0; reg CVFPADDER12RRh10shot1; reg CVFPADDER12RRh10shot2; reg CVFPADDER12RRh10shot3; reg [63:0] CVFPADDER10RRh10hold; reg CVFPADDER10RRh10shot0; reg CVFPADDER10RRh10shot1; reg CVFPADDER10RRh10shot2; reg CVFPADDER10RRh10shot3; reg [63:0] FPDCCSCALbx44ARG0RRh10hold; reg FPDCCSCALbx44ARG0RRh10shot0; reg [9:0] xpc10nz; always @(* ) begin KppWaypoint0 = 32'sd0; CVFPDIVIDER16_NN = 32'sd0; CVFPDIVIDER16_DD = 32'sd0; CVFPDIVIDER14_NN = 32'sd0; CVFPDIVIDER14_DD = 32'sd0; A_FPD_CC_SCALbx36_ARC0_WRD0 = 32'sd0; A_FPD_CC_SCALbx36_ARC0_AD0 = 32'sd0; CVFPMULTIPLIER28_A0 = 32'sd0; CVFPMULTIPLIER28_A1 = 32'sd0; CVFPMULTIPLIER26_A0 = 32'sd0; CVFPMULTIPLIER26_A1 = 32'sd0; fpcvt16_arg = 32'sd0; fpcvt14_arg = 32'sd0; CVFPMULTIPLIER24_A0 = 32'sd0; CVFPMULTIPLIER24_A1 = 32'sd0; CVFPMULTIPLIER22_A0 = 32'sd0; CVFPMULTIPLIER22_A1 = 32'sd0; CVFPMULTIPLIER20_A0 = 32'sd0; CVFPMULTIPLIER20_A1 = 32'sd0; CVFPDIVIDER12_NN = 32'sd0; CVFPDIVIDER12_DD = 32'sd0; CVFPMULTIPLIER18_A0 = 32'sd0; CVFPMULTIPLIER18_A1 = 32'sd0; A_FPD_CC_SCALbx42_ARF0_WRD0 = 32'sd0; CVFPDIVIDER10_NN = 32'sd0; CVFPDIVIDER10_DD = 32'sd0; CVFPMULTIPLIER16_A0 = 32'sd0; CVFPMULTIPLIER16_A1 = 32'sd0; CVFPMULTIPLIER14_A0 = 32'sd0; CVFPMULTIPLIER14_A1 = 32'sd0; A_FPD_CC_SCALbx46_ARH0_WRD0 = 32'sd0; A_FPD_CC_SCALbx46_ARH0_AD0 = 32'sd0; A_FPD_CC_SCALbx42_ARF0_AD0 = 32'sd0; A_FPD_CC_SCALbx40_ARE0_AD0 = 32'sd0; A_FPD_CC_SCALbx40_ARE0_WRD0 = 32'sd0; CVFPMULTIPLIER12_A0 = 32'sd0; CVFPMULTIPLIER12_A1 = 32'sd0; CVFPMULTIPLIER10_A0 = 32'sd0; CVFPMULTIPLIER10_A1 = 32'sd0; fpcvt12_arg = 32'sd0; fpcvt10_arg = 32'sd0; A_FPD_CC_SCALbx32_ARA0_AD0 = 32'sd0; A_FPD_CC_SCALbx32_ARA0_WRD0 = 32'sd0; A_FPD_CC_SCALbx38_ARD0_AD0 = 32'sd0; A_FPD_CC_SCALbx38_ARD0_WRD0 = 32'sd0; A_FPD_CC_SCALbx34_ARB0_AD0 = 32'sd0; A_FPD_CC_SCALbx34_ARB0_WRD0 = 32'sd0; CVFPADDER20_A0 = 32'sd0; CVFPADDER20_A1 = 32'sd0; CVFPADDER18_A0 = 32'sd0; CVFPADDER18_A1 = 32'sd0; CVFPADDER16_A0 = 32'sd0; CVFPADDER16_A1 = 32'sd0; CVFPADDER14_A0 = 32'sd0; CVFPADDER14_A1 = 32'sd0; CVFPADDER12_A0 = 32'sd0; CVFPADDER12_A1 = 32'sd0; CVFPADDER10_A0 = 32'sd0; CVFPADDER10_A1 = 32'sd0; A_FPD_CC_SCALbx44_ARG0_AD0 = 32'sd0; A_FPD_CC_SCALbx44_ARG0_WRD0 = 32'sd0; A_FPD_CC_SCALbx34_ARB0_REN0 = 32'sd0; A_FPD_CC_SCALbx32_ARA0_WEN0 = 32'sd0; A_FPD_CC_SCALbx34_ARB0_WEN0 = 32'sd0; A_FPD_CC_SCALbx32_ARA0_REN0 = 32'sd0; A_FPD_CC_SCALbx36_ARC0_WEN0 = 32'sd0; A_FPD_CC_SCALbx36_ARC0_REN0 = 32'sd0; A_FPD_CC_SCALbx38_ARD0_WEN0 = 32'sd0; A_FPD_CC_SCALbx40_ARE0_WEN0 = 32'sd0; A_FPD_CC_SCALbx38_ARD0_REN0 = 32'sd0; A_FPD_CC_SCALbx40_ARE0_REN0 = 32'sd0; A_FPD_CC_SCALbx42_ARF0_WEN0 = 32'sd0; A_FPD_CC_SCALbx42_ARF0_REN0 = 32'sd0; A_FPD_CC_SCALbx46_ARH0_WEN0 = 32'sd0; A_FPD_CC_SCALbx44_ARG0_REN0 = 32'sd0; A_FPD_CC_SCALbx46_ARH0_REN0 = 32'sd0; A_FPD_CC_SCALbx44_ARG0_WEN0 = 32'sd0; A_FPD_CC_SCALbx44_ARG0_WEN0 = ((xpc10nz==10'sd372/*372:xpc10nz*/) || (xpc10nz==10'sd354/*354:xpc10nz*/) || (xpc10nz==10'sd336/*336:xpc10nz*/) || (xpc10nz==10'sd318/*318:xpc10nz*/) || (xpc10nz==10'sd302/*302:xpc10nz*/) || (xpc10nz==10'sd294/*294:xpc10nz*/) || (xpc10nz==10'sd286 /*286:xpc10nz*/) || (xpc10nz==10'sd278/*278:xpc10nz*/) || (xpc10nz==10'sd268/*268:xpc10nz*/) || (xpc10nz==10'sd260/*260:xpc10nz*/) || (xpc10nz==10'sd252/*252:xpc10nz*/) || (xpc10nz==10'sd244/*244:xpc10nz*/) || (xpc10nz==10'sd234/*234:xpc10nz*/) || (xpc10nz==10'sd226 /*226:xpc10nz*/) || (xpc10nz==10'sd218/*218:xpc10nz*/) || (xpc10nz==10'sd210/*210:xpc10nz*/) || (xpc10nz==10'sd200/*200:xpc10nz*/) || (xpc10nz==10'sd192/*192:xpc10nz*/) || (xpc10nz==10'sd184/*184:xpc10nz*/) || (xpc10nz==10'sd176/*176:xpc10nz*/) || (xpc10nz==10'sd166 /*166:xpc10nz*/) || (xpc10nz==10'sd158/*158:xpc10nz*/) || (xpc10nz==10'sd150/*150:xpc10nz*/) || (xpc10nz==10'sd142/*142:xpc10nz*/) || (xpc10nz==10'sd132/*132:xpc10nz*/) || (xpc10nz==10'sd124/*124:xpc10nz*/) || (xpc10nz==10'sd116/*116:xpc10nz*/) || (xpc10nz==10'sd108 /*108:xpc10nz*/) || (xpc10nz==10'sd98/*98:xpc10nz*/) || (xpc10nz==10'sd90/*90:xpc10nz*/) || (xpc10nz==10'sd82/*82:xpc10nz*/) || (xpc10nz==10'sd74/*74:xpc10nz*/) || (xpc10nz==10'sd64/*64:xpc10nz*/) || (xpc10nz==10'sd56/*56:xpc10nz*/) || (xpc10nz==10'sd48/*48:xpc10nz*/) || (xpc10nz==10'sd40/*40:xpc10nz*/) || (xpc10nz==10'sd44/*44:xpc10nz*/) || (xpc10nz==10'sd52/*52:xpc10nz*/) || (xpc10nz==10'sd60/*60:xpc10nz*/) || (xpc10nz==10'sd68/*68:xpc10nz*/) || (xpc10nz==10'sd78/*78:xpc10nz*/) || (xpc10nz==10'sd86/*86:xpc10nz*/) || (xpc10nz==10'sd94/*94:xpc10nz*/) || (xpc10nz==10'sd102/*102:xpc10nz*/) || (xpc10nz==10'sd112/*112:xpc10nz*/) || (xpc10nz==10'sd120/*120:xpc10nz*/) || (xpc10nz==10'sd128 /*128:xpc10nz*/) || (xpc10nz==10'sd136/*136:xpc10nz*/) || (xpc10nz==10'sd146/*146:xpc10nz*/) || (xpc10nz==10'sd154/*154:xpc10nz*/) || (xpc10nz==10'sd162/*162:xpc10nz*/) || (xpc10nz==10'sd170/*170:xpc10nz*/) || (xpc10nz==10'sd180/*180:xpc10nz*/) || (xpc10nz==10'sd188 /*188:xpc10nz*/) || (xpc10nz==10'sd196/*196:xpc10nz*/) || (xpc10nz==10'sd204/*204:xpc10nz*/) || (xpc10nz==10'sd214/*214:xpc10nz*/) || (xpc10nz==10'sd222/*222:xpc10nz*/) || (xpc10nz==10'sd230/*230:xpc10nz*/) || (xpc10nz==10'sd238/*238:xpc10nz*/) || (xpc10nz==10'sd248 /*248:xpc10nz*/) || (xpc10nz==10'sd256/*256:xpc10nz*/) || (xpc10nz==10'sd264/*264:xpc10nz*/) || (xpc10nz==10'sd272/*272:xpc10nz*/) || (xpc10nz==10'sd282/*282:xpc10nz*/) || (xpc10nz==10'sd290/*290:xpc10nz*/) || (xpc10nz==10'sd298/*298:xpc10nz*/) || (xpc10nz==10'sd306 /*306:xpc10nz*/) || (xpc10nz==10'sd327/*327:xpc10nz*/) || (xpc10nz==10'sd345/*345:xpc10nz*/) || (xpc10nz==10'sd363/*363:xpc10nz*/) || (xpc10nz==10'sd381/*381:xpc10nz*/)? 1'd1: 1'd0); A_FPD_CC_SCALbx46_ARH0_REN0 = ((xpc10nz==10'sd746/*746:xpc10nz*/) || (xpc10nz==10'sd741/*741:xpc10nz*/)) && (TMp1_V_0_GP<32'sh8 ); A_FPD_CC_SCALbx44_ARG0_REN0 = (xpc10nz==10'sd648/*648:xpc10nz*/) || (xpc10nz==10'sd640/*640:xpc10nz*/) || (xpc10nz==10'sd632/*632:xpc10nz*/) || (xpc10nz==10'sd624/*624:xpc10nz*/) || (xpc10nz==10'sd614/*614:xpc10nz*/) || (xpc10nz==10'sd606/*606:xpc10nz*/) || (xpc10nz==10'sd598 /*598:xpc10nz*/) || (xpc10nz==10'sd590/*590:xpc10nz*/) || (xpc10nz==10'sd580/*580:xpc10nz*/) || (xpc10nz==10'sd572/*572:xpc10nz*/) || (xpc10nz==10'sd564/*564:xpc10nz*/) || (xpc10nz==10'sd556/*556:xpc10nz*/) || (xpc10nz==10'sd546/*546:xpc10nz*/) || (xpc10nz==10'sd538 /*538:xpc10nz*/) || (xpc10nz==10'sd530/*530:xpc10nz*/) || (xpc10nz==10'sd522/*522:xpc10nz*/) || (xpc10nz==10'sd512/*512:xpc10nz*/) || (xpc10nz==10'sd504/*504:xpc10nz*/) || (xpc10nz==10'sd496/*496:xpc10nz*/) || (xpc10nz==10'sd488/*488:xpc10nz*/) || (xpc10nz==10'sd478 /*478:xpc10nz*/) || (xpc10nz==10'sd470/*470:xpc10nz*/) || (xpc10nz==10'sd462/*462:xpc10nz*/) || (xpc10nz==10'sd454/*454:xpc10nz*/) || (xpc10nz==10'sd444/*444:xpc10nz*/) || (xpc10nz==10'sd436/*436:xpc10nz*/) || (xpc10nz==10'sd428/*428:xpc10nz*/) || (xpc10nz==10'sd420 /*420:xpc10nz*/) || (xpc10nz==10'sd410/*410:xpc10nz*/) || (xpc10nz==10'sd402/*402:xpc10nz*/) || (xpc10nz==10'sd394/*394:xpc10nz*/) || (xpc10nz==10'sd386/*386:xpc10nz*/) || (xpc10nz==10'sd366/*366:xpc10nz*/) || (xpc10nz==10'sd348/*348:xpc10nz*/) || (xpc10nz==10'sd330 /*330:xpc10nz*/) || (xpc10nz==10'sd312/*312:xpc10nz*/) || (xpc10nz==10'sd321/*321:xpc10nz*/) || (xpc10nz==10'sd339/*339:xpc10nz*/) || (xpc10nz==10'sd357/*357:xpc10nz*/) || (xpc10nz==10'sd375/*375:xpc10nz*/) || (xpc10nz==10'sd390/*390:xpc10nz*/) || (xpc10nz==10'sd398 /*398:xpc10nz*/) || (xpc10nz==10'sd406/*406:xpc10nz*/) || (xpc10nz==10'sd414/*414:xpc10nz*/) || (xpc10nz==10'sd424/*424:xpc10nz*/) || (xpc10nz==10'sd432/*432:xpc10nz*/) || (xpc10nz==10'sd440/*440:xpc10nz*/) || (xpc10nz==10'sd448/*448:xpc10nz*/) || (xpc10nz==10'sd458 /*458:xpc10nz*/) || (xpc10nz==10'sd466/*466:xpc10nz*/) || (xpc10nz==10'sd474/*474:xpc10nz*/) || (xpc10nz==10'sd482/*482:xpc10nz*/) || (xpc10nz==10'sd492/*492:xpc10nz*/) || (xpc10nz==10'sd500/*500:xpc10nz*/) || (xpc10nz==10'sd508/*508:xpc10nz*/) || (xpc10nz==10'sd516 /*516:xpc10nz*/) || (xpc10nz==10'sd526/*526:xpc10nz*/) || (xpc10nz==10'sd534/*534:xpc10nz*/) || (xpc10nz==10'sd542/*542:xpc10nz*/) || (xpc10nz==10'sd550/*550:xpc10nz*/) || (xpc10nz==10'sd560/*560:xpc10nz*/) || (xpc10nz==10'sd568/*568:xpc10nz*/) || (xpc10nz==10'sd576 /*576:xpc10nz*/) || (xpc10nz==10'sd584/*584:xpc10nz*/) || (xpc10nz==10'sd594/*594:xpc10nz*/) || (xpc10nz==10'sd602/*602:xpc10nz*/) || (xpc10nz==10'sd610/*610:xpc10nz*/) || (xpc10nz==10'sd618/*618:xpc10nz*/) || (xpc10nz==10'sd628/*628:xpc10nz*/) || (xpc10nz==10'sd636 /*636:xpc10nz*/) || (xpc10nz==10'sd644/*644:xpc10nz*/) || (xpc10nz==10'sd652/*652:xpc10nz*/) || ((xpc10nz==10'sd762/*762:xpc10nz*/) || (xpc10nz==10'sd749/*749:xpc10nz*/)) && (TMm1_V_2_GP<32'sh8); A_FPD_CC_SCALbx46_ARH0_WEN0 = ((xpc10nz==10'sd762/*762:xpc10nz*/) || (xpc10nz==10'sd749/*749:xpc10nz*/)) && (TMm1_V_2_GP>=32'sh8 ); A_FPD_CC_SCALbx42_ARF0_REN0 = ((xpc10nz==10'sd800/*800:xpc10nz*/) || (xpc10nz==10'sd776/*776:xpc10nz*/)) && (TMm1_V_2_GP<32'sd8 ) || ((xpc10nz==10'sd749/*749:xpc10nz*/) || (xpc10nz==10'sd762/*762:xpc10nz*/)) && (TMm1_V_2_GP<32'sh8) || ((xpc10nz==10'sd773/*773:xpc10nz*/) || (xpc10nz==10'sd735/*735:xpc10nz*/)) && (TMp1_V_0_GP<32'sh8); A_FPD_CC_SCALbx42_ARF0_WEN0 = ((xpc10nz==10'sd810/*810:xpc10nz*/) || (xpc10nz==10'sd786/*786:xpc10nz*/)) && (TMm1_V_2_GP>=32'sd8 ); A_FPD_CC_SCALbx40_ARE0_REN0 = ((xpc10nz==10'sd776/*776:xpc10nz*/) || (xpc10nz==10'sd800/*800:xpc10nz*/)) && (TMm1_V_2_GP>=32'sd8 ) || ((xpc10nz==10'sd843/*843:xpc10nz*/) || (xpc10nz==10'sd825/*825:xpc10nz*/)) && (TMm1_V_2_GP<TMp1_V_0_GP) || ((xpc10nz==10'sd822 /*822:xpc10nz*/) || (xpc10nz==10'sd729/*729:xpc10nz*/)) && (TMp1_V_0_GP<32'sh8); A_FPD_CC_SCALbx38_ARD0_REN0 = ((TMp1_V_0_GP<32'sd8)? (xpc10nz==10'sd862/*862:xpc10nz*/) || (xpc10nz==10'sd723/*723:xpc10nz*/): (xpc10nz ==10'sd720/*720:xpc10nz*/) || (xpc10nz==10'sd859/*859:xpc10nz*/)) || ((xpc10nz==10'sd825/*825:xpc10nz*/) || (xpc10nz==10'sd843/*843:xpc10nz*/)) && (TMm1_V_2_GP>=TMp1_V_0_GP); A_FPD_CC_SCALbx40_ARE0_WEN0 = ((xpc10nz==10'sd721/*721:xpc10nz*/) || (xpc10nz==10'sd860/*860:xpc10nz*/)) && (TMp1_V_0_GP>=32'sd8 ) || ((xpc10nz==10'sd848/*848:xpc10nz*/) || (xpc10nz==10'sd830/*830:xpc10nz*/)) && (TMm1_V_2_GP>=TMp1_V_0_GP); A_FPD_CC_SCALbx38_ARD0_WEN0 = ((TMp1_V_0_GP<32'sd8)? (xpc10nz==10'sd717/*717:xpc10nz*/) || (xpc10nz==10'sd879/*879:xpc10nz*/): (xpc10nz ==10'sd865/*865:xpc10nz*/) || (xpc10nz==10'sd703/*703:xpc10nz*/)); A_FPD_CC_SCALbx36_ARC0_REN0 = ((xpc10nz==10'sd888/*888:xpc10nz*/) || (xpc10nz==10'sd882/*882:xpc10nz*/)) && (TMp1_V_0_GP<32'sd8 ); A_FPD_CC_SCALbx36_ARC0_WEN0 = ((xpc10nz==10'sd906/*906:xpc10nz*/) || (xpc10nz==10'sd893/*893:xpc10nz*/)) && (TMm1_V_2_GP>=32'sd8 ); A_FPD_CC_SCALbx32_ARA0_REN0 = ((xpc10nz==10'sd843/*843:xpc10nz*/) || (xpc10nz==10'sd825/*825:xpc10nz*/)) && (TMm1_V_2_GP<TMp1_V_0_GP ) || ((xpc10nz==10'sd906/*906:xpc10nz*/) || (xpc10nz==10'sd893/*893:xpc10nz*/)) && (TMm1_V_2_GP<32'sd8) || ((xpc10nz==10'sd923/*923:xpc10nz*/) || (xpc10nz==10'sd917/*917:xpc10nz*/)) && (TMp1_V_0_GP<32'sd8); A_FPD_CC_SCALbx34_ARB0_WEN0 = (xpc10nz==10'sd653/*653:xpc10nz*/) || (xpc10nz==10'sd645/*645:xpc10nz*/) || (xpc10nz==10'sd637/*637:xpc10nz*/) || (xpc10nz==10'sd629/*629:xpc10nz*/) || (xpc10nz==10'sd619/*619:xpc10nz*/) || (xpc10nz==10'sd611/*611:xpc10nz*/) || (xpc10nz==10'sd603 /*603:xpc10nz*/) || (xpc10nz==10'sd595/*595:xpc10nz*/) || (xpc10nz==10'sd585/*585:xpc10nz*/) || (xpc10nz==10'sd577/*577:xpc10nz*/) || (xpc10nz==10'sd569/*569:xpc10nz*/) || (xpc10nz==10'sd561/*561:xpc10nz*/) || (xpc10nz==10'sd551/*551:xpc10nz*/) || (xpc10nz==10'sd543 /*543:xpc10nz*/) || (xpc10nz==10'sd535/*535:xpc10nz*/) || (xpc10nz==10'sd527/*527:xpc10nz*/) || (xpc10nz==10'sd517/*517:xpc10nz*/) || (xpc10nz==10'sd509/*509:xpc10nz*/) || (xpc10nz==10'sd501/*501:xpc10nz*/) || (xpc10nz==10'sd493/*493:xpc10nz*/) || (xpc10nz==10'sd483 /*483:xpc10nz*/) || (xpc10nz==10'sd475/*475:xpc10nz*/) || (xpc10nz==10'sd467/*467:xpc10nz*/) || (xpc10nz==10'sd459/*459:xpc10nz*/) || (xpc10nz==10'sd449/*449:xpc10nz*/) || (xpc10nz==10'sd441/*441:xpc10nz*/) || (xpc10nz==10'sd433/*433:xpc10nz*/) || (xpc10nz==10'sd425 /*425:xpc10nz*/) || (xpc10nz==10'sd415/*415:xpc10nz*/) || (xpc10nz==10'sd407/*407:xpc10nz*/) || (xpc10nz==10'sd399/*399:xpc10nz*/) || (xpc10nz==10'sd391/*391:xpc10nz*/) || (xpc10nz==10'sd387/*387:xpc10nz*/) || (xpc10nz==10'sd395/*395:xpc10nz*/) || (xpc10nz==10'sd403 /*403:xpc10nz*/) || (xpc10nz==10'sd411/*411:xpc10nz*/) || (xpc10nz==10'sd421/*421:xpc10nz*/) || (xpc10nz==10'sd429/*429:xpc10nz*/) || (xpc10nz==10'sd437/*437:xpc10nz*/) || (xpc10nz==10'sd445/*445:xpc10nz*/) || (xpc10nz==10'sd455/*455:xpc10nz*/) || (xpc10nz==10'sd463 /*463:xpc10nz*/) || (xpc10nz==10'sd471/*471:xpc10nz*/) || (xpc10nz==10'sd479/*479:xpc10nz*/) || (xpc10nz==10'sd489/*489:xpc10nz*/) || (xpc10nz==10'sd497/*497:xpc10nz*/) || (xpc10nz==10'sd505/*505:xpc10nz*/) || (xpc10nz==10'sd513/*513:xpc10nz*/) || (xpc10nz==10'sd523 /*523:xpc10nz*/) || (xpc10nz==10'sd531/*531:xpc10nz*/) || (xpc10nz==10'sd539/*539:xpc10nz*/) || (xpc10nz==10'sd547/*547:xpc10nz*/) || (xpc10nz==10'sd557/*557:xpc10nz*/) || (xpc10nz==10'sd565/*565:xpc10nz*/) || (xpc10nz==10'sd573/*573:xpc10nz*/) || (xpc10nz==10'sd581 /*581:xpc10nz*/) || (xpc10nz==10'sd591/*591:xpc10nz*/) || (xpc10nz==10'sd599/*599:xpc10nz*/) || (xpc10nz==10'sd607/*607:xpc10nz*/) || (xpc10nz==10'sd615/*615:xpc10nz*/) || (xpc10nz==10'sd625/*625:xpc10nz*/) || (xpc10nz==10'sd633/*633:xpc10nz*/) || (xpc10nz==10'sd641 /*641:xpc10nz*/) || (xpc10nz==10'sd649/*649:xpc10nz*/) || (xpc10nz==10'sd945/*945:xpc10nz*/) || ((xpc10nz==10'sd979/*979:xpc10nz*/) || (xpc10nz==10'sd959/*959:xpc10nz*/)) && (lTMTMaV_1_GP<32'sd8); A_FPD_CC_SCALbx32_ARA0_WEN0 = (xpc10nz==10'sd947/*947:xpc10nz*/) || ((xpc10nz==10'sd982/*982:xpc10nz*/) || (xpc10nz==10'sd934/*934:xpc10nz*/)) && (TMm1_V_2_GP<32'sd8) || ((xpc10nz==10'sd688/*688:xpc10nz*/) || (xpc10nz==10'sd985/*985:xpc10nz*/)) && (TMp1_V_0_GP<32'sd8); A_FPD_CC_SCALbx34_ARB0_REN0 = ((TMm1_V_2_GP<32'sd8)? (xpc10nz==10'sd992/*992:xpc10nz*/) || (xpc10nz==10'sd961/*961:xpc10nz*/) || (xpc10nz==10'sd936/*936:xpc10nz*/) || (xpc10nz==10'sd906/*906:xpc10nz*/) || (xpc10nz==10'sd788/*788:xpc10nz*/) || (xpc10nz==10'sd812 /*812:xpc10nz*/) || (xpc10nz==10'sd893/*893:xpc10nz*/) || (xpc10nz==10'sd937/*937:xpc10nz*/) || (xpc10nz==10'sd962/*962:xpc10nz*/) || (xpc10nz==10'sd988/*988:xpc10nz*/): (xpc10nz==10'sd800/*800:xpc10nz*/) || (xpc10nz==10'sd776/*776:xpc10nz*/)) || (xpc10nz==10'sd678 /*678:xpc10nz*/) || (xpc10nz==10'sd672/*672:xpc10nz*/) || (xpc10nz==10'sd666/*666:xpc10nz*/) || (xpc10nz==10'sd660/*660:xpc10nz*/) || (xpc10nz==10'sd663/*663:xpc10nz*/) || (xpc10nz==10'sd669/*669:xpc10nz*/) || (xpc10nz==10'sd675/*675:xpc10nz*/) || (xpc10nz==10'sd681 /*681:xpc10nz*/) || ((xpc10nz==10'sd932/*932:xpc10nz*/) || (xpc10nz==10'sd926/*926:xpc10nz*/)) && (TMp1_V_0_GP<32'sd8) || ((xpc10nz ==10'sd970/*970:xpc10nz*/) || (xpc10nz==10'sd950/*950:xpc10nz*/) || (xpc10nz==10'sd951/*951:xpc10nz*/) || (xpc10nz==10'sd971/*971:xpc10nz*/)) && (lTMTMaV_1_GP<32'sd8); case (xpc10nz) 10'sd40/*40:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4024_0000_0000_0000; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd0; end 10'sd44/*44:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4026_0000_0000_0000; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd1; end 10'sd48/*48:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4028_3333_3333_3334; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd2; end 10'sd52/*52:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_402a_9eb8_51eb_8520; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd3; end 10'sd56/*56:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_402d_4831_26e9_78d7; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd4; end 10'sd60/*60:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4030_1ae7_d566_cf43; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd5; end 10'sd64/*64:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4031_b732_378a_b0ca; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd6; end 10'sd68/*68:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4033_7cb7_3d18_8f45; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd7; end 10'sd74/*74:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4035_6f96_5cce_3733; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd8; end 10'sd78/*78:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4037_9458_9949_3cb9; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd9; end 10'sd82/*82:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4039_effb_0f03_c2cc; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd10; end 10'sd86/*86:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_403c_87fa_9084_2314; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd11; end 10'sd90/*90:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_403f_6260_6bc4_8cfd; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd12; end 10'sd94/*94:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4041_42e8_3b45_b3f2; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd13; end 10'sd98/*98:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4042_fccc_4133_12be; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd14; end 10'sd102/*102:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4044_e2e0_ae1e_949e; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd15; end 10'sd108/*108:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4046_f990_bf88_09e2; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd16; end 10'sd112/*112:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4049_45b8_d2af_3e13; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd17; end 10'sd116/*116:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_404b_ccb1_b48d_9116; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd18; end 10'sd120/*120:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_404e_945d_1368_85ff; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd19; end 10'sd124/*124:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4050_d199_9779_7ce6; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd20; end 10'sd128/*128:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4052_8028_f36c_0964; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd21; end 10'sd132/*132:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4054_59c6_a55d_3d88; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd22; end 10'sd136/*136:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4056_62c0_e919_c3b0; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd23; end 10'sd142/*142:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4058_9fd4_339c_5742; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd24; end 10'sd146/*146:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_405b_1636_38c5_9330; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd25; end 10'sd150/*150:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_405d_cba2_0b3f_bb82; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd26; end 10'sd154/*154:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4060_6332_b963_0d88; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd27; end 10'sd158/*158:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4062_06b7_cbec_f549; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd28; end 10'sd162/*162:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4063_d430_9384_a76a; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd29; end 10'sd166/*166:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4065_cfcf_08ab_84f5; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd30; end 10'sd170/*170:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4067_fe30_8989_78a8; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd31; end 10'sd176/*176:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_406a_6468_974a_6b20; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd32; end 10'sd180/*180:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_406d_080c_a66b_75d7; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd33; end 10'sd184/*184:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_406f_ef41_1d76_34d4; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd34; end 10'sd188/*188:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4071_9063_d034_36a8; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd35; end 10'sd192/*192:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4073_5207_6506_3c20; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd36; end 10'sd196/*196:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4075_40a1_bbed_4224; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd37; end 10'sd200/*200:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4077_60b1_e851_c8c2; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd38; end 10'sd204/*204:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4079_b72a_1926_c33c; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd39; end 10'sd210/*210:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_407c_497b_1baa_a38f; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd40; end 10'sd214/*214:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_407f_1da1_04d5_4d84; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd41; end 10'sd218/*218:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4081_1d18_8f75_5109; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd42; end 10'sd222/*222:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4082_d334_9dcd_d924; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd43; end 10'sd226/*226:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4084_b520_472f_3ba8; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd44; end 10'sd230/*230:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4086_c73d_1b1a_5b39; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd45; end 10'sd234/*234:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4089_0e5c_d103_6459; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd46; end 10'sd238/*238:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_408b_8fcc_7f83_bb2f; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd47; end 10'sd244/*244:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_408e_5160_f2aa_811b; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd48; end 10'sd248/*248:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4090_acc2_1f10_fa36; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd49; end 10'sd252/*252:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4092_57a2_555f_79a2; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd50; end 10'sd256/*256:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4094_2d32_911c_38ff; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd51; end 10'sd260/*260:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4096_31b7_9f9f_0b7f; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd52; end 10'sd264/*264:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_4098_69e3_95fb_bfd9; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd53; end 10'sd268/*268:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_409a_dae0_be94_eca3; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd54; end 10'sd272/*272:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_409d_8a5d_9e70_9de7; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd55; end 10'sd278/*278:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_40a0_3f4d_1724_56d9; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd56; end 10'sd282/*282:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_40a1_df3b_330e_5f89; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd57; end 10'sd286/*286:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_40a3_a8c1_1e8f_cf7e; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd58; end 10'sd290/*290:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_40a5_a007_a19e_310b; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd59; end 10'sd294/*294:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_40a7_c9a1_fe94_6926; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd60; end 10'sd298/*298:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_40aa_2a98_9809_a6de; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd61; end 10'sd302/*302:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_40ac_c874_a73d_d128; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd62; end 10'sd306/*306:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = 64'h_40af_a94d_1e5d_9946; A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd63; end endcase if ((xpc10nz==10'sd312/*312:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd0; case (xpc10nz) 10'sd314/*314:xpc10nz*/: begin CVFPADDER10_A1 = Tlge0_9_V_4; CVFPADDER10_A0 = 64'h_4024_0000_0000_0000; end 10'sd318/*318:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = ((xpc10nz==10'sd318/*318:xpc10nz*/)? CVFPADDER10_FPRR: CVFPADDER10RRh10hold); A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd0; end endcase if ((xpc10nz==10'sd321/*321:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd9; case (xpc10nz) 10'sd323/*323:xpc10nz*/: begin CVFPADDER12_A1 = Tlge0_9_V_4; CVFPADDER12_A0 = 64'h_4024_0000_0000_0000; end 10'sd327/*327:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = ((xpc10nz==10'sd327/*327:xpc10nz*/)? CVFPADDER12_FPRR: CVFPADDER12RRh10hold); A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd9; end endcase if ((xpc10nz==10'sd330/*330:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd18; case (xpc10nz) 10'sd332/*332:xpc10nz*/: begin CVFPADDER14_A1 = Tlge0_9_V_4; CVFPADDER14_A0 = 64'h_4024_0000_0000_0000; end 10'sd336/*336:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = ((xpc10nz==10'sd336/*336:xpc10nz*/)? CVFPADDER14_FPRR: CVFPADDER14RRh10hold); A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd18; end endcase if ((xpc10nz==10'sd339/*339:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd27; case (xpc10nz) 10'sd341/*341:xpc10nz*/: begin CVFPADDER16_A1 = Tlge0_9_V_4; CVFPADDER16_A0 = 64'h_4024_0000_0000_0000; end 10'sd345/*345:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = ((xpc10nz==10'sd345/*345:xpc10nz*/)? CVFPADDER16_FPRR: CVFPADDER16RRh10hold); A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd27; end endcase if ((xpc10nz==10'sd348/*348:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd36; case (xpc10nz) 10'sd350/*350:xpc10nz*/: begin CVFPADDER18_A1 = Tlge0_9_V_4; CVFPADDER18_A0 = 64'h_4024_0000_0000_0000; end 10'sd354/*354:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = ((xpc10nz==10'sd354/*354:xpc10nz*/)? CVFPADDER18_FPRR: CVFPADDER18RRh10hold); A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd36; end endcase if ((xpc10nz==10'sd357/*357:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd45; case (xpc10nz) 10'sd359/*359:xpc10nz*/: begin CVFPADDER20_A1 = Tlge0_9_V_4; CVFPADDER20_A0 = 64'h_4024_0000_0000_0000; end 10'sd363/*363:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = ((xpc10nz==10'sd363/*363:xpc10nz*/)? CVFPADDER20_FPRR: CVFPADDER20RRh10hold); A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd45; end endcase if ((xpc10nz==10'sd366/*366:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd54; case (xpc10nz) 10'sd368/*368:xpc10nz*/: begin CVFPADDER20_A1 = Tlge0_9_V_4; CVFPADDER20_A0 = 64'h_4024_0000_0000_0000; end 10'sd372/*372:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = ((xpc10nz==10'sd372/*372:xpc10nz*/)? CVFPADDER20_FPRR: CVFPADDER20RRh10hold); A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd54; end endcase if ((xpc10nz==10'sd375/*375:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd63; case (xpc10nz) 10'sd377/*377:xpc10nz*/: begin CVFPADDER20_A1 = Tlge0_9_V_4; CVFPADDER20_A0 = 64'h_4024_0000_0000_0000; end 10'sd381/*381:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_WRD0 = ((xpc10nz==10'sd381/*381:xpc10nz*/)? CVFPADDER20_FPRR: CVFPADDER20RRh10hold); A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd63; end endcase if ((xpc10nz==10'sd386/*386:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd0; if ((xpc10nz==10'sd387/*387:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd387/*387:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd0; end if ((xpc10nz==10'sd390/*390:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd1; if ((xpc10nz==10'sd391/*391:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd391/*391:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd1; end if ((xpc10nz==10'sd394/*394:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd2; if ((xpc10nz==10'sd395/*395:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd395/*395:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd2; end if ((xpc10nz==10'sd398/*398:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd3; if ((xpc10nz==10'sd399/*399:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd399/*399:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd3; end if ((xpc10nz==10'sd402/*402:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd4; if ((xpc10nz==10'sd403/*403:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd403/*403:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd4; end if ((xpc10nz==10'sd406/*406:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd5; if ((xpc10nz==10'sd407/*407:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd407/*407:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd5; end if ((xpc10nz==10'sd410/*410:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd6; if ((xpc10nz==10'sd411/*411:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd411/*411:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd6; end if ((xpc10nz==10'sd414/*414:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd7; if ((xpc10nz==10'sd415/*415:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd415/*415:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd7; end if ((xpc10nz==10'sd420/*420:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd8; if ((xpc10nz==10'sd421/*421:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd421/*421:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd8; end if ((xpc10nz==10'sd424/*424:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd9; if ((xpc10nz==10'sd425/*425:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd425/*425:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd9; end if ((xpc10nz==10'sd428/*428:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd10; if ((xpc10nz==10'sd429/*429:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd429/*429:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd10; end if ((xpc10nz==10'sd432/*432:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd11; if ((xpc10nz==10'sd433/*433:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd433/*433:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd11; end if ((xpc10nz==10'sd436/*436:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd12; if ((xpc10nz==10'sd437/*437:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd437/*437:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd12; end if ((xpc10nz==10'sd440/*440:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd13; if ((xpc10nz==10'sd441/*441:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd441/*441:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd13; end if ((xpc10nz==10'sd444/*444:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd14; if ((xpc10nz==10'sd445/*445:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd445/*445:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd14; end if ((xpc10nz==10'sd448/*448:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd15; if ((xpc10nz==10'sd449/*449:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd449/*449:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd15; end if ((xpc10nz==10'sd454/*454:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd16; if ((xpc10nz==10'sd455/*455:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd455/*455:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd16; end if ((xpc10nz==10'sd458/*458:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd17; if ((xpc10nz==10'sd459/*459:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd459/*459:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd17; end if ((xpc10nz==10'sd462/*462:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd18; if ((xpc10nz==10'sd463/*463:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd463/*463:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd18; end if ((xpc10nz==10'sd466/*466:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd19; if ((xpc10nz==10'sd467/*467:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd467/*467:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd19; end if ((xpc10nz==10'sd470/*470:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd20; if ((xpc10nz==10'sd471/*471:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd471/*471:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd20; end if ((xpc10nz==10'sd474/*474:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd21; if ((xpc10nz==10'sd475/*475:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd475/*475:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd21; end if ((xpc10nz==10'sd478/*478:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd22; if ((xpc10nz==10'sd479/*479:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd479/*479:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd22; end if ((xpc10nz==10'sd482/*482:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd23; if ((xpc10nz==10'sd483/*483:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd483/*483:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd23; end if ((xpc10nz==10'sd488/*488:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd24; if ((xpc10nz==10'sd489/*489:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd489/*489:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd24; end if ((xpc10nz==10'sd492/*492:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd25; if ((xpc10nz==10'sd493/*493:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd493/*493:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd25; end if ((xpc10nz==10'sd496/*496:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd26; if ((xpc10nz==10'sd497/*497:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd497/*497:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd26; end if ((xpc10nz==10'sd500/*500:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd27; if ((xpc10nz==10'sd501/*501:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd501/*501:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd27; end if ((xpc10nz==10'sd504/*504:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd28; if ((xpc10nz==10'sd505/*505:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd505/*505:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd28; end if ((xpc10nz==10'sd508/*508:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd29; if ((xpc10nz==10'sd509/*509:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd509/*509:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd29; end if ((xpc10nz==10'sd512/*512:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd30; if ((xpc10nz==10'sd513/*513:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd513/*513:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd30; end if ((xpc10nz==10'sd516/*516:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd31; if ((xpc10nz==10'sd517/*517:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd517/*517:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd31; end if ((xpc10nz==10'sd522/*522:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd32; if ((xpc10nz==10'sd523/*523:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd523/*523:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd32; end if ((xpc10nz==10'sd526/*526:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd33; if ((xpc10nz==10'sd527/*527:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd527/*527:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd33; end if ((xpc10nz==10'sd530/*530:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd34; if ((xpc10nz==10'sd531/*531:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd531/*531:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd34; end if ((xpc10nz==10'sd534/*534:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd35; if ((xpc10nz==10'sd535/*535:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd535/*535:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd35; end if ((xpc10nz==10'sd538/*538:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd36; if ((xpc10nz==10'sd539/*539:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd539/*539:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd36; end if ((xpc10nz==10'sd542/*542:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd37; if ((xpc10nz==10'sd543/*543:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd543/*543:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd37; end if ((xpc10nz==10'sd546/*546:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd38; if ((xpc10nz==10'sd547/*547:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd547/*547:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd38; end if ((xpc10nz==10'sd550/*550:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd39; if ((xpc10nz==10'sd551/*551:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd551/*551:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd39; end if ((xpc10nz==10'sd556/*556:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd40; if ((xpc10nz==10'sd557/*557:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd557/*557:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd40; end if ((xpc10nz==10'sd560/*560:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd41; if ((xpc10nz==10'sd561/*561:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd561/*561:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd41; end if ((xpc10nz==10'sd564/*564:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd42; if ((xpc10nz==10'sd565/*565:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd565/*565:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd42; end if ((xpc10nz==10'sd568/*568:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd43; if ((xpc10nz==10'sd569/*569:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd569/*569:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd43; end if ((xpc10nz==10'sd572/*572:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd44; if ((xpc10nz==10'sd573/*573:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd573/*573:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd44; end if ((xpc10nz==10'sd576/*576:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd45; if ((xpc10nz==10'sd577/*577:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd577/*577:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd45; end if ((xpc10nz==10'sd580/*580:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd46; if ((xpc10nz==10'sd581/*581:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd581/*581:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd46; end if ((xpc10nz==10'sd584/*584:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd47; if ((xpc10nz==10'sd585/*585:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd585/*585:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd47; end if ((xpc10nz==10'sd590/*590:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd48; if ((xpc10nz==10'sd591/*591:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd591/*591:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd48; end if ((xpc10nz==10'sd594/*594:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd49; if ((xpc10nz==10'sd595/*595:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd595/*595:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd49; end if ((xpc10nz==10'sd598/*598:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd50; if ((xpc10nz==10'sd599/*599:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd599/*599:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd50; end if ((xpc10nz==10'sd602/*602:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd51; if ((xpc10nz==10'sd603/*603:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd603/*603:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd51; end if ((xpc10nz==10'sd606/*606:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd52; if ((xpc10nz==10'sd607/*607:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd607/*607:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd52; end if ((xpc10nz==10'sd610/*610:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd53; if ((xpc10nz==10'sd611/*611:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd611/*611:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd53; end if ((xpc10nz==10'sd614/*614:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd54; if ((xpc10nz==10'sd615/*615:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd615/*615:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd54; end if ((xpc10nz==10'sd618/*618:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd55; if ((xpc10nz==10'sd619/*619:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd619/*619:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd55; end if ((xpc10nz==10'sd624/*624:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd56; if ((xpc10nz==10'sd625/*625:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd625/*625:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd56; end if ((xpc10nz==10'sd628/*628:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd57; if ((xpc10nz==10'sd629/*629:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd629/*629:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd57; end if ((xpc10nz==10'sd632/*632:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd58; if ((xpc10nz==10'sd633/*633:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd633/*633:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd58; end if ((xpc10nz==10'sd636/*636:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd59; if ((xpc10nz==10'sd637/*637:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd637/*637:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd59; end if ((xpc10nz==10'sd640/*640:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd60; if ((xpc10nz==10'sd641/*641:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd641/*641:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd60; end if ((xpc10nz==10'sd644/*644:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd61; if ((xpc10nz==10'sd645/*645:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd645/*645:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd61; end if ((xpc10nz==10'sd648/*648:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd62; if ((xpc10nz==10'sd649/*649:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd649/*649:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd62; end if ((xpc10nz==10'sd652/*652:xpc10nz*/)) A_FPD_CC_SCALbx44_ARG0_AD0 = 6'd63; if ((xpc10nz==10'sd653/*653:xpc10nz*/)) begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd653/*653:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd63; end if ((xpc10nz==10'sd660/*660:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd0; if ((xpc10nz==10'sd663/*663:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd1; if ((xpc10nz==10'sd666/*666:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd2; if ((xpc10nz==10'sd669/*669:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd3; if ((xpc10nz==10'sd672/*672:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd4; if ((xpc10nz==10'sd675/*675:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd5; if ((xpc10nz==10'sd678/*678:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd6; if ((xpc10nz==10'sd681/*681:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = 6'd7; if ((TMp1_V_0_GP<32'sd8)) case (xpc10nz) 10'sd688/*688:xpc10nz*/: begin A_FPD_CC_SCALbx32_ARA0_WRD0 = 64'h_3ff0_0000_0000_0000; A_FPD_CC_SCALbx32_ARA0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP)+64'sh8*rtl_unsigned_extend1(TMp1_V_0_GP )); end 10'sd703/*703:xpc10nz*/: begin fpcvt10_arg = TMp1_V_0_GP; fpcvt12_arg = lTMTMaV_1_GP; end 10'sd706/*706:xpc10nz*/: begin CVFPMULTIPLIER10_A1 = ((xpc10nz==10'sd706/*706:xpc10nz*/)? fpcvt10_result: fpcvt10RRh10hold); CVFPMULTIPLIER10_A0 = 64'h_4000_0000_0000_0000; CVFPMULTIPLIER12_A1 = ((xpc10nz==10'sd706/*706:xpc10nz*/)? fpcvt12_result: fpcvt12RRh10hold); CVFPMULTIPLIER12_A0 = 64'h_4024_0000_0000_0000; end 10'sd709/*709:xpc10nz*/: begin CVFPADDER20_A1 = ((xpc10nz==10'sd709/*709:xpc10nz*/)? CVFPMULTIPLIER12_FPRR: CVFPMULTIPLIER12RRh10hold); CVFPADDER20_A0 = ((xpc10nz==10'sd709/*709:xpc10nz*/)? CVFPMULTIPLIER10_FPRR: CVFPMULTIPLIER10RRh10hold); end 10'sd713/*713:xpc10nz*/: begin CVFPADDER18_A1 = ((xpc10nz==10'sd713/*713:xpc10nz*/)? CVFPADDER20_FPRR: CVFPADDER20RRh10hold); CVFPADDER18_A0 = 64'h_3ff0_0000_0000_0000; end 10'sd717/*717:xpc10nz*/: begin A_FPD_CC_SCALbx38_ARD0_WRD0 = ((xpc10nz==10'sd717/*717:xpc10nz*/)? CVFPADDER18_FPRR: CVFPADDER18RRh10hold); A_FPD_CC_SCALbx38_ARD0_AD0 = TMp1_V_0_GP; end endcase else if ((xpc10nz==10'sd703/*703:xpc10nz*/)) begin A_FPD_CC_SCALbx38_ARD0_WRD0 = 64'h_4005_ae14_7ae1_47ae; A_FPD_CC_SCALbx38_ARD0_AD0 = 3'd7; end if ((TMp1_V_0_GP<32'sd8)) begin if ((xpc10nz==10'sd723/*723:xpc10nz*/)) A_FPD_CC_SCALbx38_ARD0_AD0 = TMp1_V_0_GP; end else begin if ((xpc10nz==10'sd720/*720:xpc10nz*/)) A_FPD_CC_SCALbx38_ARD0_AD0 = 3'd0; if ((xpc10nz==10'sd721/*721:xpc10nz*/)) begin A_FPD_CC_SCALbx40_ARE0_WRD0 = ((xpc10nz==10'sd721/*721:xpc10nz*/)? A_FPD_CC_SCALbx38_ARD0_RDD0: FPDCCSCALbx38ARD0RRh10hold ); A_FPD_CC_SCALbx40_ARE0_AD0 = 3'd0; end end if ((TMp1_V_0_GP<32'sd8)) begin if ((xpc10nz==10'sd729/*729:xpc10nz*/)) A_FPD_CC_SCALbx40_ARE0_AD0 = TMp1_V_0_GP; if ((xpc10nz==10'sd735/*735:xpc10nz*/)) A_FPD_CC_SCALbx42_ARF0_AD0 = TMp1_V_0_GP; if ((xpc10nz==10'sd741/*741:xpc10nz*/)) A_FPD_CC_SCALbx46_ARH0_AD0 = TMp1_V_0_GP; if ((xpc10nz==10'sd746/*746:xpc10nz*/)) A_FPD_CC_SCALbx46_ARH0_AD0 = TMp1_V_0_GP; end if ((TMm1_V_2_GP<32'sd8)) case (xpc10nz) 10'sd749/*749:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMm1_V_2_GP)+64'sh8*rtl_unsigned_extend1(TMp1_V_0_GP )); A_FPD_CC_SCALbx42_ARF0_AD0 = TMm1_V_2_GP; end 10'sd751/*751:xpc10nz*/: begin CVFPMULTIPLIER14_A1 = ((xpc10nz==10'sd751/*751:xpc10nz*/)? A_FPD_CC_SCALbx42_ARF0_RDD0: FPDCCSCALbx42ARF0RRh10hold ); CVFPMULTIPLIER14_A0 = ((xpc10nz==10'sd751/*751:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); end 10'sd754/*754:xpc10nz*/: begin CVFPADDER20_A1 = ((xpc10nz==10'sd754/*754:xpc10nz*/)? CVFPMULTIPLIER14_FPRR: CVFPMULTIPLIER14RRh10hold); CVFPADDER20_A0 = TMm1_V_1_GP; end endcase else if ((xpc10nz==10'sd749/*749:xpc10nz*/)) begin A_FPD_CC_SCALbx46_ARH0_WRD0 = TMm1_V_1_GP; A_FPD_CC_SCALbx46_ARH0_AD0 = TMp1_V_0_GP; end if ((TMm1_V_2_GP<32'sd8)) case (xpc10nz) 10'sd762/*762:xpc10nz*/: begin A_FPD_CC_SCALbx44_ARG0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMm1_V_2_GP)+64'sh8*rtl_unsigned_extend1(TMp1_V_0_GP )); A_FPD_CC_SCALbx42_ARF0_AD0 = TMm1_V_2_GP; end 10'sd764/*764:xpc10nz*/: begin CVFPMULTIPLIER16_A1 = ((xpc10nz==10'sd764/*764:xpc10nz*/)? A_FPD_CC_SCALbx42_ARF0_RDD0: FPDCCSCALbx42ARF0RRh10hold ); CVFPMULTIPLIER16_A0 = ((xpc10nz==10'sd764/*764:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold ); end 10'sd767/*767:xpc10nz*/: begin CVFPADDER20_A1 = ((xpc10nz==10'sd767/*767:xpc10nz*/)? CVFPMULTIPLIER16_FPRR: CVFPMULTIPLIER16RRh10hold); CVFPADDER20_A0 = TMm1_V_1_GP; end endcase else if ((xpc10nz==10'sd762/*762:xpc10nz*/)) begin A_FPD_CC_SCALbx46_ARH0_WRD0 = TMm1_V_1_GP; A_FPD_CC_SCALbx46_ARH0_AD0 = TMp1_V_0_GP; end if ((TMp1_V_0_GP<32'sd8)) begin if ((xpc10nz==10'sd773/*773:xpc10nz*/)) A_FPD_CC_SCALbx42_ARF0_AD0 = TMp1_V_0_GP; end if ((TMm1_V_2_GP<32'sd8)) begin if ((xpc10nz==10'sd776/*776:xpc10nz*/)) A_FPD_CC_SCALbx42_ARF0_AD0 = TMm1_V_2_GP; if ((xpc10nz==10'sd788/*788:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMm1_V_2_GP )+64'sh8*rtl_unsigned_extend1(TMp1_V_0_GP)); case (xpc10nz) 10'sd789/*789:xpc10nz*/: begin CVFPMULTIPLIER18_A1 = ((xpc10nz==10'sd789/*789:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0: FPDCCSCALbx34ARB0RRh10hold ); CVFPMULTIPLIER18_A0 = ((xpc10nz==10'sd788/*788:xpc10nz*/)? A_FPD_CC_SCALbx42_ARF0_RDD0: FPDCCSCALbx42ARF0RRh10hold ); end 10'sd792/*792:xpc10nz*/: begin CVFPADDER18_A1 = ((xpc10nz==10'sd792/*792:xpc10nz*/)? CVFPMULTIPLIER18_FPRR: CVFPMULTIPLIER18RRh10hold); CVFPADDER18_A0 = TMm1_V_1_GP; end endcase end else case (xpc10nz) 10'sd776/*776:xpc10nz*/: begin A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP)+64'sh8*rtl_unsigned_extend1(TMp1_V_0_GP )); A_FPD_CC_SCALbx40_ARE0_AD0 = TMp1_V_0_GP; end 10'sd777/*777:xpc10nz*/: begin CVFPADDER20_A1 = 64'sh_8000_0000_0000_0000^TMm1_V_1_GP; CVFPADDER20_A0 = ((xpc10nz==10'sd777/*777:xpc10nz*/)? A_FPD_CC_SCALbx40_ARE0_RDD0: FPDCCSCALbx40ARE0RRh10hold); end 10'sd781/*781:xpc10nz*/: begin CVFPDIVIDER10_DD = ((xpc10nz==10'sd777/*777:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0: FPDCCSCALbx34ARB0RRh10hold); CVFPDIVIDER10_NN = ((xpc10nz==10'sd781/*781:xpc10nz*/)? CVFPADDER20_FPRR: CVFPADDER20RRh10hold); end 10'sd786/*786:xpc10nz*/: begin A_FPD_CC_SCALbx42_ARF0_WRD0 = ((xpc10nz==10'sd786/*786:xpc10nz*/)? CVFPDIVIDER10_FPRR: CVFPDIVIDER10RRh10hold); A_FPD_CC_SCALbx42_ARF0_AD0 = TMp1_V_0_GP; end endcase if ((TMm1_V_2_GP<32'sd8)) begin if ((xpc10nz==10'sd800/*800:xpc10nz*/)) A_FPD_CC_SCALbx42_ARF0_AD0 = TMm1_V_2_GP; if ((xpc10nz==10'sd812/*812:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMm1_V_2_GP )+64'sh8*rtl_unsigned_extend1(TMp1_V_0_GP)); case (xpc10nz) 10'sd813/*813:xpc10nz*/: begin CVFPMULTIPLIER20_A1 = ((xpc10nz==10'sd813/*813:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0: FPDCCSCALbx34ARB0RRh10hold ); CVFPMULTIPLIER20_A0 = ((xpc10nz==10'sd812/*812:xpc10nz*/)? A_FPD_CC_SCALbx42_ARF0_RDD0: FPDCCSCALbx42ARF0RRh10hold ); end 10'sd816/*816:xpc10nz*/: begin CVFPADDER18_A1 = ((xpc10nz==10'sd816/*816:xpc10nz*/)? CVFPMULTIPLIER20_FPRR: CVFPMULTIPLIER20RRh10hold); CVFPADDER18_A0 = TMm1_V_1_GP; end endcase end else case (xpc10nz) 10'sd800/*800:xpc10nz*/: begin A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP)+64'sh8*rtl_unsigned_extend1(TMp1_V_0_GP )); A_FPD_CC_SCALbx40_ARE0_AD0 = TMp1_V_0_GP; end 10'sd801/*801:xpc10nz*/: begin CVFPADDER20_A1 = 64'sh_8000_0000_0000_0000^TMm1_V_1_GP; CVFPADDER20_A0 = ((xpc10nz==10'sd801/*801:xpc10nz*/)? A_FPD_CC_SCALbx40_ARE0_RDD0: FPDCCSCALbx40ARE0RRh10hold); end 10'sd805/*805:xpc10nz*/: begin CVFPDIVIDER12_DD = ((xpc10nz==10'sd801/*801:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0: FPDCCSCALbx34ARB0RRh10hold); CVFPDIVIDER12_NN = ((xpc10nz==10'sd805/*805:xpc10nz*/)? CVFPADDER20_FPRR: CVFPADDER20RRh10hold); end 10'sd810/*810:xpc10nz*/: begin A_FPD_CC_SCALbx42_ARF0_WRD0 = ((xpc10nz==10'sd810/*810:xpc10nz*/)? CVFPDIVIDER12_FPRR: CVFPDIVIDER12RRh10hold); A_FPD_CC_SCALbx42_ARF0_AD0 = TMp1_V_0_GP; end endcase if ((TMp1_V_0_GP<32'sd8)) begin if ((xpc10nz==10'sd822/*822:xpc10nz*/)) A_FPD_CC_SCALbx40_ARE0_AD0 = TMp1_V_0_GP; end if ((TMm1_V_2_GP<TMp1_V_0_GP)) case (xpc10nz) 10'sd825/*825:xpc10nz*/: begin A_FPD_CC_SCALbx32_ARA0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMm1_V_2_GP)+64'sh8*rtl_unsigned_extend1(TMp1_V_0_GP )); A_FPD_CC_SCALbx40_ARE0_AD0 = TMm1_V_2_GP; end 10'sd832/*832:xpc10nz*/: begin CVFPMULTIPLIER22_A1 = ((xpc10nz==10'sd832/*832:xpc10nz*/)? A_FPD_CC_SCALbx32_ARA0_RDD0: FPDCCSCALbx32ARA0RRh10hold ); CVFPMULTIPLIER22_A0 = ((xpc10nz==10'sd832/*832:xpc10nz*/)? A_FPD_CC_SCALbx40_ARE0_RDD0: FPDCCSCALbx40ARE0RRh10hold ); end 10'sd835/*835:xpc10nz*/: begin CVFPADDER18_A1 = ((xpc10nz==10'sd835/*835:xpc10nz*/)? CVFPMULTIPLIER22_FPRR: CVFPMULTIPLIER22RRh10hold); CVFPADDER18_A0 = TMm1_V_1_GP; end endcase else case (xpc10nz) 10'sd825/*825:xpc10nz*/: A_FPD_CC_SCALbx38_ARD0_AD0 = TMp1_V_0_GP; 10'sd826/*826:xpc10nz*/: begin CVFPADDER20_A1 = 64'sh_8000_0000_0000_0000^TMm1_V_1_GP; CVFPADDER20_A0 = ((xpc10nz==10'sd826/*826:xpc10nz*/)? A_FPD_CC_SCALbx38_ARD0_RDD0: FPDCCSCALbx38ARD0RRh10hold); end 10'sd830/*830:xpc10nz*/: begin A_FPD_CC_SCALbx40_ARE0_WRD0 = ((xpc10nz==10'sd830/*830:xpc10nz*/)? CVFPADDER20_FPRR: CVFPADDER20RRh10hold); A_FPD_CC_SCALbx40_ARE0_AD0 = TMp1_V_0_GP; end endcase if ((TMm1_V_2_GP<TMp1_V_0_GP)) case (xpc10nz) 10'sd843/*843:xpc10nz*/: begin A_FPD_CC_SCALbx32_ARA0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMm1_V_2_GP)+64'sh8*rtl_unsigned_extend1(TMp1_V_0_GP )); A_FPD_CC_SCALbx40_ARE0_AD0 = TMm1_V_2_GP; end 10'sd850/*850:xpc10nz*/: begin CVFPMULTIPLIER24_A1 = ((xpc10nz==10'sd850/*850:xpc10nz*/)? A_FPD_CC_SCALbx32_ARA0_RDD0: FPDCCSCALbx32ARA0RRh10hold ); CVFPMULTIPLIER24_A0 = ((xpc10nz==10'sd850/*850:xpc10nz*/)? A_FPD_CC_SCALbx40_ARE0_RDD0: FPDCCSCALbx40ARE0RRh10hold ); end 10'sd853/*853:xpc10nz*/: begin CVFPADDER18_A1 = ((xpc10nz==10'sd853/*853:xpc10nz*/)? CVFPMULTIPLIER24_FPRR: CVFPMULTIPLIER24RRh10hold); CVFPADDER18_A0 = TMm1_V_1_GP; end endcase else case (xpc10nz) 10'sd843/*843:xpc10nz*/: A_FPD_CC_SCALbx38_ARD0_AD0 = TMp1_V_0_GP; 10'sd844/*844:xpc10nz*/: begin CVFPADDER20_A1 = 64'sh_8000_0000_0000_0000^TMm1_V_1_GP; CVFPADDER20_A0 = ((xpc10nz==10'sd844/*844:xpc10nz*/)? A_FPD_CC_SCALbx38_ARD0_RDD0: FPDCCSCALbx38ARD0RRh10hold); end 10'sd848/*848:xpc10nz*/: begin A_FPD_CC_SCALbx40_ARE0_WRD0 = ((xpc10nz==10'sd848/*848:xpc10nz*/)? CVFPADDER20_FPRR: CVFPADDER20RRh10hold); A_FPD_CC_SCALbx40_ARE0_AD0 = TMp1_V_0_GP; end endcase if ((TMp1_V_0_GP<32'sd8)) begin if ((xpc10nz==10'sd862/*862:xpc10nz*/)) A_FPD_CC_SCALbx38_ARD0_AD0 = TMp1_V_0_GP; end else begin if ((xpc10nz==10'sd859/*859:xpc10nz*/)) A_FPD_CC_SCALbx38_ARD0_AD0 = 3'd0; if ((xpc10nz==10'sd860/*860:xpc10nz*/)) begin A_FPD_CC_SCALbx40_ARE0_WRD0 = ((xpc10nz==10'sd860/*860:xpc10nz*/)? A_FPD_CC_SCALbx38_ARD0_RDD0: FPDCCSCALbx38ARD0RRh10hold ); A_FPD_CC_SCALbx40_ARE0_AD0 = 3'd0; end end if ((TMp1_V_0_GP<32'sd8)) case (xpc10nz) 10'sd865/*865:xpc10nz*/: begin fpcvt14_arg = TMp1_V_0_GP; fpcvt16_arg = lTMTMaV_1_GP; end 10'sd868/*868:xpc10nz*/: begin CVFPMULTIPLIER26_A1 = ((xpc10nz==10'sd868/*868:xpc10nz*/)? fpcvt14_result: fpcvt14RRh10hold); CVFPMULTIPLIER26_A0 = 64'h_4000_0000_0000_0000; CVFPMULTIPLIER28_A1 = ((xpc10nz==10'sd868/*868:xpc10nz*/)? fpcvt16_result: fpcvt16RRh10hold); CVFPMULTIPLIER28_A0 = 64'h_4024_0000_0000_0000; end 10'sd871/*871:xpc10nz*/: begin CVFPADDER20_A1 = ((xpc10nz==10'sd871/*871:xpc10nz*/)? CVFPMULTIPLIER28_FPRR: CVFPMULTIPLIER28RRh10hold); CVFPADDER20_A0 = ((xpc10nz==10'sd871/*871:xpc10nz*/)? CVFPMULTIPLIER26_FPRR: CVFPMULTIPLIER26RRh10hold); end 10'sd875/*875:xpc10nz*/: begin CVFPADDER18_A1 = ((xpc10nz==10'sd875/*875:xpc10nz*/)? CVFPADDER20_FPRR: CVFPADDER20RRh10hold); CVFPADDER18_A0 = 64'h_3ff0_0000_0000_0000; end 10'sd879/*879:xpc10nz*/: begin A_FPD_CC_SCALbx38_ARD0_WRD0 = ((xpc10nz==10'sd879/*879:xpc10nz*/)? CVFPADDER18_FPRR: CVFPADDER18RRh10hold); A_FPD_CC_SCALbx38_ARD0_AD0 = TMp1_V_0_GP; end endcase else if ((xpc10nz==10'sd865/*865:xpc10nz*/)) begin A_FPD_CC_SCALbx38_ARD0_WRD0 = 64'h_4005_ae14_7ae1_47ae; A_FPD_CC_SCALbx38_ARD0_AD0 = 3'd7; end if ((TMp1_V_0_GP<32'sd8)) begin if ((xpc10nz==10'sd882/*882:xpc10nz*/)) A_FPD_CC_SCALbx36_ARC0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP )+64'sh8*rtl_unsigned_extend1(lTMTMaV_1_GP)); if ((xpc10nz==10'sd888/*888:xpc10nz*/)) A_FPD_CC_SCALbx36_ARC0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP )+64'sh8*rtl_unsigned_extend1(lTMTMaV_1_GP)); end if ((TMm1_V_2_GP<32'sd8)) case (xpc10nz) 10'sd893/*893:xpc10nz*/: begin A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP)+64'sh8*rtl_unsigned_extend1(TMm1_V_2_GP )); A_FPD_CC_SCALbx32_ARA0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMm1_V_2_GP)+64'sh8*rtl_unsigned_extend1(lTMTMaV_1_GP )); end 10'sd895/*895:xpc10nz*/: begin CVFPMULTIPLIER28_A1 = ((xpc10nz==10'sd895/*895:xpc10nz*/)? A_FPD_CC_SCALbx32_ARA0_RDD0: FPDCCSCALbx32ARA0RRh10hold ); CVFPMULTIPLIER28_A0 = ((xpc10nz==10'sd895/*895:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0: FPDCCSCALbx34ARB0RRh10hold ); end 10'sd898/*898:xpc10nz*/: begin CVFPADDER20_A1 = ((xpc10nz==10'sd898/*898:xpc10nz*/)? CVFPMULTIPLIER28_FPRR: CVFPMULTIPLIER28RRh10hold); CVFPADDER20_A0 = TMm1_V_1_GP; end endcase else if ((xpc10nz==10'sd893/*893:xpc10nz*/)) begin A_FPD_CC_SCALbx36_ARC0_WRD0 = TMm1_V_1_GP; A_FPD_CC_SCALbx36_ARC0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP)+64'sh8*rtl_unsigned_extend1(lTMTMaV_1_GP )); end if ((TMm1_V_2_GP<32'sd8)) case (xpc10nz) 10'sd906/*906:xpc10nz*/: begin A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP)+64'sh8*rtl_unsigned_extend1(TMm1_V_2_GP )); A_FPD_CC_SCALbx32_ARA0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMm1_V_2_GP)+64'sh8*rtl_unsigned_extend1(lTMTMaV_1_GP )); end 10'sd908/*908:xpc10nz*/: begin CVFPMULTIPLIER28_A1 = ((xpc10nz==10'sd908/*908:xpc10nz*/)? A_FPD_CC_SCALbx32_ARA0_RDD0: FPDCCSCALbx32ARA0RRh10hold ); CVFPMULTIPLIER28_A0 = ((xpc10nz==10'sd908/*908:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0: FPDCCSCALbx34ARB0RRh10hold ); end 10'sd911/*911:xpc10nz*/: begin CVFPADDER20_A1 = ((xpc10nz==10'sd911/*911:xpc10nz*/)? CVFPMULTIPLIER28_FPRR: CVFPMULTIPLIER28RRh10hold); CVFPADDER20_A0 = TMm1_V_1_GP; end endcase else if ((xpc10nz==10'sd906/*906:xpc10nz*/)) begin A_FPD_CC_SCALbx36_ARC0_WRD0 = TMm1_V_1_GP; A_FPD_CC_SCALbx36_ARC0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP)+64'sh8*rtl_unsigned_extend1(lTMTMaV_1_GP )); end if ((TMp1_V_0_GP<32'sd8)) begin if ((xpc10nz==10'sd917/*917:xpc10nz*/)) A_FPD_CC_SCALbx32_ARA0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP )+64'sh8*rtl_unsigned_extend1(lTMTMaV_1_GP)); if ((xpc10nz==10'sd923/*923:xpc10nz*/)) A_FPD_CC_SCALbx32_ARA0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP )+64'sh8*rtl_unsigned_extend1(lTMTMaV_1_GP)); if ((xpc10nz==10'sd926/*926:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP )+64'sh8*rtl_unsigned_extend1(lTMTMaV_1_GP)); if ((xpc10nz==10'sd932/*932:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP )+64'sh8*rtl_unsigned_extend1(lTMTMaV_1_GP)); end if ((TMm1_V_2_GP<32'sd8)) begin if ((xpc10nz==10'sd934/*934:xpc10nz*/)) begin A_FPD_CC_SCALbx32_ARA0_WRD0 = 64'h_3ff0_0000_0000_0000; A_FPD_CC_SCALbx32_ARA0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMm1_V_2_GP)+64'sh8*rtl_unsigned_extend1(TMm1_V_2_GP )); end if ((xpc10nz==10'sd936/*936:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP )+64'sh8*rtl_unsigned_extend1(TMm1_V_2_GP)); if ((xpc10nz==10'sd937/*937:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP )+64'sh8*rtl_unsigned_extend1(TMp1_V_0_GP)); if ((xpc10nz==10'sd938/*938:xpc10nz*/)) begin CVFPDIVIDER14_DD = ((xpc10nz==10'sd938/*938:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0: FPDCCSCALbx34ARB0RRh12hold ); CVFPDIVIDER14_NN = ((xpc10nz==10'sd937/*937:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0: FPDCCSCALbx34ARB0RRh10hold ); end end case (xpc10nz) 10'sd945/*945:xpc10nz*/: begin A_FPD_CC_SCALbx34_ARB0_WRD0 = 64'h0; A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP)+64'sh8*rtl_unsigned_extend1(TMm1_V_2_GP )); end 10'sd947/*947:xpc10nz*/: begin A_FPD_CC_SCALbx32_ARA0_WRD0 = TMm1_V_1_GP; A_FPD_CC_SCALbx32_ARA0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP)+64'sh8*rtl_unsigned_extend1(TMm1_V_2_GP )); end endcase if ((lTMTMaV_1_GP<32'sd8)) begin if ((xpc10nz==10'sd950/*950:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(lTMTMaV_1_GP )+64'sh8*rtl_unsigned_extend1(TMm1_V_2_GP)); if ((xpc10nz==10'sd951/*951:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(lTMTMaV_1_GP )+64'sh8*rtl_unsigned_extend1(TMp1_V_0_GP)); case (xpc10nz) 10'sd952/*952:xpc10nz*/: begin CVFPMULTIPLIER28_A1 = 64'sh_8000_0000_0000_0000^TMm1_V_1_GP; CVFPMULTIPLIER28_A0 = ((xpc10nz==10'sd952/*952:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0: FPDCCSCALbx34ARB0RRh10hold ); end 10'sd955/*955:xpc10nz*/: begin CVFPADDER20_A1 = ((xpc10nz==10'sd955/*955:xpc10nz*/)? CVFPMULTIPLIER28_FPRR: CVFPMULTIPLIER28RRh10hold); CVFPADDER20_A0 = ((xpc10nz==10'sd951/*951:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0: FPDCCSCALbx34ARB0RRh12hold); end 10'sd959/*959:xpc10nz*/: begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd959/*959:xpc10nz*/)? CVFPADDER20_FPRR: CVFPADDER20RRh10hold); A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(lTMTMaV_1_GP)+64'sh8*rtl_unsigned_extend1(TMm1_V_2_GP )); end endcase end if ((TMm1_V_2_GP<32'sd8)) begin if ((xpc10nz==10'sd961/*961:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP )+64'sh8*rtl_unsigned_extend1(TMm1_V_2_GP)); if ((xpc10nz==10'sd962/*962:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP )+64'sh8*rtl_unsigned_extend1(TMp1_V_0_GP)); if ((xpc10nz==10'sd963/*963:xpc10nz*/)) begin CVFPDIVIDER16_DD = ((xpc10nz==10'sd963/*963:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0: FPDCCSCALbx34ARB0RRh10hold ); CVFPDIVIDER16_NN = ((xpc10nz==10'sd962/*962:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0: FPDCCSCALbx34ARB0RRh12hold ); end end if ((lTMTMaV_1_GP<32'sd8)) begin if ((xpc10nz==10'sd970/*970:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(lTMTMaV_1_GP )+64'sh8*rtl_unsigned_extend1(TMm1_V_2_GP)); if ((xpc10nz==10'sd971/*971:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(lTMTMaV_1_GP )+64'sh8*rtl_unsigned_extend1(TMp1_V_0_GP)); case (xpc10nz) 10'sd972/*972:xpc10nz*/: begin CVFPMULTIPLIER28_A1 = 64'sh_8000_0000_0000_0000^TMm1_V_1_GP; CVFPMULTIPLIER28_A0 = ((xpc10nz==10'sd972/*972:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0: FPDCCSCALbx34ARB0RRh10hold ); end 10'sd975/*975:xpc10nz*/: begin CVFPADDER20_A1 = ((xpc10nz==10'sd975/*975:xpc10nz*/)? CVFPMULTIPLIER28_FPRR: CVFPMULTIPLIER28RRh10hold); CVFPADDER20_A0 = ((xpc10nz==10'sd971/*971:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0: FPDCCSCALbx34ARB0RRh12hold); end 10'sd979/*979:xpc10nz*/: begin A_FPD_CC_SCALbx34_ARB0_WRD0 = ((xpc10nz==10'sd979/*979:xpc10nz*/)? CVFPADDER20_FPRR: CVFPADDER20RRh10hold); A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(lTMTMaV_1_GP)+64'sh8*rtl_unsigned_extend1(TMm1_V_2_GP )); end endcase end if ((TMm1_V_2_GP<32'sd8) && (xpc10nz==10'sd982/*982:xpc10nz*/)) begin A_FPD_CC_SCALbx32_ARA0_WRD0 = 64'h_3ff0_0000_0000_0000; A_FPD_CC_SCALbx32_ARA0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMm1_V_2_GP)+64'sh8*rtl_unsigned_extend1(TMm1_V_2_GP )); end if ((TMp1_V_0_GP<32'sd8) && (xpc10nz==10'sd985/*985:xpc10nz*/)) begin A_FPD_CC_SCALbx32_ARA0_WRD0 = 64'h_3ff0_0000_0000_0000; A_FPD_CC_SCALbx32_ARA0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMp1_V_0_GP)+64'sh8*rtl_unsigned_extend1(TMp1_V_0_GP )); end if ((TMm1_V_2_GP<32'sd8)) begin if ((xpc10nz==10'sd988/*988:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMm1_V_2_GP )+64'sh8*rtl_unsigned_extend1(TMp1_V_0_GP)); if ((xpc10nz==10'sd992/*992:xpc10nz*/)) A_FPD_CC_SCALbx34_ARB0_AD0 = rtl_signed_bitextract0(rtl_unsigned_extend1(TMm1_V_2_GP )+64'sh8*rtl_unsigned_extend1(TMp1_V_0_GP)); end if ((lTMTMaV_1_GP>=32'sd3)) begin if ((xpc10nz==10'sd744/*744:xpc10nz*/)) KppWaypoint0 = "ThreeTestsFinished"; if ((xpc10nz==10'sd700/*700:xpc10nz*/)) KppWaypoint0 = "ThreeTestsFinished"; end if ((xpc10nz==10'sd698/*698:xpc10nz*/)) KppWaypoint0 = "Coefficients Created"; if ((xpc10nz==10'sd37/*37:xpc10nz*/)) KppWaypoint0 = "Start"; end always @(posedge clk ) begin //Start structure HPR lu-decomp if (reset) begin lTMTMaV_1_GP <= 32'd0; Tlge0_9_V_4 <= 64'd0; TMp1_V_0_GP <= 32'd0; TMm1_V_2_GP <= 32'd0; TMm1_V_1_GP <= 64'd0; CVFPADDER10RRh10hold <= 64'd0; CVFPADDER10RRh10shot1 <= 1'd0; CVFPADDER10RRh10shot2 <= 1'd0; CVFPADDER10RRh10shot3 <= 1'd0; CVFPADDER12RRh10hold <= 64'd0; CVFPADDER12RRh10shot1 <= 1'd0; CVFPADDER12RRh10shot2 <= 1'd0; CVFPADDER12RRh10shot3 <= 1'd0; CVFPADDER14RRh10hold <= 64'd0; CVFPADDER14RRh10shot1 <= 1'd0; CVFPADDER14RRh10shot2 <= 1'd0; CVFPADDER14RRh10shot3 <= 1'd0; CVFPADDER16RRh10hold <= 64'd0; CVFPADDER16RRh10shot1 <= 1'd0; CVFPADDER16RRh10shot2 <= 1'd0; CVFPADDER16RRh10shot3 <= 1'd0; fpcvt10RRh10hold <= 64'd0; fpcvt10RRh10shot1 <= 1'd0; fpcvt12RRh10hold <= 64'd0; fpcvt12RRh10shot1 <= 1'd0; CVFPMULTIPLIER10RRh10hold <= 64'd0; CVFPMULTIPLIER10RRh10shot1 <= 1'd0; CVFPMULTIPLIER10RRh10shot2 <= 1'd0; CVFPMULTIPLIER12RRh10hold <= 64'd0; CVFPMULTIPLIER12RRh10shot1 <= 1'd0; CVFPMULTIPLIER12RRh10shot2 <= 1'd0; FPDCCSCALbx46ARH0RRh10hold <= 64'd0; CVFPMULTIPLIER14RRh10hold <= 64'd0; CVFPMULTIPLIER14RRh10shot1 <= 1'd0; CVFPMULTIPLIER14RRh10shot2 <= 1'd0; FPDCCSCALbx44ARG0RRh10hold <= 64'd0; CVFPMULTIPLIER16RRh10hold <= 64'd0; CVFPMULTIPLIER16RRh10shot1 <= 1'd0; CVFPMULTIPLIER16RRh10shot2 <= 1'd0; CVFPMULTIPLIER18RRh10hold <= 64'd0; CVFPMULTIPLIER18RRh10shot1 <= 1'd0; CVFPMULTIPLIER18RRh10shot2 <= 1'd0; CVFPDIVIDER10RRh10hold <= 64'd0; CVFPDIVIDER10RRh10shot1 <= 1'd0; CVFPDIVIDER10RRh10shot2 <= 1'd0; CVFPDIVIDER10RRh10shot3 <= 1'd0; CVFPDIVIDER10RRh10shot4 <= 1'd0; FPDCCSCALbx42ARF0RRh10hold <= 64'd0; CVFPMULTIPLIER20RRh10hold <= 64'd0; CVFPMULTIPLIER20RRh10shot1 <= 1'd0; CVFPMULTIPLIER20RRh10shot2 <= 1'd0; CVFPDIVIDER12RRh10hold <= 64'd0; CVFPDIVIDER12RRh10shot1 <= 1'd0; CVFPDIVIDER12RRh10shot2 <= 1'd0; CVFPDIVIDER12RRh10shot3 <= 1'd0; CVFPDIVIDER12RRh10shot4 <= 1'd0; CVFPMULTIPLIER22RRh10hold <= 64'd0; CVFPMULTIPLIER22RRh10shot1 <= 1'd0; CVFPMULTIPLIER22RRh10shot2 <= 1'd0; FPDCCSCALbx40ARE0RRh10hold <= 64'd0; CVFPMULTIPLIER24RRh10hold <= 64'd0; CVFPMULTIPLIER24RRh10shot1 <= 1'd0; CVFPMULTIPLIER24RRh10shot2 <= 1'd0; FPDCCSCALbx38ARD0RRh10hold <= 64'd0; fpcvt14RRh10hold <= 64'd0; fpcvt14RRh10shot1 <= 1'd0; fpcvt16RRh10hold <= 64'd0; fpcvt16RRh10shot1 <= 1'd0; CVFPMULTIPLIER26RRh10hold <= 64'd0; CVFPMULTIPLIER26RRh10shot1 <= 1'd0; CVFPMULTIPLIER26RRh10shot2 <= 1'd0; CVFPADDER18RRh10hold <= 64'd0; CVFPADDER18RRh10shot1 <= 1'd0; CVFPADDER18RRh10shot2 <= 1'd0; CVFPADDER18RRh10shot3 <= 1'd0; FPDCCSCALbx36ARC0RRh10hold <= 64'd0; FPDCCSCALbx32ARA0RRh10hold <= 64'd0; CVFPDIVIDER14RRh10hold <= 64'd0; CVFPDIVIDER14RRh10shot1 <= 1'd0; CVFPDIVIDER14RRh10shot2 <= 1'd0; CVFPDIVIDER14RRh10shot3 <= 1'd0; CVFPDIVIDER14RRh10shot4 <= 1'd0; CVFPDIVIDER16RRh10hold <= 64'd0; CVFPDIVIDER16RRh10shot1 <= 1'd0; CVFPDIVIDER16RRh10shot2 <= 1'd0; CVFPDIVIDER16RRh10shot3 <= 1'd0; CVFPDIVIDER16RRh10shot4 <= 1'd0; FPDCCSCALbx34ARB0RRh10hold <= 64'd0; CVFPMULTIPLIER28RRh10hold <= 64'd0; CVFPMULTIPLIER28RRh10shot1 <= 1'd0; CVFPMULTIPLIER28RRh10shot2 <= 1'd0; CVFPADDER20RRh10hold <= 64'd0; CVFPADDER20RRh10shot1 <= 1'd0; CVFPADDER20RRh10shot2 <= 1'd0; CVFPADDER20RRh10shot3 <= 1'd0; FPDCCSCALbx34ARB0RRh12hold <= 64'd0; FPDCCSCALbx34ARB0RRh12shot0 <= 1'd0; CVFPADDER20RRh10shot0 <= 1'd0; CVFPMULTIPLIER28RRh10shot0 <= 1'd0; FPDCCSCALbx34ARB0RRh10shot0 <= 1'd0; CVFPDIVIDER16RRh10shot0 <= 1'd0; CVFPDIVIDER14RRh10shot0 <= 1'd0; FPDCCSCALbx32ARA0RRh10shot0 <= 1'd0; FPDCCSCALbx36ARC0RRh10shot0 <= 1'd0; CVFPADDER18RRh10shot0 <= 1'd0; CVFPMULTIPLIER26RRh10shot0 <= 1'd0; fpcvt16RRh10shot0 <= 1'd0; fpcvt14RRh10shot0 <= 1'd0; FPDCCSCALbx38ARD0RRh10shot0 <= 1'd0; CVFPMULTIPLIER24RRh10shot0 <= 1'd0; FPDCCSCALbx40ARE0RRh10shot0 <= 1'd0; CVFPMULTIPLIER22RRh10shot0 <= 1'd0; CVFPDIVIDER12RRh10shot0 <= 1'd0; CVFPMULTIPLIER20RRh10shot0 <= 1'd0; FPDCCSCALbx42ARF0RRh10shot0 <= 1'd0; CVFPDIVIDER10RRh10shot0 <= 1'd0; CVFPMULTIPLIER18RRh10shot0 <= 1'd0; CVFPMULTIPLIER16RRh10shot0 <= 1'd0; FPDCCSCALbx44ARG0RRh10shot0 <= 1'd0; CVFPMULTIPLIER14RRh10shot0 <= 1'd0; FPDCCSCALbx46ARH0RRh10shot0 <= 1'd0; CVFPMULTIPLIER12RRh10shot0 <= 1'd0; CVFPMULTIPLIER10RRh10shot0 <= 1'd0; fpcvt12RRh10shot0 <= 1'd0; fpcvt10RRh10shot0 <= 1'd0; CVFPADDER16RRh10shot0 <= 1'd0; CVFPADDER14RRh10shot0 <= 1'd0; CVFPADDER12RRh10shot0 <= 1'd0; CVFPADDER10RRh10shot0 <= 1'd0; xpc10nz <= 10'd0; end else begin if ((TMm1_V_2_GP>=32'sd8)) begin if ((xpc10nz==10'sd992/*992:xpc10nz*/)) $display(""); end else if ((xpc10nz==10'sd993/*993:xpc10nz*/)) $write(" %F ", $bitstoreal(((xpc10nz==10'sd993/*993:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0 : FPDCCSCALbx34ARB0RRh12hold))); if ((TMm1_V_2_GP>=32'sd8)) begin if ((xpc10nz==10'sd988/*988:xpc10nz*/)) $display(""); end else if ((xpc10nz==10'sd989/*989:xpc10nz*/)) $write(" %F ", $bitstoreal(((xpc10nz==10'sd989/*989:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0 : FPDCCSCALbx34ARB0RRh12hold))); if ((TMp1_V_0_GP>=32'sd8)) case (xpc10nz) 10'sd932/*932:xpc10nz*/: $display(""); 10'sd944/*944:xpc10nz*/: $display("UU="); endcase else if ((xpc10nz==10'sd933/*933:xpc10nz*/)) $write(" %F ", $bitstoreal(((xpc10nz==10'sd933/*933:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0 : FPDCCSCALbx34ARB0RRh10hold))); if ((lTMTMaV_1_GP>=32'sd8)) begin if ((xpc10nz==10'sd930/*930:xpc10nz*/)) $display(""); end else if ((xpc10nz==10'sd930/*930:xpc10nz*/)) $write(" "); if ((TMp1_V_0_GP>=32'sd8)) begin if ((xpc10nz==10'sd926/*926:xpc10nz*/)) $display(""); end else if ((xpc10nz==10'sd927/*927:xpc10nz*/)) $write(" %F ", $bitstoreal(((xpc10nz==10'sd927/*927:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0 : FPDCCSCALbx34ARB0RRh10hold))); if ((TMp1_V_0_GP>=32'sd8)) begin if ((xpc10nz==10'sd923/*923:xpc10nz*/)) $display(""); end else if ((xpc10nz==10'sd924/*924:xpc10nz*/)) $write(" %F ", $bitstoreal(((xpc10nz==10'sd924/*924:xpc10nz*/)? A_FPD_CC_SCALbx32_ARA0_RDD0 : FPDCCSCALbx32ARA0RRh10hold))); if ((lTMTMaV_1_GP>=32'sd8)) begin if ((xpc10nz==10'sd921/*921:xpc10nz*/)) $display(""); end else if ((xpc10nz==10'sd921/*921:xpc10nz*/)) $write(" "); if ((TMp1_V_0_GP>=32'sd8)) begin if ((xpc10nz==10'sd917/*917:xpc10nz*/)) $display(""); end else if ((xpc10nz==10'sd918/*918:xpc10nz*/)) $write(" %F ", $bitstoreal(((xpc10nz==10'sd918/*918:xpc10nz*/)? A_FPD_CC_SCALbx32_ARA0_RDD0 : FPDCCSCALbx32ARA0RRh10hold))); if ((TMp1_V_0_GP>=32'sd8)) begin if ((xpc10nz==10'sd888/*888:xpc10nz*/)) $display(""); end else if ((xpc10nz==10'sd889/*889:xpc10nz*/)) $write(" %F ", $bitstoreal(((xpc10nz==10'sd889/*889:xpc10nz*/)? A_FPD_CC_SCALbx36_ARC0_RDD0 : FPDCCSCALbx36ARC0RRh10hold))); if ((lTMTMaV_1_GP>=32'sd8)) begin if ((xpc10nz==10'sd886/*886:xpc10nz*/)) $display(""); end else if ((xpc10nz==10'sd886/*886:xpc10nz*/)) $write(" "); if ((TMp1_V_0_GP>=32'sd8)) begin if ((xpc10nz==10'sd882/*882:xpc10nz*/)) $display(""); end else case (xpc10nz) 10'sd774/*774:xpc10nz*/: $write("%F ", $bitstoreal(((xpc10nz==10'sd774/*774:xpc10nz*/)? A_FPD_CC_SCALbx42_ARF0_RDD0 : FPDCCSCALbx42ARF0RRh10hold))); 10'sd823/*823:xpc10nz*/: $write("%F ", $bitstoreal(((xpc10nz==10'sd823/*823:xpc10nz*/)? A_FPD_CC_SCALbx40_ARE0_RDD0 : FPDCCSCALbx40ARE0RRh10hold))); 10'sd863/*863:xpc10nz*/: $display(" test=%1d target_rhs [%1d] == %F", lTMTMaV_1_GP, TMp1_V_0_GP, $bitstoreal(((xpc10nz ==10'sd863/*863:xpc10nz*/)? A_FPD_CC_SCALbx38_ARD0_RDD0: FPDCCSCALbx38ARD0RRh10hold))); 10'sd883/*883:xpc10nz*/: $write(" %F ", $bitstoreal(((xpc10nz==10'sd883/*883:xpc10nz*/)? A_FPD_CC_SCALbx36_ARC0_RDD0 : FPDCCSCALbx36ARC0RRh10hold))); endcase if ((TMp1_V_0_GP>=32'sd8)) begin if ((xpc10nz==10'sd760/*760:xpc10nz*/)) $write("{"); end else if ((xpc10nz==10'sd747/*747:xpc10nz*/)) $write("%F ", $bitstoreal(((xpc10nz==10'sd747/*747:xpc10nz*/)? A_FPD_CC_SCALbx46_ARH0_RDD0 : FPDCCSCALbx46ARH0RRh10hold))); if ((lTMTMaV_1_GP>=32'sd3)) begin if ((xpc10nz==10'sd744/*744:xpc10nz*/)) $display("Kiwi L/U demo - L/U decomposition demo complete at %1d." , $time); end else if ((xpc10nz==10'sd744/*744:xpc10nz*/)) $display("\nKiwi L/U demo - L/U decomposition test with rhs no %1d.", lTMTMaV_1_GP ); if ((xpc10nz==10'sd743/*743:xpc10nz*/)) $display("}"); if ((TMp1_V_0_GP<32'sd8)) begin if ((xpc10nz==10'sd742/*742:xpc10nz*/)) $write("%F ", $bitstoreal(((xpc10nz==10'sd742 /*742:xpc10nz*/)? A_FPD_CC_SCALbx46_ARH0_RDD0: FPDCCSCALbx46ARH0RRh10hold))); end else if ((xpc10nz==10'sd739/*739:xpc10nz*/)) $write("{"); case (xpc10nz) 10'sd737/*737:xpc10nz*/: $display("}"); 10'sd738/*738:xpc10nz*/: $write("Substitute back - rhs given by solution is: y="); endcase if ((TMp1_V_0_GP<32'sd8) && (xpc10nz==10'sd736/*736:xpc10nz*/)) $write("%F ", $bitstoreal(((xpc10nz==10'sd736/*736:xpc10nz*/)? A_FPD_CC_SCALbx42_ARF0_RDD0 : FPDCCSCALbx42ARF0RRh10hold))); case (xpc10nz) 10'sd731/*731:xpc10nz*/: $display("}"); 10'sd733/*733:xpc10nz*/: begin $write("After back subst="); $write("{"); end endcase if ((TMp1_V_0_GP<32'sd8) && (xpc10nz==10'sd730/*730:xpc10nz*/)) $write("%F ", $bitstoreal(((xpc10nz==10'sd730/*730:xpc10nz*/)? A_FPD_CC_SCALbx40_ARE0_RDD0 : FPDCCSCALbx40ARE0RRh10hold))); if ((xpc10nz==10'sd727/*727:xpc10nz*/)) begin $write("After fwds subst="); $write("{"); end if ((TMp1_V_0_GP<32'sd8) && (xpc10nz==10'sd724/*724:xpc10nz*/)) $display(" test=%1d target_rhs [%1d] == %F", lTMTMaV_1_GP , TMp1_V_0_GP, $bitstoreal(((xpc10nz==10'sd724/*724:xpc10nz*/)? A_FPD_CC_SCALbx38_ARD0_RDD0: FPDCCSCALbx38ARD0RRh10hold ))); if ((xpc10nz==10'sd701/*701:xpc10nz*/)) $finish(32'sd0); if ((lTMTMaV_1_GP>=32'sd3)) begin if ((xpc10nz==10'sd700/*700:xpc10nz*/)) $display("Kiwi L/U demo - L/U decomposition demo complete at %1d." , $time); end else if ((xpc10nz==10'sd700/*700:xpc10nz*/)) $display("\nKiwi L/U demo - L/U decomposition test with rhs no %1d.", lTMTMaV_1_GP ); if ((xpc10nz==10'sd698/*698:xpc10nz*/)) $display("Kiwi L/U demo - coefficient matrix decomposed."); if ((lTMTMaV_1_GP>=32'sd8)) begin if ((xpc10nz==10'sd697/*697:xpc10nz*/)) $display(""); end else if ((xpc10nz==10'sd697/*697:xpc10nz*/)) $write(" "); if ((xpc10nz==10'sd695/*695:xpc10nz*/)) $display("Recombine LL and RR: Should result in the original:"); if ((lTMTMaV_1_GP>=32'sd8)) begin if ((xpc10nz==10'sd694/*694:xpc10nz*/)) $display(""); end else if ((xpc10nz==10'sd694/*694:xpc10nz*/)) $write(" "); if ((xpc10nz==10'sd693/*693:xpc10nz*/)) $display("LL="); if ((lTMTMaV_1_GP>=32'sd8)) begin if ((xpc10nz==10'sd692/*692:xpc10nz*/)) $display(""); end else if ((xpc10nz==10'sd692/*692:xpc10nz*/)) $write(" "); if ((TMp1_V_0_GP>=32'sd8)) case (xpc10nz) 10'sd686/*686:xpc10nz*/: $display(""); 10'sd690/*690:xpc10nz*/: $display("UU="); endcase else if ((xpc10nz==10'sd686/*686:xpc10nz*/)) $write(" "); case (xpc10nz) 10'sd24/*24:xpc10nz*/: $display("Kiwi Demo - L/U decomposition"); 10'sd384/*384:xpc10nz*/: $display("Kiwi L/U demo - L/U decomposition target_rhs generated."); 10'sd657/*657:xpc10nz*/: begin $display("L/U Decomposition - single-threaded version.\n"); $display("Initial Coefficient Matrix Pre L/U Decomposition:\n"); end 10'sd659/*659:xpc10nz*/: $write(" "); 10'sd661/*661:xpc10nz*/: $write(" %F ", $bitstoreal(((xpc10nz==10'sd661/*661:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0 : FPDCCSCALbx34ARB0RRh10hold))); 10'sd664/*664:xpc10nz*/: $write(" %F ", $bitstoreal(((xpc10nz==10'sd664/*664:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0 : FPDCCSCALbx34ARB0RRh10hold))); 10'sd667/*667:xpc10nz*/: $write(" %F ", $bitstoreal(((xpc10nz==10'sd667/*667:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0 : FPDCCSCALbx34ARB0RRh10hold))); 10'sd670/*670:xpc10nz*/: $write(" %F ", $bitstoreal(((xpc10nz==10'sd670/*670:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0 : FPDCCSCALbx34ARB0RRh10hold))); 10'sd673/*673:xpc10nz*/: $write(" %F ", $bitstoreal(((xpc10nz==10'sd673/*673:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0 : FPDCCSCALbx34ARB0RRh10hold))); 10'sd676/*676:xpc10nz*/: $write(" %F ", $bitstoreal(((xpc10nz==10'sd676/*676:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0 : FPDCCSCALbx34ARB0RRh10hold))); 10'sd679/*679:xpc10nz*/: $write(" %F ", $bitstoreal(((xpc10nz==10'sd679/*679:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0 : FPDCCSCALbx34ARB0RRh10hold))); 10'sd682/*682:xpc10nz*/: $write(" %F ", $bitstoreal(((xpc10nz==10'sd682/*682:xpc10nz*/)? A_FPD_CC_SCALbx34_ARB0_RDD0 : FPDCCSCALbx34ARB0RRh10hold))); 10'sd684/*684:xpc10nz*/: $display(""); endcase if ((TMp1_V_0_GP<32'sd8)) case (xpc10nz) 10'sd686/*686:xpc10nz*/: xpc10nz <= 10'sd987/*987:xpc10nz*/; 10'sd688/*688:xpc10nz*/: xpc10nz <= 10'sd689/*689:xpc10nz*/; 10'sd690/*690:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd0; xpc10nz <= 10'sd934/*934:xpc10nz*/; end 10'sd703/*703:xpc10nz*/: xpc10nz <= 10'sd705/*705:xpc10nz*/; 10'sd720/*720:xpc10nz*/: xpc10nz <= 10'sd723/*723:xpc10nz*/; 10'sd726/*726:xpc10nz*/: begin TMm1_V_1_GP <= 64'h0; xpc10nz <= 10'sd824/*824:xpc10nz*/; end 10'sd729/*729:xpc10nz*/: xpc10nz <= 10'sd730/*730:xpc10nz*/; 10'sd735/*735:xpc10nz*/: xpc10nz <= 10'sd736/*736:xpc10nz*/; 10'sd739/*739:xpc10nz*/: begin TMm1_V_1_GP <= 64'h0; xpc10nz <= 10'sd748/*748:xpc10nz*/; end 10'sd741/*741:xpc10nz*/: xpc10nz <= 10'sd742/*742:xpc10nz*/; 10'sd746/*746:xpc10nz*/: xpc10nz <= 10'sd747/*747:xpc10nz*/; 10'sd760/*760:xpc10nz*/: begin TMm1_V_1_GP <= 64'h0; xpc10nz <= 10'sd748/*748:xpc10nz*/; end 10'sd773/*773:xpc10nz*/: xpc10nz <= 10'sd774/*774:xpc10nz*/; 10'sd822/*822:xpc10nz*/: xpc10nz <= 10'sd823/*823:xpc10nz*/; 10'sd841/*841:xpc10nz*/: begin TMm1_V_1_GP <= 64'h0; xpc10nz <= 10'sd824/*824:xpc10nz*/; end 10'sd859/*859:xpc10nz*/: xpc10nz <= 10'sd862/*862:xpc10nz*/; 10'sd865/*865:xpc10nz*/: xpc10nz <= 10'sd867/*867:xpc10nz*/; 10'sd882/*882:xpc10nz*/: xpc10nz <= 10'sd883/*883:xpc10nz*/; 10'sd888/*888:xpc10nz*/: xpc10nz <= 10'sd889/*889:xpc10nz*/; 10'sd890/*890:xpc10nz*/: begin TMm1_V_1_GP <= 64'h0; xpc10nz <= 10'sd892/*892:xpc10nz*/; end 10'sd904/*904:xpc10nz*/: begin TMm1_V_1_GP <= 64'h0; xpc10nz <= 10'sd892/*892:xpc10nz*/; end 10'sd917/*917:xpc10nz*/: xpc10nz <= 10'sd918/*918:xpc10nz*/; 10'sd923/*923:xpc10nz*/: xpc10nz <= 10'sd924/*924:xpc10nz*/; 10'sd926/*926:xpc10nz*/: xpc10nz <= 10'sd927/*927:xpc10nz*/; 10'sd932/*932:xpc10nz*/: xpc10nz <= 10'sd933/*933:xpc10nz*/; 10'sd944/*944:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd0; xpc10nz <= 10'sd934/*934:xpc10nz*/; end 10'sd985/*985:xpc10nz*/: xpc10nz <= 10'sd986/*986:xpc10nz*/; endcase else case (xpc10nz) 10'sd686/*686:xpc10nz*/: xpc10nz <= 10'sd687/*687:xpc10nz*/; 10'sd688/*688:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd690/*690:xpc10nz*/; end 10'sd690/*690:xpc10nz*/: xpc10nz <= 10'sd691/*691:xpc10nz*/; 10'sd703/*703:xpc10nz*/: xpc10nz <= 10'sd704/*704:xpc10nz*/; 10'sd720/*720:xpc10nz*/: xpc10nz <= 10'sd721/*721:xpc10nz*/; 10'sd726/*726:xpc10nz*/: xpc10nz <= 10'sd727/*727:xpc10nz*/; 10'sd729/*729:xpc10nz*/: xpc10nz <= 10'sd731/*731:xpc10nz*/; 10'sd735/*735:xpc10nz*/: xpc10nz <= 10'sd737/*737:xpc10nz*/; 10'sd739/*739:xpc10nz*/: xpc10nz <= 10'sd740/*740:xpc10nz*/; 10'sd741/*741:xpc10nz*/: xpc10nz <= 10'sd743/*743:xpc10nz*/; 10'sd746/*746:xpc10nz*/: xpc10nz <= 10'sd743/*743:xpc10nz*/; 10'sd760/*760:xpc10nz*/: xpc10nz <= 10'sd740/*740:xpc10nz*/; 10'sd773/*773:xpc10nz*/: xpc10nz <= 10'sd737/*737:xpc10nz*/; 10'sd822/*822:xpc10nz*/: xpc10nz <= 10'sd731/*731:xpc10nz*/; 10'sd841/*841:xpc10nz*/: xpc10nz <= 10'sd727/*727:xpc10nz*/; 10'sd859/*859:xpc10nz*/: xpc10nz <= 10'sd860/*860:xpc10nz*/; 10'sd865/*865:xpc10nz*/: xpc10nz <= 10'sd866/*866:xpc10nz*/; 10'sd882/*882:xpc10nz*/: xpc10nz <= 10'sd884/*884:xpc10nz*/; 10'sd888/*888:xpc10nz*/: xpc10nz <= 10'sd884/*884:xpc10nz*/; 10'sd890/*890:xpc10nz*/: begin lTMTMaV_1_GP <= 32'sd1+lTMTMaV_1_GP; xpc10nz <= 10'sd891/*891:xpc10nz*/; end 10'sd904/*904:xpc10nz*/: begin lTMTMaV_1_GP <= 32'sd1+lTMTMaV_1_GP; xpc10nz <= 10'sd891/*891:xpc10nz*/; end 10'sd917/*917:xpc10nz*/: xpc10nz <= 10'sd919/*919:xpc10nz*/; 10'sd923/*923:xpc10nz*/: xpc10nz <= 10'sd919/*919:xpc10nz*/; 10'sd926/*926:xpc10nz*/: xpc10nz <= 10'sd928/*928:xpc10nz*/; 10'sd932/*932:xpc10nz*/: xpc10nz <= 10'sd928/*928:xpc10nz*/; 10'sd944/*944:xpc10nz*/: xpc10nz <= 10'sd691/*691:xpc10nz*/; 10'sd985/*985:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd690/*690:xpc10nz*/; end endcase if ((lTMTMaV_1_GP<32'sd8)) case (xpc10nz) 10'sd692/*692:xpc10nz*/: xpc10nz <= 10'sd925/*925:xpc10nz*/; 10'sd694/*694:xpc10nz*/: xpc10nz <= 10'sd916/*916:xpc10nz*/; 10'sd696/*696:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd890/*890:xpc10nz*/; end 10'sd697/*697:xpc10nz*/: xpc10nz <= 10'sd881/*881:xpc10nz*/; 10'sd886/*886:xpc10nz*/: xpc10nz <= 10'sd881/*881:xpc10nz*/; 10'sd891/*891:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd890/*890:xpc10nz*/; end 10'sd921/*921:xpc10nz*/: xpc10nz <= 10'sd916/*916:xpc10nz*/; 10'sd930/*930:xpc10nz*/: xpc10nz <= 10'sd925/*925:xpc10nz*/; 10'sd950/*950:xpc10nz*/: xpc10nz <= 10'sd951/*951:xpc10nz*/; 10'sd970/*970:xpc10nz*/: xpc10nz <= 10'sd971/*971:xpc10nz*/; endcase else case (xpc10nz) 10'sd692/*692:xpc10nz*/: xpc10nz <= 10'sd693/*693:xpc10nz*/; 10'sd694/*694:xpc10nz*/: xpc10nz <= 10'sd695/*695:xpc10nz*/; 10'sd696/*696:xpc10nz*/: begin lTMTMaV_1_GP <= 32'sd0; xpc10nz <= 10'sd697/*697:xpc10nz*/; end 10'sd697/*697:xpc10nz*/: xpc10nz <= 10'sd698/*698:xpc10nz*/; 10'sd886/*886:xpc10nz*/: xpc10nz <= 10'sd698/*698:xpc10nz*/; 10'sd891/*891:xpc10nz*/: begin lTMTMaV_1_GP <= 32'sd0; xpc10nz <= 10'sd697/*697:xpc10nz*/; end 10'sd921/*921:xpc10nz*/: xpc10nz <= 10'sd695/*695:xpc10nz*/; 10'sd930/*930:xpc10nz*/: xpc10nz <= 10'sd693/*693:xpc10nz*/; 10'sd950/*950:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1+TMm1_V_2_GP; xpc10nz <= 10'sd961/*961:xpc10nz*/; end 10'sd970/*970:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1+TMm1_V_2_GP; xpc10nz <= 10'sd961/*961:xpc10nz*/; end endcase if ((TMm1_V_2_GP<32'sd8)) case (xpc10nz) 10'sd749/*749:xpc10nz*/: xpc10nz <= 10'sd751/*751:xpc10nz*/; 10'sd758/*758:xpc10nz*/: TMm1_V_1_GP <= ((xpc10nz==10'sd758/*758:xpc10nz*/)? CVFPADDER20_FPRR: CVFPADDER20RRh10hold ); 10'sd762/*762:xpc10nz*/: xpc10nz <= 10'sd764/*764:xpc10nz*/; 10'sd771/*771:xpc10nz*/: TMm1_V_1_GP <= ((xpc10nz==10'sd771/*771:xpc10nz*/)? CVFPADDER20_FPRR: CVFPADDER20RRh10hold ); 10'sd776/*776:xpc10nz*/: xpc10nz <= 10'sd788/*788:xpc10nz*/; 10'sd796/*796:xpc10nz*/: TMm1_V_1_GP <= ((xpc10nz==10'sd796/*796:xpc10nz*/)? CVFPADDER18_FPRR: CVFPADDER18RRh10hold ); 10'sd800/*800:xpc10nz*/: xpc10nz <= 10'sd812/*812:xpc10nz*/; 10'sd820/*820:xpc10nz*/: TMm1_V_1_GP <= ((xpc10nz==10'sd820/*820:xpc10nz*/)? CVFPADDER18_FPRR: CVFPADDER18RRh10hold ); 10'sd893/*893:xpc10nz*/: xpc10nz <= 10'sd895/*895:xpc10nz*/; 10'sd902/*902:xpc10nz*/: TMm1_V_1_GP <= ((xpc10nz==10'sd902/*902:xpc10nz*/)? CVFPADDER20_FPRR: CVFPADDER20RRh10hold ); 10'sd906/*906:xpc10nz*/: xpc10nz <= 10'sd908/*908:xpc10nz*/; 10'sd915/*915:xpc10nz*/: TMm1_V_1_GP <= ((xpc10nz==10'sd915/*915:xpc10nz*/)? CVFPADDER20_FPRR: CVFPADDER20RRh10hold ); 10'sd934/*934:xpc10nz*/: xpc10nz <= 10'sd935/*935:xpc10nz*/; 10'sd936/*936:xpc10nz*/: xpc10nz <= 10'sd937/*937:xpc10nz*/; 10'sd943/*943:xpc10nz*/: TMm1_V_1_GP <= ((xpc10nz==10'sd943/*943:xpc10nz*/)? CVFPDIVIDER14_FPRR: CVFPDIVIDER14RRh10hold ); 10'sd961/*961:xpc10nz*/: xpc10nz <= 10'sd962/*962:xpc10nz*/; 10'sd968/*968:xpc10nz*/: TMm1_V_1_GP <= ((xpc10nz==10'sd968/*968:xpc10nz*/)? CVFPDIVIDER16_FPRR: CVFPDIVIDER16RRh10hold ); 10'sd982/*982:xpc10nz*/: xpc10nz <= 10'sd983/*983:xpc10nz*/; 10'sd988/*988:xpc10nz*/: xpc10nz <= 10'sd989/*989:xpc10nz*/; 10'sd992/*992:xpc10nz*/: xpc10nz <= 10'sd993/*993:xpc10nz*/; endcase else case (xpc10nz) 10'sd749/*749:xpc10nz*/: xpc10nz <= 10'sd750/*750:xpc10nz*/; 10'sd762/*762:xpc10nz*/: xpc10nz <= 10'sd763/*763:xpc10nz*/; 10'sd776/*776:xpc10nz*/: xpc10nz <= 10'sd777/*777:xpc10nz*/; 10'sd800/*800:xpc10nz*/: xpc10nz <= 10'sd801/*801:xpc10nz*/; 10'sd893/*893:xpc10nz*/: xpc10nz <= 10'sd894/*894:xpc10nz*/; 10'sd906/*906:xpc10nz*/: xpc10nz <= 10'sd907/*907:xpc10nz*/; 10'sd934/*934:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd936/*936:xpc10nz*/; end 10'sd936/*936:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd944/*944:xpc10nz*/; end 10'sd961/*961:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd944/*944:xpc10nz*/; end 10'sd982/*982:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd936/*936:xpc10nz*/; end 10'sd988/*988:xpc10nz*/: xpc10nz <= 10'sd990/*990:xpc10nz*/; 10'sd992/*992:xpc10nz*/: xpc10nz <= 10'sd990/*990:xpc10nz*/; endcase if (CVFPADDER20RRh10shot3) begin CVFPADDER20RRh10hold <= CVFPADDER20_FPRR; CVFPADDER20RRh10hold <= CVFPADDER20_FPRR; CVFPADDER20RRh10hold <= CVFPADDER20_FPRR; CVFPADDER20RRh10hold <= CVFPADDER20_FPRR; CVFPADDER20RRh10hold <= CVFPADDER20_FPRR; CVFPADDER20RRh10hold <= CVFPADDER20_FPRR; CVFPADDER20RRh10hold <= CVFPADDER20_FPRR; CVFPADDER20RRh10hold <= CVFPADDER20_FPRR; CVFPADDER20RRh10hold <= CVFPADDER20_FPRR; CVFPADDER20RRh10hold <= CVFPADDER20_FPRR; CVFPADDER20RRh10hold <= CVFPADDER20_FPRR; CVFPADDER20RRh10hold <= CVFPADDER20_FPRR; CVFPADDER20RRh10hold <= CVFPADDER20_FPRR; CVFPADDER20RRh10hold <= CVFPADDER20_FPRR; CVFPADDER20RRh10hold <= CVFPADDER20_FPRR; end if (FPDCCSCALbx34ARB0RRh10shot0) begin FPDCCSCALbx34ARB0RRh10hold <= A_FPD_CC_SCALbx34_ARB0_RDD0; FPDCCSCALbx34ARB0RRh10hold <= A_FPD_CC_SCALbx34_ARB0_RDD0; FPDCCSCALbx34ARB0RRh10hold <= A_FPD_CC_SCALbx34_ARB0_RDD0; FPDCCSCALbx34ARB0RRh10hold <= A_FPD_CC_SCALbx34_ARB0_RDD0; FPDCCSCALbx34ARB0RRh10hold <= A_FPD_CC_SCALbx34_ARB0_RDD0; FPDCCSCALbx34ARB0RRh10hold <= A_FPD_CC_SCALbx34_ARB0_RDD0; FPDCCSCALbx34ARB0RRh10hold <= A_FPD_CC_SCALbx34_ARB0_RDD0; FPDCCSCALbx34ARB0RRh10hold <= A_FPD_CC_SCALbx34_ARB0_RDD0; FPDCCSCALbx34ARB0RRh10hold <= A_FPD_CC_SCALbx34_ARB0_RDD0; FPDCCSCALbx34ARB0RRh10hold <= A_FPD_CC_SCALbx34_ARB0_RDD0; FPDCCSCALbx34ARB0RRh10hold <= A_FPD_CC_SCALbx34_ARB0_RDD0; end if (FPDCCSCALbx44ARG0RRh10shot0) begin FPDCCSCALbx44ARG0RRh10hold <= A_FPD_CC_SCALbx44_ARG0_RDD0; FPDCCSCALbx44ARG0RRh10hold <= A_FPD_CC_SCALbx44_ARG0_RDD0; FPDCCSCALbx44ARG0RRh10hold <= A_FPD_CC_SCALbx44_ARG0_RDD0; FPDCCSCALbx44ARG0RRh10hold <= A_FPD_CC_SCALbx44_ARG0_RDD0; FPDCCSCALbx44ARG0RRh10hold <= A_FPD_CC_SCALbx44_ARG0_RDD0; FPDCCSCALbx44ARG0RRh10hold <= A_FPD_CC_SCALbx44_ARG0_RDD0; FPDCCSCALbx44ARG0RRh10hold <= A_FPD_CC_SCALbx44_ARG0_RDD0; FPDCCSCALbx44ARG0RRh10hold <= A_FPD_CC_SCALbx44_ARG0_RDD0; FPDCCSCALbx44ARG0RRh10hold <= A_FPD_CC_SCALbx44_ARG0_RDD0; FPDCCSCALbx44ARG0RRh10hold <= A_FPD_CC_SCALbx44_ARG0_RDD0; FPDCCSCALbx44ARG0RRh10hold <= A_FPD_CC_SCALbx44_ARG0_RDD0; end if ((lTMTMaV_1_GP<32'sd3)) case (xpc10nz) 10'sd700/*700:xpc10nz*/: xpc10nz <= 10'sd702/*702:xpc10nz*/; 10'sd744/*744:xpc10nz*/: xpc10nz <= 10'sd702/*702:xpc10nz*/; endcase else case (xpc10nz) 10'sd700/*700:xpc10nz*/: xpc10nz <= 10'sd701/*701:xpc10nz*/; 10'sd744/*744:xpc10nz*/: xpc10nz <= 10'sd701/*701:xpc10nz*/; endcase if (CVFPADDER18RRh10shot3) begin CVFPADDER18RRh10hold <= CVFPADDER18_FPRR; CVFPADDER18RRh10hold <= CVFPADDER18_FPRR; CVFPADDER18RRh10hold <= CVFPADDER18_FPRR; CVFPADDER18RRh10hold <= CVFPADDER18_FPRR; CVFPADDER18RRh10hold <= CVFPADDER18_FPRR; CVFPADDER18RRh10hold <= CVFPADDER18_FPRR; CVFPADDER18RRh10hold <= CVFPADDER18_FPRR; end if (FPDCCSCALbx40ARE0RRh10shot0) begin FPDCCSCALbx40ARE0RRh10hold <= A_FPD_CC_SCALbx40_ARE0_RDD0; FPDCCSCALbx40ARE0RRh10hold <= A_FPD_CC_SCALbx40_ARE0_RDD0; FPDCCSCALbx40ARE0RRh10hold <= A_FPD_CC_SCALbx40_ARE0_RDD0; FPDCCSCALbx40ARE0RRh10hold <= A_FPD_CC_SCALbx40_ARE0_RDD0; FPDCCSCALbx40ARE0RRh10hold <= A_FPD_CC_SCALbx40_ARE0_RDD0; FPDCCSCALbx40ARE0RRh10hold <= A_FPD_CC_SCALbx40_ARE0_RDD0; end if ((TMp1_V_0_GP<32'sd0)) case (xpc10nz) 10'sd732/*732:xpc10nz*/: xpc10nz <= 10'sd733/*733:xpc10nz*/; 10'sd798/*798:xpc10nz*/: xpc10nz <= 10'sd733/*733:xpc10nz*/; endcase else case (xpc10nz) 10'sd732/*732:xpc10nz*/: begin TMm1_V_1_GP <= 64'h0; xpc10nz <= 10'sd775/*775:xpc10nz*/; end 10'sd798/*798:xpc10nz*/: begin TMm1_V_1_GP <= 64'h0; xpc10nz <= 10'sd775/*775:xpc10nz*/; end endcase if ((TMm1_V_2_GP<TMp1_V_0_GP)) case (xpc10nz) 10'sd825/*825:xpc10nz*/: xpc10nz <= 10'sd832/*832:xpc10nz*/; 10'sd839/*839:xpc10nz*/: TMm1_V_1_GP <= ((xpc10nz==10'sd839/*839:xpc10nz*/)? CVFPADDER18_FPRR: CVFPADDER18RRh10hold ); 10'sd843/*843:xpc10nz*/: xpc10nz <= 10'sd850/*850:xpc10nz*/; 10'sd857/*857:xpc10nz*/: TMm1_V_1_GP <= ((xpc10nz==10'sd857/*857:xpc10nz*/)? CVFPADDER18_FPRR: CVFPADDER18RRh10hold ); endcase else case (xpc10nz) 10'sd825/*825:xpc10nz*/: xpc10nz <= 10'sd826/*826:xpc10nz*/; 10'sd843/*843:xpc10nz*/: xpc10nz <= 10'sd844/*844:xpc10nz*/; endcase if (FPDCCSCALbx34ARB0RRh12shot0) begin FPDCCSCALbx34ARB0RRh12hold <= A_FPD_CC_SCALbx34_ARB0_RDD0; FPDCCSCALbx34ARB0RRh12hold <= A_FPD_CC_SCALbx34_ARB0_RDD0; FPDCCSCALbx34ARB0RRh12hold <= A_FPD_CC_SCALbx34_ARB0_RDD0; FPDCCSCALbx34ARB0RRh12hold <= A_FPD_CC_SCALbx34_ARB0_RDD0; FPDCCSCALbx34ARB0RRh12hold <= A_FPD_CC_SCALbx34_ARB0_RDD0; end if (CVFPMULTIPLIER28RRh10shot2) begin CVFPMULTIPLIER28RRh10hold <= CVFPMULTIPLIER28_FPRR; CVFPMULTIPLIER28RRh10hold <= CVFPMULTIPLIER28_FPRR; CVFPMULTIPLIER28RRh10hold <= CVFPMULTIPLIER28_FPRR; CVFPMULTIPLIER28RRh10hold <= CVFPMULTIPLIER28_FPRR; CVFPMULTIPLIER28RRh10hold <= CVFPMULTIPLIER28_FPRR; end if (FPDCCSCALbx32ARA0RRh10shot0) begin FPDCCSCALbx32ARA0RRh10hold <= A_FPD_CC_SCALbx32_ARA0_RDD0; FPDCCSCALbx32ARA0RRh10hold <= A_FPD_CC_SCALbx32_ARA0_RDD0; FPDCCSCALbx32ARA0RRh10hold <= A_FPD_CC_SCALbx32_ARA0_RDD0; FPDCCSCALbx32ARA0RRh10hold <= A_FPD_CC_SCALbx32_ARA0_RDD0; FPDCCSCALbx32ARA0RRh10hold <= A_FPD_CC_SCALbx32_ARA0_RDD0; end if (FPDCCSCALbx42ARF0RRh10shot0) begin FPDCCSCALbx42ARF0RRh10hold <= A_FPD_CC_SCALbx42_ARF0_RDD0; FPDCCSCALbx42ARF0RRh10hold <= A_FPD_CC_SCALbx42_ARF0_RDD0; FPDCCSCALbx42ARF0RRh10hold <= A_FPD_CC_SCALbx42_ARF0_RDD0; FPDCCSCALbx42ARF0RRh10hold <= A_FPD_CC_SCALbx42_ARF0_RDD0; FPDCCSCALbx42ARF0RRh10hold <= A_FPD_CC_SCALbx42_ARF0_RDD0; end if (FPDCCSCALbx38ARD0RRh10shot0) begin FPDCCSCALbx38ARD0RRh10hold <= A_FPD_CC_SCALbx38_ARD0_RDD0; FPDCCSCALbx38ARD0RRh10hold <= A_FPD_CC_SCALbx38_ARD0_RDD0; FPDCCSCALbx38ARD0RRh10hold <= A_FPD_CC_SCALbx38_ARD0_RDD0; FPDCCSCALbx38ARD0RRh10hold <= A_FPD_CC_SCALbx38_ARD0_RDD0; end case (xpc10nz) 10'sd24/*24:xpc10nz*/: xpc10nz <= 10'sd25/*25:xpc10nz*/; 10'sd37/*37:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4024_0000_0000_0000; xpc10nz <= 10'sd38/*38:xpc10nz*/; end 10'sd38/*38:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd0; xpc10nz <= 10'sd39/*39:xpc10nz*/; end 10'sd39/*39:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd40/*40:xpc10nz*/; end 10'sd42/*42:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4026_0000_0000_0000; xpc10nz <= 10'sd43/*43:xpc10nz*/; end 10'sd43/*43:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1; xpc10nz <= 10'sd44/*44:xpc10nz*/; end 10'sd46/*46:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4028_3333_3333_3334; xpc10nz <= 10'sd47/*47:xpc10nz*/; end 10'sd47/*47:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd2; xpc10nz <= 10'sd48/*48:xpc10nz*/; end 10'sd50/*50:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_402a_9eb8_51eb_8520; xpc10nz <= 10'sd51/*51:xpc10nz*/; end 10'sd51/*51:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd3; xpc10nz <= 10'sd52/*52:xpc10nz*/; end 10'sd54/*54:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_402d_4831_26e9_78d7; xpc10nz <= 10'sd55/*55:xpc10nz*/; end 10'sd55/*55:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd4; xpc10nz <= 10'sd56/*56:xpc10nz*/; end 10'sd58/*58:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4030_1ae7_d566_cf43; xpc10nz <= 10'sd59/*59:xpc10nz*/; end 10'sd59/*59:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd5; xpc10nz <= 10'sd60/*60:xpc10nz*/; end 10'sd62/*62:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4031_b732_378a_b0ca; xpc10nz <= 10'sd63/*63:xpc10nz*/; end 10'sd63/*63:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd6; xpc10nz <= 10'sd64/*64:xpc10nz*/; end 10'sd66/*66:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4033_7cb7_3d18_8f45; xpc10nz <= 10'sd67/*67:xpc10nz*/; end 10'sd67/*67:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd7; xpc10nz <= 10'sd68/*68:xpc10nz*/; end 10'sd70/*70:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4035_6f96_5cce_3733; xpc10nz <= 10'sd71/*71:xpc10nz*/; end 10'sd71/*71:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd8; xpc10nz <= 10'sd72/*72:xpc10nz*/; end 10'sd72/*72:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1; xpc10nz <= 10'sd73/*73:xpc10nz*/; end 10'sd73/*73:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd74/*74:xpc10nz*/; end 10'sd76/*76:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4037_9458_9949_3cb9; xpc10nz <= 10'sd77/*77:xpc10nz*/; end 10'sd77/*77:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1; xpc10nz <= 10'sd78/*78:xpc10nz*/; end 10'sd80/*80:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4039_effb_0f03_c2cc; xpc10nz <= 10'sd81/*81:xpc10nz*/; end 10'sd81/*81:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd2; xpc10nz <= 10'sd82/*82:xpc10nz*/; end 10'sd84/*84:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_403c_87fa_9084_2314; xpc10nz <= 10'sd85/*85:xpc10nz*/; end 10'sd85/*85:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd3; xpc10nz <= 10'sd86/*86:xpc10nz*/; end 10'sd88/*88:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_403f_6260_6bc4_8cfd; xpc10nz <= 10'sd89/*89:xpc10nz*/; end 10'sd89/*89:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd4; xpc10nz <= 10'sd90/*90:xpc10nz*/; end 10'sd92/*92:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4041_42e8_3b45_b3f2; xpc10nz <= 10'sd93/*93:xpc10nz*/; end 10'sd93/*93:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd5; xpc10nz <= 10'sd94/*94:xpc10nz*/; end 10'sd96/*96:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4042_fccc_4133_12be; xpc10nz <= 10'sd97/*97:xpc10nz*/; end 10'sd97/*97:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd6; xpc10nz <= 10'sd98/*98:xpc10nz*/; end 10'sd100/*100:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4044_e2e0_ae1e_949e; xpc10nz <= 10'sd101/*101:xpc10nz*/; end 10'sd101/*101:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd7; xpc10nz <= 10'sd102/*102:xpc10nz*/; end 10'sd104/*104:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4046_f990_bf88_09e2; xpc10nz <= 10'sd105/*105:xpc10nz*/; end 10'sd105/*105:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd8; xpc10nz <= 10'sd106/*106:xpc10nz*/; end 10'sd106/*106:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd2; xpc10nz <= 10'sd107/*107:xpc10nz*/; end 10'sd107/*107:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd108/*108:xpc10nz*/; end 10'sd110/*110:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4049_45b8_d2af_3e13; xpc10nz <= 10'sd111/*111:xpc10nz*/; end 10'sd111/*111:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1; xpc10nz <= 10'sd112/*112:xpc10nz*/; end 10'sd114/*114:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_404b_ccb1_b48d_9116; xpc10nz <= 10'sd115/*115:xpc10nz*/; end 10'sd115/*115:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd2; xpc10nz <= 10'sd116/*116:xpc10nz*/; end 10'sd118/*118:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_404e_945d_1368_85ff; xpc10nz <= 10'sd119/*119:xpc10nz*/; end 10'sd119/*119:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd3; xpc10nz <= 10'sd120/*120:xpc10nz*/; end 10'sd122/*122:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4050_d199_9779_7ce6; xpc10nz <= 10'sd123/*123:xpc10nz*/; end 10'sd123/*123:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd4; xpc10nz <= 10'sd124/*124:xpc10nz*/; end 10'sd126/*126:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4052_8028_f36c_0964; xpc10nz <= 10'sd127/*127:xpc10nz*/; end 10'sd127/*127:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd5; xpc10nz <= 10'sd128/*128:xpc10nz*/; end 10'sd130/*130:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4054_59c6_a55d_3d88; xpc10nz <= 10'sd131/*131:xpc10nz*/; end 10'sd131/*131:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd6; xpc10nz <= 10'sd132/*132:xpc10nz*/; end 10'sd134/*134:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4056_62c0_e919_c3b0; xpc10nz <= 10'sd135/*135:xpc10nz*/; end 10'sd135/*135:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd7; xpc10nz <= 10'sd136/*136:xpc10nz*/; end 10'sd138/*138:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4058_9fd4_339c_5742; xpc10nz <= 10'sd139/*139:xpc10nz*/; end 10'sd139/*139:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd8; xpc10nz <= 10'sd140/*140:xpc10nz*/; end 10'sd140/*140:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd3; xpc10nz <= 10'sd141/*141:xpc10nz*/; end 10'sd141/*141:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd142/*142:xpc10nz*/; end 10'sd144/*144:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_405b_1636_38c5_9330; xpc10nz <= 10'sd145/*145:xpc10nz*/; end 10'sd145/*145:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1; xpc10nz <= 10'sd146/*146:xpc10nz*/; end 10'sd148/*148:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_405d_cba2_0b3f_bb82; xpc10nz <= 10'sd149/*149:xpc10nz*/; end 10'sd149/*149:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd2; xpc10nz <= 10'sd150/*150:xpc10nz*/; end 10'sd152/*152:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4060_6332_b963_0d88; xpc10nz <= 10'sd153/*153:xpc10nz*/; end 10'sd153/*153:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd3; xpc10nz <= 10'sd154/*154:xpc10nz*/; end 10'sd156/*156:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4062_06b7_cbec_f549; xpc10nz <= 10'sd157/*157:xpc10nz*/; end 10'sd157/*157:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd4; xpc10nz <= 10'sd158/*158:xpc10nz*/; end 10'sd160/*160:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4063_d430_9384_a76a; xpc10nz <= 10'sd161/*161:xpc10nz*/; end 10'sd161/*161:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd5; xpc10nz <= 10'sd162/*162:xpc10nz*/; end 10'sd164/*164:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4065_cfcf_08ab_84f5; xpc10nz <= 10'sd165/*165:xpc10nz*/; end 10'sd165/*165:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd6; xpc10nz <= 10'sd166/*166:xpc10nz*/; end 10'sd168/*168:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4067_fe30_8989_78a8; xpc10nz <= 10'sd169/*169:xpc10nz*/; end 10'sd169/*169:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd7; xpc10nz <= 10'sd170/*170:xpc10nz*/; end 10'sd172/*172:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_406a_6468_974a_6b20; xpc10nz <= 10'sd173/*173:xpc10nz*/; end 10'sd173/*173:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd8; xpc10nz <= 10'sd174/*174:xpc10nz*/; end 10'sd174/*174:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd4; xpc10nz <= 10'sd175/*175:xpc10nz*/; end 10'sd175/*175:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd176/*176:xpc10nz*/; end 10'sd178/*178:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_406d_080c_a66b_75d7; xpc10nz <= 10'sd179/*179:xpc10nz*/; end 10'sd179/*179:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1; xpc10nz <= 10'sd180/*180:xpc10nz*/; end 10'sd182/*182:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_406f_ef41_1d76_34d4; xpc10nz <= 10'sd183/*183:xpc10nz*/; end 10'sd183/*183:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd2; xpc10nz <= 10'sd184/*184:xpc10nz*/; end 10'sd186/*186:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4071_9063_d034_36a8; xpc10nz <= 10'sd187/*187:xpc10nz*/; end 10'sd187/*187:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd3; xpc10nz <= 10'sd188/*188:xpc10nz*/; end 10'sd190/*190:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4073_5207_6506_3c20; xpc10nz <= 10'sd191/*191:xpc10nz*/; end 10'sd191/*191:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd4; xpc10nz <= 10'sd192/*192:xpc10nz*/; end 10'sd194/*194:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4075_40a1_bbed_4224; xpc10nz <= 10'sd195/*195:xpc10nz*/; end 10'sd195/*195:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd5; xpc10nz <= 10'sd196/*196:xpc10nz*/; end 10'sd198/*198:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4077_60b1_e851_c8c2; xpc10nz <= 10'sd199/*199:xpc10nz*/; end 10'sd199/*199:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd6; xpc10nz <= 10'sd200/*200:xpc10nz*/; end 10'sd202/*202:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4079_b72a_1926_c33c; xpc10nz <= 10'sd203/*203:xpc10nz*/; end 10'sd203/*203:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd7; xpc10nz <= 10'sd204/*204:xpc10nz*/; end 10'sd206/*206:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_407c_497b_1baa_a38f; xpc10nz <= 10'sd207/*207:xpc10nz*/; end 10'sd207/*207:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd8; xpc10nz <= 10'sd208/*208:xpc10nz*/; end 10'sd208/*208:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd5; xpc10nz <= 10'sd209/*209:xpc10nz*/; end 10'sd209/*209:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd210/*210:xpc10nz*/; end 10'sd212/*212:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_407f_1da1_04d5_4d84; xpc10nz <= 10'sd213/*213:xpc10nz*/; end 10'sd213/*213:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1; xpc10nz <= 10'sd214/*214:xpc10nz*/; end 10'sd216/*216:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4081_1d18_8f75_5109; xpc10nz <= 10'sd217/*217:xpc10nz*/; end 10'sd217/*217:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd2; xpc10nz <= 10'sd218/*218:xpc10nz*/; end 10'sd220/*220:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4082_d334_9dcd_d924; xpc10nz <= 10'sd221/*221:xpc10nz*/; end 10'sd221/*221:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd3; xpc10nz <= 10'sd222/*222:xpc10nz*/; end 10'sd224/*224:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4084_b520_472f_3ba8; xpc10nz <= 10'sd225/*225:xpc10nz*/; end 10'sd225/*225:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd4; xpc10nz <= 10'sd226/*226:xpc10nz*/; end 10'sd228/*228:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4086_c73d_1b1a_5b39; xpc10nz <= 10'sd229/*229:xpc10nz*/; end 10'sd229/*229:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd5; xpc10nz <= 10'sd230/*230:xpc10nz*/; end 10'sd232/*232:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4089_0e5c_d103_6459; xpc10nz <= 10'sd233/*233:xpc10nz*/; end 10'sd233/*233:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd6; xpc10nz <= 10'sd234/*234:xpc10nz*/; end 10'sd236/*236:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_408b_8fcc_7f83_bb2f; xpc10nz <= 10'sd237/*237:xpc10nz*/; end 10'sd237/*237:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd7; xpc10nz <= 10'sd238/*238:xpc10nz*/; end 10'sd240/*240:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_408e_5160_f2aa_811b; xpc10nz <= 10'sd241/*241:xpc10nz*/; end 10'sd241/*241:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd8; xpc10nz <= 10'sd242/*242:xpc10nz*/; end 10'sd242/*242:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd6; xpc10nz <= 10'sd243/*243:xpc10nz*/; end 10'sd243/*243:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd244/*244:xpc10nz*/; end 10'sd246/*246:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4090_acc2_1f10_fa36; xpc10nz <= 10'sd247/*247:xpc10nz*/; end 10'sd247/*247:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1; xpc10nz <= 10'sd248/*248:xpc10nz*/; end 10'sd250/*250:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4092_57a2_555f_79a2; xpc10nz <= 10'sd251/*251:xpc10nz*/; end 10'sd251/*251:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd2; xpc10nz <= 10'sd252/*252:xpc10nz*/; end 10'sd254/*254:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4094_2d32_911c_38ff; xpc10nz <= 10'sd255/*255:xpc10nz*/; end 10'sd255/*255:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd3; xpc10nz <= 10'sd256/*256:xpc10nz*/; end 10'sd258/*258:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4096_31b7_9f9f_0b7f; xpc10nz <= 10'sd259/*259:xpc10nz*/; end 10'sd259/*259:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd4; xpc10nz <= 10'sd260/*260:xpc10nz*/; end 10'sd262/*262:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_4098_69e3_95fb_bfd9; xpc10nz <= 10'sd263/*263:xpc10nz*/; end 10'sd263/*263:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd5; xpc10nz <= 10'sd264/*264:xpc10nz*/; end 10'sd266/*266:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_409a_dae0_be94_eca3; xpc10nz <= 10'sd267/*267:xpc10nz*/; end 10'sd267/*267:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd6; xpc10nz <= 10'sd268/*268:xpc10nz*/; end 10'sd270/*270:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_409d_8a5d_9e70_9de7; xpc10nz <= 10'sd271/*271:xpc10nz*/; end 10'sd271/*271:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd7; xpc10nz <= 10'sd272/*272:xpc10nz*/; end 10'sd274/*274:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_40a0_3f4d_1724_56d9; xpc10nz <= 10'sd275/*275:xpc10nz*/; end 10'sd275/*275:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd8; xpc10nz <= 10'sd276/*276:xpc10nz*/; end 10'sd276/*276:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd7; xpc10nz <= 10'sd277/*277:xpc10nz*/; end 10'sd277/*277:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd278/*278:xpc10nz*/; end 10'sd280/*280:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_40a1_df3b_330e_5f89; xpc10nz <= 10'sd281/*281:xpc10nz*/; end 10'sd281/*281:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1; xpc10nz <= 10'sd282/*282:xpc10nz*/; end 10'sd284/*284:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_40a3_a8c1_1e8f_cf7e; xpc10nz <= 10'sd285/*285:xpc10nz*/; end 10'sd285/*285:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd2; xpc10nz <= 10'sd286/*286:xpc10nz*/; end 10'sd288/*288:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_40a5_a007_a19e_310b; xpc10nz <= 10'sd289/*289:xpc10nz*/; end 10'sd289/*289:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd3; xpc10nz <= 10'sd290/*290:xpc10nz*/; end 10'sd292/*292:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_40a7_c9a1_fe94_6926; xpc10nz <= 10'sd293/*293:xpc10nz*/; end 10'sd293/*293:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd4; xpc10nz <= 10'sd294/*294:xpc10nz*/; end 10'sd296/*296:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_40aa_2a98_9809_a6de; xpc10nz <= 10'sd297/*297:xpc10nz*/; end 10'sd297/*297:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd5; xpc10nz <= 10'sd298/*298:xpc10nz*/; end 10'sd300/*300:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_40ac_c874_a73d_d128; xpc10nz <= 10'sd301/*301:xpc10nz*/; end 10'sd301/*301:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd6; xpc10nz <= 10'sd302/*302:xpc10nz*/; end 10'sd304/*304:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_40af_a94d_1e5d_9946; xpc10nz <= 10'sd305/*305:xpc10nz*/; end 10'sd305/*305:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd7; xpc10nz <= 10'sd306/*306:xpc10nz*/; end 10'sd308/*308:xpc10nz*/: begin TMm1_V_1_GP <= 64'h_40b1_69ea_6a4d_144d; xpc10nz <= 10'sd309/*309:xpc10nz*/; end 10'sd309/*309:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd8; xpc10nz <= 10'sd310/*310:xpc10nz*/; end 10'sd310/*310:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd8; xpc10nz <= 10'sd311/*311:xpc10nz*/; end 10'sd311/*311:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd312/*312:xpc10nz*/; end 10'sd313/*313:xpc10nz*/: begin Tlge0_9_V_4 <= ((xpc10nz==10'sd313/*313:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold); xpc10nz <= 10'sd314/*314:xpc10nz*/; end 10'sd320/*320:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1; xpc10nz <= 10'sd321/*321:xpc10nz*/; end 10'sd322/*322:xpc10nz*/: begin Tlge0_9_V_4 <= ((xpc10nz==10'sd322/*322:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold); xpc10nz <= 10'sd323/*323:xpc10nz*/; end 10'sd329/*329:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd2; xpc10nz <= 10'sd330/*330:xpc10nz*/; end 10'sd331/*331:xpc10nz*/: begin Tlge0_9_V_4 <= ((xpc10nz==10'sd331/*331:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold); xpc10nz <= 10'sd332/*332:xpc10nz*/; end 10'sd338/*338:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd3; xpc10nz <= 10'sd339/*339:xpc10nz*/; end 10'sd340/*340:xpc10nz*/: begin Tlge0_9_V_4 <= ((xpc10nz==10'sd340/*340:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold); xpc10nz <= 10'sd341/*341:xpc10nz*/; end 10'sd347/*347:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd4; xpc10nz <= 10'sd348/*348:xpc10nz*/; end 10'sd349/*349:xpc10nz*/: begin Tlge0_9_V_4 <= ((xpc10nz==10'sd349/*349:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold); xpc10nz <= 10'sd350/*350:xpc10nz*/; end 10'sd356/*356:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd5; xpc10nz <= 10'sd357/*357:xpc10nz*/; end 10'sd358/*358:xpc10nz*/: begin Tlge0_9_V_4 <= ((xpc10nz==10'sd358/*358:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold); xpc10nz <= 10'sd359/*359:xpc10nz*/; end 10'sd365/*365:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd6; xpc10nz <= 10'sd366/*366:xpc10nz*/; end 10'sd367/*367:xpc10nz*/: begin Tlge0_9_V_4 <= ((xpc10nz==10'sd367/*367:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold); xpc10nz <= 10'sd368/*368:xpc10nz*/; end 10'sd374/*374:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd7; xpc10nz <= 10'sd375/*375:xpc10nz*/; end 10'sd376/*376:xpc10nz*/: begin Tlge0_9_V_4 <= ((xpc10nz==10'sd376/*376:xpc10nz*/)? A_FPD_CC_SCALbx44_ARG0_RDD0: FPDCCSCALbx44ARG0RRh10hold); xpc10nz <= 10'sd377/*377:xpc10nz*/; end 10'sd383/*383:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd8; xpc10nz <= 10'sd384/*384:xpc10nz*/; end 10'sd384/*384:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd385/*385:xpc10nz*/; end 10'sd385/*385:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd0; xpc10nz <= 10'sd386/*386:xpc10nz*/; end 10'sd389/*389:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1; xpc10nz <= 10'sd390/*390:xpc10nz*/; end 10'sd393/*393:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd2; xpc10nz <= 10'sd394/*394:xpc10nz*/; end 10'sd397/*397:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd3; xpc10nz <= 10'sd398/*398:xpc10nz*/; end 10'sd401/*401:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd4; xpc10nz <= 10'sd402/*402:xpc10nz*/; end 10'sd405/*405:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd5; xpc10nz <= 10'sd406/*406:xpc10nz*/; end 10'sd409/*409:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd6; xpc10nz <= 10'sd410/*410:xpc10nz*/; end 10'sd413/*413:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd7; xpc10nz <= 10'sd414/*414:xpc10nz*/; end 10'sd417/*417:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd8; xpc10nz <= 10'sd418/*418:xpc10nz*/; end 10'sd418/*418:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1; xpc10nz <= 10'sd419/*419:xpc10nz*/; end 10'sd419/*419:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd0; xpc10nz <= 10'sd420/*420:xpc10nz*/; end 10'sd423/*423:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1; xpc10nz <= 10'sd424/*424:xpc10nz*/; end 10'sd427/*427:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd2; xpc10nz <= 10'sd428/*428:xpc10nz*/; end 10'sd431/*431:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd3; xpc10nz <= 10'sd432/*432:xpc10nz*/; end 10'sd435/*435:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd4; xpc10nz <= 10'sd436/*436:xpc10nz*/; end 10'sd439/*439:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd5; xpc10nz <= 10'sd440/*440:xpc10nz*/; end 10'sd443/*443:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd6; xpc10nz <= 10'sd444/*444:xpc10nz*/; end 10'sd447/*447:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd7; xpc10nz <= 10'sd448/*448:xpc10nz*/; end 10'sd451/*451:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd8; xpc10nz <= 10'sd452/*452:xpc10nz*/; end 10'sd452/*452:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd2; xpc10nz <= 10'sd453/*453:xpc10nz*/; end 10'sd453/*453:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd0; xpc10nz <= 10'sd454/*454:xpc10nz*/; end 10'sd457/*457:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1; xpc10nz <= 10'sd458/*458:xpc10nz*/; end 10'sd461/*461:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd2; xpc10nz <= 10'sd462/*462:xpc10nz*/; end 10'sd465/*465:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd3; xpc10nz <= 10'sd466/*466:xpc10nz*/; end 10'sd469/*469:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd4; xpc10nz <= 10'sd470/*470:xpc10nz*/; end 10'sd473/*473:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd5; xpc10nz <= 10'sd474/*474:xpc10nz*/; end 10'sd477/*477:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd6; xpc10nz <= 10'sd478/*478:xpc10nz*/; end 10'sd481/*481:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd7; xpc10nz <= 10'sd482/*482:xpc10nz*/; end 10'sd485/*485:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd8; xpc10nz <= 10'sd486/*486:xpc10nz*/; end 10'sd486/*486:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd3; xpc10nz <= 10'sd487/*487:xpc10nz*/; end 10'sd487/*487:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd0; xpc10nz <= 10'sd488/*488:xpc10nz*/; end 10'sd491/*491:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1; xpc10nz <= 10'sd492/*492:xpc10nz*/; end 10'sd495/*495:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd2; xpc10nz <= 10'sd496/*496:xpc10nz*/; end 10'sd499/*499:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd3; xpc10nz <= 10'sd500/*500:xpc10nz*/; end 10'sd503/*503:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd4; xpc10nz <= 10'sd504/*504:xpc10nz*/; end 10'sd507/*507:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd5; xpc10nz <= 10'sd508/*508:xpc10nz*/; end 10'sd511/*511:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd6; xpc10nz <= 10'sd512/*512:xpc10nz*/; end 10'sd515/*515:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd7; xpc10nz <= 10'sd516/*516:xpc10nz*/; end 10'sd519/*519:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd8; xpc10nz <= 10'sd520/*520:xpc10nz*/; end 10'sd520/*520:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd4; xpc10nz <= 10'sd521/*521:xpc10nz*/; end 10'sd521/*521:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd0; xpc10nz <= 10'sd522/*522:xpc10nz*/; end 10'sd525/*525:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1; xpc10nz <= 10'sd526/*526:xpc10nz*/; end 10'sd529/*529:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd2; xpc10nz <= 10'sd530/*530:xpc10nz*/; end 10'sd533/*533:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd3; xpc10nz <= 10'sd534/*534:xpc10nz*/; end 10'sd537/*537:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd4; xpc10nz <= 10'sd538/*538:xpc10nz*/; end 10'sd541/*541:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd5; xpc10nz <= 10'sd542/*542:xpc10nz*/; end 10'sd545/*545:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd6; xpc10nz <= 10'sd546/*546:xpc10nz*/; end 10'sd549/*549:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd7; xpc10nz <= 10'sd550/*550:xpc10nz*/; end 10'sd553/*553:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd8; xpc10nz <= 10'sd554/*554:xpc10nz*/; end 10'sd554/*554:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd5; xpc10nz <= 10'sd555/*555:xpc10nz*/; end 10'sd555/*555:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd0; xpc10nz <= 10'sd556/*556:xpc10nz*/; end 10'sd559/*559:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1; xpc10nz <= 10'sd560/*560:xpc10nz*/; end 10'sd563/*563:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd2; xpc10nz <= 10'sd564/*564:xpc10nz*/; end 10'sd567/*567:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd3; xpc10nz <= 10'sd568/*568:xpc10nz*/; end 10'sd571/*571:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd4; xpc10nz <= 10'sd572/*572:xpc10nz*/; end 10'sd575/*575:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd5; xpc10nz <= 10'sd576/*576:xpc10nz*/; end 10'sd579/*579:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd6; xpc10nz <= 10'sd580/*580:xpc10nz*/; end 10'sd583/*583:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd7; xpc10nz <= 10'sd584/*584:xpc10nz*/; end 10'sd587/*587:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd8; xpc10nz <= 10'sd588/*588:xpc10nz*/; end 10'sd588/*588:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd6; xpc10nz <= 10'sd589/*589:xpc10nz*/; end 10'sd589/*589:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd0; xpc10nz <= 10'sd590/*590:xpc10nz*/; end 10'sd593/*593:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1; xpc10nz <= 10'sd594/*594:xpc10nz*/; end 10'sd597/*597:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd2; xpc10nz <= 10'sd598/*598:xpc10nz*/; end 10'sd601/*601:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd3; xpc10nz <= 10'sd602/*602:xpc10nz*/; end 10'sd605/*605:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd4; xpc10nz <= 10'sd606/*606:xpc10nz*/; end 10'sd609/*609:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd5; xpc10nz <= 10'sd610/*610:xpc10nz*/; end 10'sd613/*613:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd6; xpc10nz <= 10'sd614/*614:xpc10nz*/; end 10'sd617/*617:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd7; xpc10nz <= 10'sd618/*618:xpc10nz*/; end 10'sd621/*621:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd8; xpc10nz <= 10'sd622/*622:xpc10nz*/; end 10'sd622/*622:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd7; xpc10nz <= 10'sd623/*623:xpc10nz*/; end 10'sd623/*623:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd0; xpc10nz <= 10'sd624/*624:xpc10nz*/; end 10'sd627/*627:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1; xpc10nz <= 10'sd628/*628:xpc10nz*/; end 10'sd631/*631:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd2; xpc10nz <= 10'sd632/*632:xpc10nz*/; end 10'sd635/*635:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd3; xpc10nz <= 10'sd636/*636:xpc10nz*/; end 10'sd639/*639:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd4; xpc10nz <= 10'sd640/*640:xpc10nz*/; end 10'sd643/*643:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd5; xpc10nz <= 10'sd644/*644:xpc10nz*/; end 10'sd647/*647:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd6; xpc10nz <= 10'sd648/*648:xpc10nz*/; end 10'sd651/*651:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd7; xpc10nz <= 10'sd652/*652:xpc10nz*/; end 10'sd655/*655:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd8; xpc10nz <= 10'sd656/*656:xpc10nz*/; end 10'sd656/*656:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd8; xpc10nz <= 10'sd657/*657:xpc10nz*/; end 10'sd657/*657:xpc10nz*/: xpc10nz <= 10'sd658/*658:xpc10nz*/; 10'sd658/*658:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd659/*659:xpc10nz*/; end 10'sd659/*659:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd0; xpc10nz <= 10'sd660/*660:xpc10nz*/; end 10'sd661/*661:xpc10nz*/: xpc10nz <= 10'sd662/*662:xpc10nz*/; 10'sd662/*662:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1; xpc10nz <= 10'sd663/*663:xpc10nz*/; end 10'sd664/*664:xpc10nz*/: xpc10nz <= 10'sd665/*665:xpc10nz*/; 10'sd665/*665:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd2; xpc10nz <= 10'sd666/*666:xpc10nz*/; end 10'sd667/*667:xpc10nz*/: xpc10nz <= 10'sd668/*668:xpc10nz*/; 10'sd668/*668:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd3; xpc10nz <= 10'sd669/*669:xpc10nz*/; end 10'sd670/*670:xpc10nz*/: xpc10nz <= 10'sd671/*671:xpc10nz*/; 10'sd671/*671:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd4; xpc10nz <= 10'sd672/*672:xpc10nz*/; end 10'sd673/*673:xpc10nz*/: xpc10nz <= 10'sd674/*674:xpc10nz*/; 10'sd674/*674:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd5; xpc10nz <= 10'sd675/*675:xpc10nz*/; end 10'sd676/*676:xpc10nz*/: xpc10nz <= 10'sd677/*677:xpc10nz*/; 10'sd677/*677:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd6; xpc10nz <= 10'sd678/*678:xpc10nz*/; end 10'sd679/*679:xpc10nz*/: xpc10nz <= 10'sd680/*680:xpc10nz*/; 10'sd680/*680:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd7; xpc10nz <= 10'sd681/*681:xpc10nz*/; end 10'sd682/*682:xpc10nz*/: xpc10nz <= 10'sd683/*683:xpc10nz*/; 10'sd683/*683:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd8; xpc10nz <= 10'sd684/*684:xpc10nz*/; end 10'sd684/*684:xpc10nz*/: xpc10nz <= 10'sd685/*685:xpc10nz*/; 10'sd685/*685:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd686/*686:xpc10nz*/; end 10'sd687/*687:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd688/*688:xpc10nz*/; end 10'sd691/*691:xpc10nz*/: begin lTMTMaV_1_GP <= 32'sd0; xpc10nz <= 10'sd692/*692:xpc10nz*/; end 10'sd693/*693:xpc10nz*/: begin lTMTMaV_1_GP <= 32'sd0; xpc10nz <= 10'sd694/*694:xpc10nz*/; end 10'sd695/*695:xpc10nz*/: begin lTMTMaV_1_GP <= 32'sd0; xpc10nz <= 10'sd696/*696:xpc10nz*/; end 10'sd698/*698:xpc10nz*/: xpc10nz <= 10'sd699/*699:xpc10nz*/; 10'sd699/*699:xpc10nz*/: begin lTMTMaV_1_GP <= 32'sd0; xpc10nz <= 10'sd700/*700:xpc10nz*/; end 10'sd701/*701:xpc10nz*/: xpc10nz <= 10'sd701/*701:xpc10nz*/; 10'sd702/*702:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd703/*703:xpc10nz*/; end 10'sd719/*719:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd720/*720:xpc10nz*/; end 10'sd724/*724:xpc10nz*/: xpc10nz <= 10'sd858/*858:xpc10nz*/; 10'sd725/*725:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1; xpc10nz <= 10'sd726/*726:xpc10nz*/; end 10'sd727/*727:xpc10nz*/: xpc10nz <= 10'sd728/*728:xpc10nz*/; 10'sd728/*728:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd729/*729:xpc10nz*/; end 10'sd730/*730:xpc10nz*/: xpc10nz <= 10'sd821/*821:xpc10nz*/; 10'sd731/*731:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd7; xpc10nz <= 10'sd732/*732:xpc10nz*/; end 10'sd733/*733:xpc10nz*/: xpc10nz <= 10'sd734/*734:xpc10nz*/; 10'sd734/*734:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd735/*735:xpc10nz*/; end 10'sd736/*736:xpc10nz*/: xpc10nz <= 10'sd772/*772:xpc10nz*/; 10'sd737/*737:xpc10nz*/: xpc10nz <= 10'sd738/*738:xpc10nz*/; 10'sd738/*738:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd739/*739:xpc10nz*/; end 10'sd740/*740:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd741/*741:xpc10nz*/; end 10'sd742/*742:xpc10nz*/: xpc10nz <= 10'sd745/*745:xpc10nz*/; 10'sd743/*743:xpc10nz*/: begin lTMTMaV_1_GP <= 32'sd1+lTMTMaV_1_GP; xpc10nz <= 10'sd744/*744:xpc10nz*/; end 10'sd745/*745:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd746/*746:xpc10nz*/; end 10'sd747/*747:xpc10nz*/: xpc10nz <= 10'sd745/*745:xpc10nz*/; 10'sd748/*748:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd0; xpc10nz <= 10'sd749/*749:xpc10nz*/; end 10'sd758/*758:xpc10nz*/: xpc10nz <= 10'sd761/*761:xpc10nz*/; 10'sd759/*759:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd760/*760:xpc10nz*/; end 10'sd761/*761:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1+TMm1_V_2_GP; xpc10nz <= 10'sd762/*762:xpc10nz*/; end 10'sd771/*771:xpc10nz*/: xpc10nz <= 10'sd761/*761:xpc10nz*/; 10'sd772/*772:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd773/*773:xpc10nz*/; end 10'sd774/*774:xpc10nz*/: xpc10nz <= 10'sd772/*772:xpc10nz*/; 10'sd775/*775:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd776/*776:xpc10nz*/; end 10'sd796/*796:xpc10nz*/: xpc10nz <= 10'sd799/*799:xpc10nz*/; 10'sd797/*797:xpc10nz*/: begin TMp1_V_0_GP <= -32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd798/*798:xpc10nz*/; end 10'sd799/*799:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1+TMm1_V_2_GP; xpc10nz <= 10'sd800/*800:xpc10nz*/; end 10'sd820/*820:xpc10nz*/: xpc10nz <= 10'sd799/*799:xpc10nz*/; 10'sd821/*821:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd822/*822:xpc10nz*/; end 10'sd823/*823:xpc10nz*/: xpc10nz <= 10'sd821/*821:xpc10nz*/; 10'sd824/*824:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd0; xpc10nz <= 10'sd825/*825:xpc10nz*/; end 10'sd839/*839:xpc10nz*/: xpc10nz <= 10'sd842/*842:xpc10nz*/; 10'sd840/*840:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd841/*841:xpc10nz*/; end 10'sd842/*842:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1+TMm1_V_2_GP; xpc10nz <= 10'sd843/*843:xpc10nz*/; end 10'sd857/*857:xpc10nz*/: xpc10nz <= 10'sd842/*842:xpc10nz*/; 10'sd858/*858:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd859/*859:xpc10nz*/; end 10'sd863/*863:xpc10nz*/: xpc10nz <= 10'sd858/*858:xpc10nz*/; 10'sd864/*864:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd865/*865:xpc10nz*/; end 10'sd881/*881:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd882/*882:xpc10nz*/; end 10'sd883/*883:xpc10nz*/: xpc10nz <= 10'sd887/*887:xpc10nz*/; 10'sd885/*885:xpc10nz*/: begin lTMTMaV_1_GP <= 32'sd1+lTMTMaV_1_GP; xpc10nz <= 10'sd886/*886:xpc10nz*/; end 10'sd887/*887:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd888/*888:xpc10nz*/; end 10'sd889/*889:xpc10nz*/: xpc10nz <= 10'sd887/*887:xpc10nz*/; 10'sd892/*892:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd0; xpc10nz <= 10'sd893/*893:xpc10nz*/; end 10'sd902/*902:xpc10nz*/: xpc10nz <= 10'sd905/*905:xpc10nz*/; 10'sd903/*903:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd904/*904:xpc10nz*/; end 10'sd905/*905:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1+TMm1_V_2_GP; xpc10nz <= 10'sd906/*906:xpc10nz*/; end 10'sd915/*915:xpc10nz*/: xpc10nz <= 10'sd905/*905:xpc10nz*/; 10'sd916/*916:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd917/*917:xpc10nz*/; end 10'sd918/*918:xpc10nz*/: xpc10nz <= 10'sd922/*922:xpc10nz*/; 10'sd920/*920:xpc10nz*/: begin lTMTMaV_1_GP <= 32'sd1+lTMTMaV_1_GP; xpc10nz <= 10'sd921/*921:xpc10nz*/; end 10'sd922/*922:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd923/*923:xpc10nz*/; end 10'sd924/*924:xpc10nz*/: xpc10nz <= 10'sd922/*922:xpc10nz*/; 10'sd925/*925:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd0; xpc10nz <= 10'sd926/*926:xpc10nz*/; end 10'sd927/*927:xpc10nz*/: xpc10nz <= 10'sd931/*931:xpc10nz*/; 10'sd929/*929:xpc10nz*/: begin lTMTMaV_1_GP <= 32'sd1+lTMTMaV_1_GP; xpc10nz <= 10'sd930/*930:xpc10nz*/; end 10'sd931/*931:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd932/*932:xpc10nz*/; end 10'sd933/*933:xpc10nz*/: xpc10nz <= 10'sd931/*931:xpc10nz*/; 10'sd943/*943:xpc10nz*/: xpc10nz <= 10'sd945/*945:xpc10nz*/; 10'sd949/*949:xpc10nz*/: begin lTMTMaV_1_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd950/*950:xpc10nz*/; end 10'sd968/*968:xpc10nz*/: xpc10nz <= 10'sd945/*945:xpc10nz*/; 10'sd969/*969:xpc10nz*/: begin lTMTMaV_1_GP <= 32'sd1+lTMTMaV_1_GP; xpc10nz <= 10'sd970/*970:xpc10nz*/; end 10'sd981/*981:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1+TMm1_V_2_GP; xpc10nz <= 10'sd982/*982:xpc10nz*/; end 10'sd984/*984:xpc10nz*/: begin TMp1_V_0_GP <= 32'sd1+TMp1_V_0_GP; xpc10nz <= 10'sd985/*985:xpc10nz*/; end 10'sd987/*987:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd0; xpc10nz <= 10'sd988/*988:xpc10nz*/; end 10'sd989/*989:xpc10nz*/: xpc10nz <= 10'sd991/*991:xpc10nz*/; 10'sd991/*991:xpc10nz*/: begin TMm1_V_2_GP <= 32'sd1+TMm1_V_2_GP; xpc10nz <= 10'sd992/*992:xpc10nz*/; end 10'sd993/*993:xpc10nz*/: xpc10nz <= 10'sd991/*991:xpc10nz*/; endcase if (CVFPADDER10RRh10shot3) CVFPADDER10RRh10hold <= CVFPADDER10_FPRR; CVFPADDER10RRh10shot1 <= CVFPADDER10RRh10shot0; CVFPADDER10RRh10shot2 <= CVFPADDER10RRh10shot1; CVFPADDER10RRh10shot3 <= CVFPADDER10RRh10shot2; if (CVFPADDER12RRh10shot3) CVFPADDER12RRh10hold <= CVFPADDER12_FPRR; CVFPADDER12RRh10shot1 <= CVFPADDER12RRh10shot0; CVFPADDER12RRh10shot2 <= CVFPADDER12RRh10shot1; CVFPADDER12RRh10shot3 <= CVFPADDER12RRh10shot2; if (CVFPADDER14RRh10shot3) CVFPADDER14RRh10hold <= CVFPADDER14_FPRR; CVFPADDER14RRh10shot1 <= CVFPADDER14RRh10shot0; CVFPADDER14RRh10shot2 <= CVFPADDER14RRh10shot1; CVFPADDER14RRh10shot3 <= CVFPADDER14RRh10shot2; if (CVFPADDER16RRh10shot3) CVFPADDER16RRh10hold <= CVFPADDER16_FPRR; CVFPADDER16RRh10shot1 <= CVFPADDER16RRh10shot0; CVFPADDER16RRh10shot2 <= CVFPADDER16RRh10shot1; CVFPADDER16RRh10shot3 <= CVFPADDER16RRh10shot2; if (fpcvt10RRh10shot1) fpcvt10RRh10hold <= fpcvt10_result; fpcvt10RRh10shot1 <= fpcvt10RRh10shot0; if (fpcvt12RRh10shot1) fpcvt12RRh10hold <= fpcvt12_result; fpcvt12RRh10shot1 <= fpcvt12RRh10shot0; if (CVFPMULTIPLIER10RRh10shot2) CVFPMULTIPLIER10RRh10hold <= CVFPMULTIPLIER10_FPRR; CVFPMULTIPLIER10RRh10shot1 <= CVFPMULTIPLIER10RRh10shot0; CVFPMULTIPLIER10RRh10shot2 <= CVFPMULTIPLIER10RRh10shot1; if (CVFPMULTIPLIER12RRh10shot2) CVFPMULTIPLIER12RRh10hold <= CVFPMULTIPLIER12_FPRR; CVFPMULTIPLIER12RRh10shot1 <= CVFPMULTIPLIER12RRh10shot0; CVFPMULTIPLIER12RRh10shot2 <= CVFPMULTIPLIER12RRh10shot1; if (FPDCCSCALbx46ARH0RRh10shot0) FPDCCSCALbx46ARH0RRh10hold <= A_FPD_CC_SCALbx46_ARH0_RDD0; if (CVFPMULTIPLIER14RRh10shot2) CVFPMULTIPLIER14RRh10hold <= CVFPMULTIPLIER14_FPRR; CVFPMULTIPLIER14RRh10shot1 <= CVFPMULTIPLIER14RRh10shot0; CVFPMULTIPLIER14RRh10shot2 <= CVFPMULTIPLIER14RRh10shot1; if (CVFPMULTIPLIER16RRh10shot2) CVFPMULTIPLIER16RRh10hold <= CVFPMULTIPLIER16_FPRR; CVFPMULTIPLIER16RRh10shot1 <= CVFPMULTIPLIER16RRh10shot0; CVFPMULTIPLIER16RRh10shot2 <= CVFPMULTIPLIER16RRh10shot1; if (CVFPMULTIPLIER18RRh10shot2) CVFPMULTIPLIER18RRh10hold <= CVFPMULTIPLIER18_FPRR; CVFPMULTIPLIER18RRh10shot1 <= CVFPMULTIPLIER18RRh10shot0; CVFPMULTIPLIER18RRh10shot2 <= CVFPMULTIPLIER18RRh10shot1; if (CVFPDIVIDER10RRh10shot4) CVFPDIVIDER10RRh10hold <= CVFPDIVIDER10_FPRR; CVFPDIVIDER10RRh10shot1 <= CVFPDIVIDER10RRh10shot0; CVFPDIVIDER10RRh10shot2 <= CVFPDIVIDER10RRh10shot1; CVFPDIVIDER10RRh10shot3 <= CVFPDIVIDER10RRh10shot2; CVFPDIVIDER10RRh10shot4 <= CVFPDIVIDER10RRh10shot3; if (CVFPMULTIPLIER20RRh10shot2) CVFPMULTIPLIER20RRh10hold <= CVFPMULTIPLIER20_FPRR; CVFPMULTIPLIER20RRh10shot1 <= CVFPMULTIPLIER20RRh10shot0; CVFPMULTIPLIER20RRh10shot2 <= CVFPMULTIPLIER20RRh10shot1; if (CVFPDIVIDER12RRh10shot4) CVFPDIVIDER12RRh10hold <= CVFPDIVIDER12_FPRR; CVFPDIVIDER12RRh10shot1 <= CVFPDIVIDER12RRh10shot0; CVFPDIVIDER12RRh10shot2 <= CVFPDIVIDER12RRh10shot1; CVFPDIVIDER12RRh10shot3 <= CVFPDIVIDER12RRh10shot2; CVFPDIVIDER12RRh10shot4 <= CVFPDIVIDER12RRh10shot3; if (CVFPMULTIPLIER22RRh10shot2) CVFPMULTIPLIER22RRh10hold <= CVFPMULTIPLIER22_FPRR; CVFPMULTIPLIER22RRh10shot1 <= CVFPMULTIPLIER22RRh10shot0; CVFPMULTIPLIER22RRh10shot2 <= CVFPMULTIPLIER22RRh10shot1; if (CVFPMULTIPLIER24RRh10shot2) CVFPMULTIPLIER24RRh10hold <= CVFPMULTIPLIER24_FPRR; CVFPMULTIPLIER24RRh10shot1 <= CVFPMULTIPLIER24RRh10shot0; CVFPMULTIPLIER24RRh10shot2 <= CVFPMULTIPLIER24RRh10shot1; if (fpcvt14RRh10shot1) fpcvt14RRh10hold <= fpcvt14_result; fpcvt14RRh10shot1 <= fpcvt14RRh10shot0; if (fpcvt16RRh10shot1) fpcvt16RRh10hold <= fpcvt16_result; fpcvt16RRh10shot1 <= fpcvt16RRh10shot0; if (CVFPMULTIPLIER26RRh10shot2) CVFPMULTIPLIER26RRh10hold <= CVFPMULTIPLIER26_FPRR; CVFPMULTIPLIER26RRh10shot1 <= CVFPMULTIPLIER26RRh10shot0; CVFPMULTIPLIER26RRh10shot2 <= CVFPMULTIPLIER26RRh10shot1; CVFPADDER18RRh10shot1 <= CVFPADDER18RRh10shot0; CVFPADDER18RRh10shot2 <= CVFPADDER18RRh10shot1; CVFPADDER18RRh10shot3 <= CVFPADDER18RRh10shot2; if (FPDCCSCALbx36ARC0RRh10shot0) FPDCCSCALbx36ARC0RRh10hold <= A_FPD_CC_SCALbx36_ARC0_RDD0; if (CVFPDIVIDER14RRh10shot4) CVFPDIVIDER14RRh10hold <= CVFPDIVIDER14_FPRR; CVFPDIVIDER14RRh10shot1 <= CVFPDIVIDER14RRh10shot0; CVFPDIVIDER14RRh10shot2 <= CVFPDIVIDER14RRh10shot1; CVFPDIVIDER14RRh10shot3 <= CVFPDIVIDER14RRh10shot2; CVFPDIVIDER14RRh10shot4 <= CVFPDIVIDER14RRh10shot3; if (CVFPDIVIDER16RRh10shot4) CVFPDIVIDER16RRh10hold <= CVFPDIVIDER16_FPRR; CVFPDIVIDER16RRh10shot1 <= CVFPDIVIDER16RRh10shot0; CVFPDIVIDER16RRh10shot2 <= CVFPDIVIDER16RRh10shot1; CVFPDIVIDER16RRh10shot3 <= CVFPDIVIDER16RRh10shot2; CVFPDIVIDER16RRh10shot4 <= CVFPDIVIDER16RRh10shot3; CVFPMULTIPLIER28RRh10shot1 <= CVFPMULTIPLIER28RRh10shot0; CVFPMULTIPLIER28RRh10shot2 <= CVFPMULTIPLIER28RRh10shot1; CVFPADDER20RRh10shot1 <= CVFPADDER20RRh10shot0; CVFPADDER20RRh10shot2 <= CVFPADDER20RRh10shot1; CVFPADDER20RRh10shot3 <= CVFPADDER20RRh10shot2; FPDCCSCALbx34ARB0RRh12shot0 <= ((xpc10nz==10'sd970/*970:xpc10nz*/) || (xpc10nz==10'sd950/*950:xpc10nz*/)) && (lTMTMaV_1_GP <32'sd8) || ((xpc10nz==10'sd992/*992:xpc10nz*/) || (xpc10nz==10'sd937/*937:xpc10nz*/) || (xpc10nz==10'sd961/*961:xpc10nz*/) || (xpc10nz==10'sd988/*988:xpc10nz*/)) && (TMm1_V_2_GP<32'sd8); CVFPADDER20RRh10shot0 <= ((TMm1_V_2_GP<32'sd8)? (xpc10nz==10'sd898/*898:xpc10nz*/) || (xpc10nz==10'sd911/*911:xpc10nz*/): (xpc10nz ==10'sd801/*801:xpc10nz*/) || (xpc10nz==10'sd777/*777:xpc10nz*/)) || ((xpc10nz==10'sd844/*844:xpc10nz*/) || (xpc10nz==10'sd826 /*826:xpc10nz*/)) && (TMm1_V_2_GP>=TMp1_V_0_GP) || (xpc10nz==10'sd368/*368:xpc10nz*/) || (xpc10nz==10'sd359/*359:xpc10nz*/) || (xpc10nz==10'sd377/*377:xpc10nz*/) || ((xpc10nz==10'sd767/*767:xpc10nz*/) || (xpc10nz==10'sd754/*754:xpc10nz*/)) && (TMm1_V_2_GP <32'sh8) || ((xpc10nz==10'sd955/*955:xpc10nz*/) || (xpc10nz==10'sd975/*975:xpc10nz*/)) && (lTMTMaV_1_GP<32'sd8) || ((xpc10nz ==10'sd709/*709:xpc10nz*/) || (xpc10nz==10'sd871/*871:xpc10nz*/)) && (TMp1_V_0_GP<32'sd8); CVFPMULTIPLIER28RRh10shot0 <= (TMp1_V_0_GP<32'sd8) && (xpc10nz==10'sd868/*868:xpc10nz*/) || ((xpc10nz==10'sd908/*908:xpc10nz*/) || (xpc10nz==10'sd895/*895:xpc10nz*/)) && (TMm1_V_2_GP<32'sd8) || ((xpc10nz==10'sd972/*972:xpc10nz*/) || (xpc10nz==10'sd952 /*952:xpc10nz*/)) && (lTMTMaV_1_GP<32'sd8); FPDCCSCALbx34ARB0RRh10shot0 <= ((TMm1_V_2_GP<32'sd8)? (xpc10nz==10'sd962/*962:xpc10nz*/) || (xpc10nz==10'sd936/*936:xpc10nz*/) || (xpc10nz==10'sd893/*893:xpc10nz*/) || (xpc10nz==10'sd812/*812:xpc10nz*/) || (xpc10nz==10'sd788/*788:xpc10nz*/) || (xpc10nz ==10'sd906/*906:xpc10nz*/): (xpc10nz==10'sd776/*776:xpc10nz*/) || (xpc10nz==10'sd800/*800:xpc10nz*/)) || (xpc10nz==10'sd678 /*678:xpc10nz*/) || (xpc10nz==10'sd672/*672:xpc10nz*/) || (xpc10nz==10'sd666/*666:xpc10nz*/) || (xpc10nz==10'sd660/*660:xpc10nz*/) || (xpc10nz==10'sd663/*663:xpc10nz*/) || (xpc10nz==10'sd669/*669:xpc10nz*/) || (xpc10nz==10'sd675/*675:xpc10nz*/) || (xpc10nz ==10'sd681/*681:xpc10nz*/) || ((xpc10nz==10'sd951/*951:xpc10nz*/) || (xpc10nz==10'sd971/*971:xpc10nz*/)) && (lTMTMaV_1_GP <32'sd8) || ((xpc10nz==10'sd926/*926:xpc10nz*/) || (xpc10nz==10'sd932/*932:xpc10nz*/)) && (TMp1_V_0_GP<32'sd8); CVFPDIVIDER16RRh10shot0 <= (TMm1_V_2_GP<32'sd8) && (xpc10nz==10'sd963/*963:xpc10nz*/); CVFPDIVIDER14RRh10shot0 <= (TMm1_V_2_GP<32'sd8) && (xpc10nz==10'sd938/*938:xpc10nz*/); FPDCCSCALbx32ARA0RRh10shot0 <= ((xpc10nz==10'sd825/*825:xpc10nz*/) || (xpc10nz==10'sd843/*843:xpc10nz*/)) && (TMm1_V_2_GP <TMp1_V_0_GP) || ((xpc10nz==10'sd893/*893:xpc10nz*/) || (xpc10nz==10'sd906/*906:xpc10nz*/)) && (TMm1_V_2_GP<32'sd8) || ((xpc10nz==10'sd917/*917:xpc10nz*/) || (xpc10nz==10'sd923/*923:xpc10nz*/)) && (TMp1_V_0_GP<32'sd8); FPDCCSCALbx36ARC0RRh10shot0 <= ((xpc10nz==10'sd882/*882:xpc10nz*/) || (xpc10nz==10'sd888/*888:xpc10nz*/)) && (TMp1_V_0_GP <32'sd8); CVFPADDER18RRh10shot0 <= (xpc10nz==10'sd350/*350:xpc10nz*/) || ((xpc10nz==10'sd853/*853:xpc10nz*/) || (xpc10nz==10'sd835 /*835:xpc10nz*/)) && (TMm1_V_2_GP<TMp1_V_0_GP) || ((xpc10nz==10'sd816/*816:xpc10nz*/) || (xpc10nz==10'sd792/*792:xpc10nz*/)) && (TMm1_V_2_GP<32'sd8) || ((xpc10nz==10'sd713/*713:xpc10nz*/) || (xpc10nz==10'sd875/*875:xpc10nz*/)) && (TMp1_V_0_GP<32'sd8 ); CVFPMULTIPLIER26RRh10shot0 <= (TMp1_V_0_GP<32'sd8) && (xpc10nz==10'sd868/*868:xpc10nz*/); fpcvt16RRh10shot0 <= (TMp1_V_0_GP<32'sd8) && (xpc10nz==10'sd865/*865:xpc10nz*/); fpcvt14RRh10shot0 <= (TMp1_V_0_GP<32'sd8) && (xpc10nz==10'sd865/*865:xpc10nz*/); FPDCCSCALbx38ARD0RRh10shot0 <= ((TMp1_V_0_GP<32'sd8)? (xpc10nz==10'sd723/*723:xpc10nz*/) || (xpc10nz==10'sd862/*862:xpc10nz*/): (xpc10nz ==10'sd859/*859:xpc10nz*/) || (xpc10nz==10'sd720/*720:xpc10nz*/)) || ((xpc10nz==10'sd843/*843:xpc10nz*/) || (xpc10nz==10'sd825 /*825:xpc10nz*/)) && (TMm1_V_2_GP>=TMp1_V_0_GP); CVFPMULTIPLIER24RRh10shot0 <= (TMm1_V_2_GP<TMp1_V_0_GP) && (xpc10nz==10'sd850/*850:xpc10nz*/); FPDCCSCALbx40ARE0RRh10shot0 <= ((xpc10nz==10'sd800/*800:xpc10nz*/) || (xpc10nz==10'sd776/*776:xpc10nz*/)) && (TMm1_V_2_GP >=32'sd8) || ((xpc10nz==10'sd825/*825:xpc10nz*/) || (xpc10nz==10'sd843/*843:xpc10nz*/)) && (TMm1_V_2_GP<TMp1_V_0_GP) || ((xpc10nz==10'sd729/*729:xpc10nz*/) || (xpc10nz==10'sd822/*822:xpc10nz*/)) && (TMp1_V_0_GP<32'sh8); CVFPMULTIPLIER22RRh10shot0 <= (TMm1_V_2_GP<TMp1_V_0_GP) && (xpc10nz==10'sd832/*832:xpc10nz*/); CVFPDIVIDER12RRh10shot0 <= (TMm1_V_2_GP>=32'sd8) && (xpc10nz==10'sd805/*805:xpc10nz*/); CVFPMULTIPLIER20RRh10shot0 <= (TMm1_V_2_GP<32'sd8) && (xpc10nz==10'sd813/*813:xpc10nz*/); FPDCCSCALbx42ARF0RRh10shot0 <= ((xpc10nz==10'sd776/*776:xpc10nz*/) || (xpc10nz==10'sd800/*800:xpc10nz*/)) && (TMm1_V_2_GP <32'sd8) || ((xpc10nz==10'sd762/*762:xpc10nz*/) || (xpc10nz==10'sd749/*749:xpc10nz*/)) && (TMm1_V_2_GP<32'sh8) || ((xpc10nz ==10'sd735/*735:xpc10nz*/) || (xpc10nz==10'sd773/*773:xpc10nz*/)) && (TMp1_V_0_GP<32'sh8); CVFPDIVIDER10RRh10shot0 <= (TMm1_V_2_GP>=32'sd8) && (xpc10nz==10'sd781/*781:xpc10nz*/); CVFPMULTIPLIER18RRh10shot0 <= (TMm1_V_2_GP<32'sd8) && (xpc10nz==10'sd789/*789:xpc10nz*/); CVFPMULTIPLIER16RRh10shot0 <= (TMm1_V_2_GP<32'sh8) && (xpc10nz==10'sd764/*764:xpc10nz*/); FPDCCSCALbx44ARG0RRh10shot0 <= (xpc10nz==10'sd648/*648:xpc10nz*/) || (xpc10nz==10'sd640/*640:xpc10nz*/) || (xpc10nz==10'sd632 /*632:xpc10nz*/) || (xpc10nz==10'sd624/*624:xpc10nz*/) || (xpc10nz==10'sd614/*614:xpc10nz*/) || (xpc10nz==10'sd606/*606:xpc10nz*/) || (xpc10nz==10'sd598/*598:xpc10nz*/) || (xpc10nz==10'sd590/*590:xpc10nz*/) || (xpc10nz==10'sd580/*580:xpc10nz*/) || (xpc10nz ==10'sd572/*572:xpc10nz*/) || (xpc10nz==10'sd564/*564:xpc10nz*/) || (xpc10nz==10'sd556/*556:xpc10nz*/) || (xpc10nz==10'sd546 /*546:xpc10nz*/) || (xpc10nz==10'sd538/*538:xpc10nz*/) || (xpc10nz==10'sd530/*530:xpc10nz*/) || (xpc10nz==10'sd522/*522:xpc10nz*/) || (xpc10nz==10'sd512/*512:xpc10nz*/) || (xpc10nz==10'sd504/*504:xpc10nz*/) || (xpc10nz==10'sd496/*496:xpc10nz*/) || (xpc10nz ==10'sd488/*488:xpc10nz*/) || (xpc10nz==10'sd478/*478:xpc10nz*/) || (xpc10nz==10'sd470/*470:xpc10nz*/) || (xpc10nz==10'sd462 /*462:xpc10nz*/) || (xpc10nz==10'sd454/*454:xpc10nz*/) || (xpc10nz==10'sd444/*444:xpc10nz*/) || (xpc10nz==10'sd436/*436:xpc10nz*/) || (xpc10nz==10'sd428/*428:xpc10nz*/) || (xpc10nz==10'sd420/*420:xpc10nz*/) || (xpc10nz==10'sd410/*410:xpc10nz*/) || (xpc10nz ==10'sd402/*402:xpc10nz*/) || (xpc10nz==10'sd394/*394:xpc10nz*/) || (xpc10nz==10'sd386/*386:xpc10nz*/) || (xpc10nz==10'sd366 /*366:xpc10nz*/) || (xpc10nz==10'sd348/*348:xpc10nz*/) || (xpc10nz==10'sd330/*330:xpc10nz*/) || (xpc10nz==10'sd312/*312:xpc10nz*/) || (xpc10nz==10'sd321/*321:xpc10nz*/) || (xpc10nz==10'sd339/*339:xpc10nz*/) || (xpc10nz==10'sd357/*357:xpc10nz*/) || (xpc10nz ==10'sd375/*375:xpc10nz*/) || (xpc10nz==10'sd390/*390:xpc10nz*/) || (xpc10nz==10'sd398/*398:xpc10nz*/) || (xpc10nz==10'sd406 /*406:xpc10nz*/) || (xpc10nz==10'sd414/*414:xpc10nz*/) || (xpc10nz==10'sd424/*424:xpc10nz*/) || (xpc10nz==10'sd432/*432:xpc10nz*/) || (xpc10nz==10'sd440/*440:xpc10nz*/) || (xpc10nz==10'sd448/*448:xpc10nz*/) || (xpc10nz==10'sd458/*458:xpc10nz*/) || (xpc10nz ==10'sd466/*466:xpc10nz*/) || (xpc10nz==10'sd474/*474:xpc10nz*/) || (xpc10nz==10'sd482/*482:xpc10nz*/) || (xpc10nz==10'sd492 /*492:xpc10nz*/) || (xpc10nz==10'sd500/*500:xpc10nz*/) || (xpc10nz==10'sd508/*508:xpc10nz*/) || (xpc10nz==10'sd516/*516:xpc10nz*/) || (xpc10nz==10'sd526/*526:xpc10nz*/) || (xpc10nz==10'sd534/*534:xpc10nz*/) || (xpc10nz==10'sd542/*542:xpc10nz*/) || (xpc10nz ==10'sd550/*550:xpc10nz*/) || (xpc10nz==10'sd560/*560:xpc10nz*/) || (xpc10nz==10'sd568/*568:xpc10nz*/) || (xpc10nz==10'sd576 /*576:xpc10nz*/) || (xpc10nz==10'sd584/*584:xpc10nz*/) || (xpc10nz==10'sd594/*594:xpc10nz*/) || (xpc10nz==10'sd602/*602:xpc10nz*/) || (xpc10nz==10'sd610/*610:xpc10nz*/) || (xpc10nz==10'sd618/*618:xpc10nz*/) || (xpc10nz==10'sd628/*628:xpc10nz*/) || (xpc10nz ==10'sd636/*636:xpc10nz*/) || (xpc10nz==10'sd644/*644:xpc10nz*/) || (xpc10nz==10'sd652/*652:xpc10nz*/) || ((xpc10nz==10'sd749 /*749:xpc10nz*/) || (xpc10nz==10'sd762/*762:xpc10nz*/)) && (TMm1_V_2_GP<32'sh8); CVFPMULTIPLIER14RRh10shot0 <= (TMm1_V_2_GP<32'sh8) && (xpc10nz==10'sd751/*751:xpc10nz*/); FPDCCSCALbx46ARH0RRh10shot0 <= ((xpc10nz==10'sd741/*741:xpc10nz*/) || (xpc10nz==10'sd746/*746:xpc10nz*/)) && (TMp1_V_0_GP <32'sh8); CVFPMULTIPLIER12RRh10shot0 <= (TMp1_V_0_GP<32'sd8) && (xpc10nz==10'sd706/*706:xpc10nz*/); CVFPMULTIPLIER10RRh10shot0 <= (TMp1_V_0_GP<32'sd8) && (xpc10nz==10'sd706/*706:xpc10nz*/); fpcvt12RRh10shot0 <= (TMp1_V_0_GP<32'sd8) && (xpc10nz==10'sd703/*703:xpc10nz*/); fpcvt10RRh10shot0 <= (TMp1_V_0_GP<32'sd8) && (xpc10nz==10'sd703/*703:xpc10nz*/); CVFPADDER16RRh10shot0 <= (xpc10nz==10'sd341/*341:xpc10nz*/); CVFPADDER14RRh10shot0 <= (xpc10nz==10'sd332/*332:xpc10nz*/); CVFPADDER12RRh10shot0 <= (xpc10nz==10'sd323/*323:xpc10nz*/); CVFPADDER10RRh10shot0 <= (xpc10nz==10'sd314/*314:xpc10nz*/); if ((xpc10nz==10'sd0/*0:xpc10nz*/)) xpc10nz <= 10'sd1/*1:xpc10nz*/; if ((xpc10nz==10'sd1/*1:xpc10nz*/)) xpc10nz <= 10'sd2/*2:xpc10nz*/; if ((xpc10nz==10'sd2/*2:xpc10nz*/)) xpc10nz <= 10'sd3/*3:xpc10nz*/; if ((xpc10nz==10'sd3/*3:xpc10nz*/)) xpc10nz <= 10'sd4/*4:xpc10nz*/; if ((xpc10nz==10'sd4/*4:xpc10nz*/)) xpc10nz <= 10'sd5/*5:xpc10nz*/; if ((xpc10nz==10'sd5/*5:xpc10nz*/)) xpc10nz <= 10'sd6/*6:xpc10nz*/; if ((xpc10nz==10'sd6/*6:xpc10nz*/)) xpc10nz <= 10'sd7/*7:xpc10nz*/; if ((xpc10nz==10'sd7/*7:xpc10nz*/)) xpc10nz <= 10'sd8/*8:xpc10nz*/; if ((xpc10nz==10'sd8/*8:xpc10nz*/)) xpc10nz <= 10'sd9/*9:xpc10nz*/; if ((xpc10nz==10'sd9/*9:xpc10nz*/)) xpc10nz <= 10'sd10/*10:xpc10nz*/; if ((xpc10nz==10'sd10/*10:xpc10nz*/)) xpc10nz <= 10'sd11/*11:xpc10nz*/; if ((xpc10nz==10'sd11/*11:xpc10nz*/)) xpc10nz <= 10'sd12/*12:xpc10nz*/; if ((xpc10nz==10'sd12/*12:xpc10nz*/)) xpc10nz <= 10'sd13/*13:xpc10nz*/; if ((xpc10nz==10'sd13/*13:xpc10nz*/)) xpc10nz <= 10'sd14/*14:xpc10nz*/; if ((xpc10nz==10'sd14/*14:xpc10nz*/)) xpc10nz <= 10'sd15/*15:xpc10nz*/; if ((xpc10nz==10'sd15/*15:xpc10nz*/)) xpc10nz <= 10'sd16/*16:xpc10nz*/; if ((xpc10nz==10'sd16/*16:xpc10nz*/)) xpc10nz <= 10'sd17/*17:xpc10nz*/; if ((xpc10nz==10'sd17/*17:xpc10nz*/)) xpc10nz <= 10'sd18/*18:xpc10nz*/; if ((xpc10nz==10'sd18/*18:xpc10nz*/)) xpc10nz <= 10'sd19/*19:xpc10nz*/; if ((xpc10nz==10'sd19/*19:xpc10nz*/)) xpc10nz <= 10'sd20/*20:xpc10nz*/; if ((xpc10nz==10'sd20/*20:xpc10nz*/)) xpc10nz <= 10'sd21/*21:xpc10nz*/; if ((xpc10nz==10'sd21/*21:xpc10nz*/)) xpc10nz <= 10'sd22/*22:xpc10nz*/; if ((xpc10nz==10'sd22/*22:xpc10nz*/)) xpc10nz <= 10'sd23/*23:xpc10nz*/; if ((xpc10nz==10'sd23/*23:xpc10nz*/)) xpc10nz <= 10'sd24/*24:xpc10nz*/; if ((xpc10nz==10'sd25/*25:xpc10nz*/)) xpc10nz <= 10'sd26/*26:xpc10nz*/; if ((xpc10nz==10'sd26/*26:xpc10nz*/)) xpc10nz <= 10'sd27/*27:xpc10nz*/; if ((xpc10nz==10'sd27/*27:xpc10nz*/)) xpc10nz <= 10'sd28/*28:xpc10nz*/; if ((xpc10nz==10'sd28/*28:xpc10nz*/)) xpc10nz <= 10'sd29/*29:xpc10nz*/; if ((xpc10nz==10'sd29/*29:xpc10nz*/)) xpc10nz <= 10'sd30/*30:xpc10nz*/; if ((xpc10nz==10'sd30/*30:xpc10nz*/)) xpc10nz <= 10'sd31/*31:xpc10nz*/; if ((xpc10nz==10'sd31/*31:xpc10nz*/)) xpc10nz <= 10'sd32/*32:xpc10nz*/; if ((xpc10nz==10'sd32/*32:xpc10nz*/)) xpc10nz <= 10'sd33/*33:xpc10nz*/; if ((xpc10nz==10'sd33/*33:xpc10nz*/)) xpc10nz <= 10'sd34/*34:xpc10nz*/; if ((xpc10nz==10'sd34/*34:xpc10nz*/)) xpc10nz <= 10'sd35/*35:xpc10nz*/; if ((xpc10nz==10'sd35/*35:xpc10nz*/)) xpc10nz <= 10'sd36/*36:xpc10nz*/; if ((xpc10nz==10'sd36/*36:xpc10nz*/)) xpc10nz <= 10'sd37/*37:xpc10nz*/; if ((xpc10nz==10'sd40/*40:xpc10nz*/)) xpc10nz <= 10'sd41/*41:xpc10nz*/; if ((xpc10nz==10'sd41/*41:xpc10nz*/)) xpc10nz <= 10'sd42/*42:xpc10nz*/; if ((xpc10nz==10'sd44/*44:xpc10nz*/)) xpc10nz <= 10'sd45/*45:xpc10nz*/; if ((xpc10nz==10'sd45/*45:xpc10nz*/)) xpc10nz <= 10'sd46/*46:xpc10nz*/; if ((xpc10nz==10'sd48/*48:xpc10nz*/)) xpc10nz <= 10'sd49/*49:xpc10nz*/; if ((xpc10nz==10'sd49/*49:xpc10nz*/)) xpc10nz <= 10'sd50/*50:xpc10nz*/; if ((xpc10nz==10'sd52/*52:xpc10nz*/)) xpc10nz <= 10'sd53/*53:xpc10nz*/; if ((xpc10nz==10'sd53/*53:xpc10nz*/)) xpc10nz <= 10'sd54/*54:xpc10nz*/; if ((xpc10nz==10'sd56/*56:xpc10nz*/)) xpc10nz <= 10'sd57/*57:xpc10nz*/; if ((xpc10nz==10'sd57/*57:xpc10nz*/)) xpc10nz <= 10'sd58/*58:xpc10nz*/; if ((xpc10nz==10'sd60/*60:xpc10nz*/)) xpc10nz <= 10'sd61/*61:xpc10nz*/; if ((xpc10nz==10'sd61/*61:xpc10nz*/)) xpc10nz <= 10'sd62/*62:xpc10nz*/; if ((xpc10nz==10'sd64/*64:xpc10nz*/)) xpc10nz <= 10'sd65/*65:xpc10nz*/; if ((xpc10nz==10'sd65/*65:xpc10nz*/)) xpc10nz <= 10'sd66/*66:xpc10nz*/; if ((xpc10nz==10'sd68/*68:xpc10nz*/)) xpc10nz <= 10'sd69/*69:xpc10nz*/; if ((xpc10nz==10'sd69/*69:xpc10nz*/)) xpc10nz <= 10'sd70/*70:xpc10nz*/; if ((xpc10nz==10'sd74/*74:xpc10nz*/)) xpc10nz <= 10'sd75/*75:xpc10nz*/; if ((xpc10nz==10'sd75/*75:xpc10nz*/)) xpc10nz <= 10'sd76/*76:xpc10nz*/; if ((xpc10nz==10'sd78/*78:xpc10nz*/)) xpc10nz <= 10'sd79/*79:xpc10nz*/; if ((xpc10nz==10'sd79/*79:xpc10nz*/)) xpc10nz <= 10'sd80/*80:xpc10nz*/; if ((xpc10nz==10'sd82/*82:xpc10nz*/)) xpc10nz <= 10'sd83/*83:xpc10nz*/; if ((xpc10nz==10'sd83/*83:xpc10nz*/)) xpc10nz <= 10'sd84/*84:xpc10nz*/; if ((xpc10nz==10'sd86/*86:xpc10nz*/)) xpc10nz <= 10'sd87/*87:xpc10nz*/; if ((xpc10nz==10'sd87/*87:xpc10nz*/)) xpc10nz <= 10'sd88/*88:xpc10nz*/; if ((xpc10nz==10'sd90/*90:xpc10nz*/)) xpc10nz <= 10'sd91/*91:xpc10nz*/; if ((xpc10nz==10'sd91/*91:xpc10nz*/)) xpc10nz <= 10'sd92/*92:xpc10nz*/; if ((xpc10nz==10'sd94/*94:xpc10nz*/)) xpc10nz <= 10'sd95/*95:xpc10nz*/; if ((xpc10nz==10'sd95/*95:xpc10nz*/)) xpc10nz <= 10'sd96/*96:xpc10nz*/; if ((xpc10nz==10'sd98/*98:xpc10nz*/)) xpc10nz <= 10'sd99/*99:xpc10nz*/; if ((xpc10nz==10'sd99/*99:xpc10nz*/)) xpc10nz <= 10'sd100/*100:xpc10nz*/; if ((xpc10nz==10'sd102/*102:xpc10nz*/)) xpc10nz <= 10'sd103/*103:xpc10nz*/; if ((xpc10nz==10'sd103/*103:xpc10nz*/)) xpc10nz <= 10'sd104/*104:xpc10nz*/; if ((xpc10nz==10'sd108/*108:xpc10nz*/)) xpc10nz <= 10'sd109/*109:xpc10nz*/; if ((xpc10nz==10'sd109/*109:xpc10nz*/)) xpc10nz <= 10'sd110/*110:xpc10nz*/; if ((xpc10nz==10'sd112/*112:xpc10nz*/)) xpc10nz <= 10'sd113/*113:xpc10nz*/; if ((xpc10nz==10'sd113/*113:xpc10nz*/)) xpc10nz <= 10'sd114/*114:xpc10nz*/; if ((xpc10nz==10'sd116/*116:xpc10nz*/)) xpc10nz <= 10'sd117/*117:xpc10nz*/; if ((xpc10nz==10'sd117/*117:xpc10nz*/)) xpc10nz <= 10'sd118/*118:xpc10nz*/; if ((xpc10nz==10'sd120/*120:xpc10nz*/)) xpc10nz <= 10'sd121/*121:xpc10nz*/; if ((xpc10nz==10'sd121/*121:xpc10nz*/)) xpc10nz <= 10'sd122/*122:xpc10nz*/; if ((xpc10nz==10'sd124/*124:xpc10nz*/)) xpc10nz <= 10'sd125/*125:xpc10nz*/; if ((xpc10nz==10'sd125/*125:xpc10nz*/)) xpc10nz <= 10'sd126/*126:xpc10nz*/; if ((xpc10nz==10'sd128/*128:xpc10nz*/)) xpc10nz <= 10'sd129/*129:xpc10nz*/; if ((xpc10nz==10'sd129/*129:xpc10nz*/)) xpc10nz <= 10'sd130/*130:xpc10nz*/; if ((xpc10nz==10'sd132/*132:xpc10nz*/)) xpc10nz <= 10'sd133/*133:xpc10nz*/; if ((xpc10nz==10'sd133/*133:xpc10nz*/)) xpc10nz <= 10'sd134/*134:xpc10nz*/; if ((xpc10nz==10'sd136/*136:xpc10nz*/)) xpc10nz <= 10'sd137/*137:xpc10nz*/; if ((xpc10nz==10'sd137/*137:xpc10nz*/)) xpc10nz <= 10'sd138/*138:xpc10nz*/; if ((xpc10nz==10'sd142/*142:xpc10nz*/)) xpc10nz <= 10'sd143/*143:xpc10nz*/; if ((xpc10nz==10'sd143/*143:xpc10nz*/)) xpc10nz <= 10'sd144/*144:xpc10nz*/; if ((xpc10nz==10'sd146/*146:xpc10nz*/)) xpc10nz <= 10'sd147/*147:xpc10nz*/; if ((xpc10nz==10'sd147/*147:xpc10nz*/)) xpc10nz <= 10'sd148/*148:xpc10nz*/; if ((xpc10nz==10'sd150/*150:xpc10nz*/)) xpc10nz <= 10'sd151/*151:xpc10nz*/; if ((xpc10nz==10'sd151/*151:xpc10nz*/)) xpc10nz <= 10'sd152/*152:xpc10nz*/; if ((xpc10nz==10'sd154/*154:xpc10nz*/)) xpc10nz <= 10'sd155/*155:xpc10nz*/; if ((xpc10nz==10'sd155/*155:xpc10nz*/)) xpc10nz <= 10'sd156/*156:xpc10nz*/; if ((xpc10nz==10'sd158/*158:xpc10nz*/)) xpc10nz <= 10'sd159/*159:xpc10nz*/; if ((xpc10nz==10'sd159/*159:xpc10nz*/)) xpc10nz <= 10'sd160/*160:xpc10nz*/; if ((xpc10nz==10'sd162/*162:xpc10nz*/)) xpc10nz <= 10'sd163/*163:xpc10nz*/; if ((xpc10nz==10'sd163/*163:xpc10nz*/)) xpc10nz <= 10'sd164/*164:xpc10nz*/; if ((xpc10nz==10'sd166/*166:xpc10nz*/)) xpc10nz <= 10'sd167/*167:xpc10nz*/; if ((xpc10nz==10'sd167/*167:xpc10nz*/)) xpc10nz <= 10'sd168/*168:xpc10nz*/; if ((xpc10nz==10'sd170/*170:xpc10nz*/)) xpc10nz <= 10'sd171/*171:xpc10nz*/; if ((xpc10nz==10'sd171/*171:xpc10nz*/)) xpc10nz <= 10'sd172/*172:xpc10nz*/; if ((xpc10nz==10'sd176/*176:xpc10nz*/)) xpc10nz <= 10'sd177/*177:xpc10nz*/; if ((xpc10nz==10'sd177/*177:xpc10nz*/)) xpc10nz <= 10'sd178/*178:xpc10nz*/; if ((xpc10nz==10'sd180/*180:xpc10nz*/)) xpc10nz <= 10'sd181/*181:xpc10nz*/; if ((xpc10nz==10'sd181/*181:xpc10nz*/)) xpc10nz <= 10'sd182/*182:xpc10nz*/; if ((xpc10nz==10'sd184/*184:xpc10nz*/)) xpc10nz <= 10'sd185/*185:xpc10nz*/; if ((xpc10nz==10'sd185/*185:xpc10nz*/)) xpc10nz <= 10'sd186/*186:xpc10nz*/; if ((xpc10nz==10'sd188/*188:xpc10nz*/)) xpc10nz <= 10'sd189/*189:xpc10nz*/; if ((xpc10nz==10'sd189/*189:xpc10nz*/)) xpc10nz <= 10'sd190/*190:xpc10nz*/; if ((xpc10nz==10'sd192/*192:xpc10nz*/)) xpc10nz <= 10'sd193/*193:xpc10nz*/; if ((xpc10nz==10'sd193/*193:xpc10nz*/)) xpc10nz <= 10'sd194/*194:xpc10nz*/; if ((xpc10nz==10'sd196/*196:xpc10nz*/)) xpc10nz <= 10'sd197/*197:xpc10nz*/; if ((xpc10nz==10'sd197/*197:xpc10nz*/)) xpc10nz <= 10'sd198/*198:xpc10nz*/; if ((xpc10nz==10'sd200/*200:xpc10nz*/)) xpc10nz <= 10'sd201/*201:xpc10nz*/; if ((xpc10nz==10'sd201/*201:xpc10nz*/)) xpc10nz <= 10'sd202/*202:xpc10nz*/; if ((xpc10nz==10'sd204/*204:xpc10nz*/)) xpc10nz <= 10'sd205/*205:xpc10nz*/; if ((xpc10nz==10'sd205/*205:xpc10nz*/)) xpc10nz <= 10'sd206/*206:xpc10nz*/; if ((xpc10nz==10'sd210/*210:xpc10nz*/)) xpc10nz <= 10'sd211/*211:xpc10nz*/; if ((xpc10nz==10'sd211/*211:xpc10nz*/)) xpc10nz <= 10'sd212/*212:xpc10nz*/; if ((xpc10nz==10'sd214/*214:xpc10nz*/)) xpc10nz <= 10'sd215/*215:xpc10nz*/; if ((xpc10nz==10'sd215/*215:xpc10nz*/)) xpc10nz <= 10'sd216/*216:xpc10nz*/; if ((xpc10nz==10'sd218/*218:xpc10nz*/)) xpc10nz <= 10'sd219/*219:xpc10nz*/; if ((xpc10nz==10'sd219/*219:xpc10nz*/)) xpc10nz <= 10'sd220/*220:xpc10nz*/; if ((xpc10nz==10'sd222/*222:xpc10nz*/)) xpc10nz <= 10'sd223/*223:xpc10nz*/; if ((xpc10nz==10'sd223/*223:xpc10nz*/)) xpc10nz <= 10'sd224/*224:xpc10nz*/; if ((xpc10nz==10'sd226/*226:xpc10nz*/)) xpc10nz <= 10'sd227/*227:xpc10nz*/; if ((xpc10nz==10'sd227/*227:xpc10nz*/)) xpc10nz <= 10'sd228/*228:xpc10nz*/; if ((xpc10nz==10'sd230/*230:xpc10nz*/)) xpc10nz <= 10'sd231/*231:xpc10nz*/; if ((xpc10nz==10'sd231/*231:xpc10nz*/)) xpc10nz <= 10'sd232/*232:xpc10nz*/; if ((xpc10nz==10'sd234/*234:xpc10nz*/)) xpc10nz <= 10'sd235/*235:xpc10nz*/; if ((xpc10nz==10'sd235/*235:xpc10nz*/)) xpc10nz <= 10'sd236/*236:xpc10nz*/; if ((xpc10nz==10'sd238/*238:xpc10nz*/)) xpc10nz <= 10'sd239/*239:xpc10nz*/; if ((xpc10nz==10'sd239/*239:xpc10nz*/)) xpc10nz <= 10'sd240/*240:xpc10nz*/; if ((xpc10nz==10'sd244/*244:xpc10nz*/)) xpc10nz <= 10'sd245/*245:xpc10nz*/; if ((xpc10nz==10'sd245/*245:xpc10nz*/)) xpc10nz <= 10'sd246/*246:xpc10nz*/; if ((xpc10nz==10'sd248/*248:xpc10nz*/)) xpc10nz <= 10'sd249/*249:xpc10nz*/; if ((xpc10nz==10'sd249/*249:xpc10nz*/)) xpc10nz <= 10'sd250/*250:xpc10nz*/; if ((xpc10nz==10'sd252/*252:xpc10nz*/)) xpc10nz <= 10'sd253/*253:xpc10nz*/; if ((xpc10nz==10'sd253/*253:xpc10nz*/)) xpc10nz <= 10'sd254/*254:xpc10nz*/; if ((xpc10nz==10'sd256/*256:xpc10nz*/)) xpc10nz <= 10'sd257/*257:xpc10nz*/; if ((xpc10nz==10'sd257/*257:xpc10nz*/)) xpc10nz <= 10'sd258/*258:xpc10nz*/; if ((xpc10nz==10'sd260/*260:xpc10nz*/)) xpc10nz <= 10'sd261/*261:xpc10nz*/; if ((xpc10nz==10'sd261/*261:xpc10nz*/)) xpc10nz <= 10'sd262/*262:xpc10nz*/; if ((xpc10nz==10'sd264/*264:xpc10nz*/)) xpc10nz <= 10'sd265/*265:xpc10nz*/; if ((xpc10nz==10'sd265/*265:xpc10nz*/)) xpc10nz <= 10'sd266/*266:xpc10nz*/; if ((xpc10nz==10'sd268/*268:xpc10nz*/)) xpc10nz <= 10'sd269/*269:xpc10nz*/; if ((xpc10nz==10'sd269/*269:xpc10nz*/)) xpc10nz <= 10'sd270/*270:xpc10nz*/; if ((xpc10nz==10'sd272/*272:xpc10nz*/)) xpc10nz <= 10'sd273/*273:xpc10nz*/; if ((xpc10nz==10'sd273/*273:xpc10nz*/)) xpc10nz <= 10'sd274/*274:xpc10nz*/; if ((xpc10nz==10'sd278/*278:xpc10nz*/)) xpc10nz <= 10'sd279/*279:xpc10nz*/; if ((xpc10nz==10'sd279/*279:xpc10nz*/)) xpc10nz <= 10'sd280/*280:xpc10nz*/; if ((xpc10nz==10'sd282/*282:xpc10nz*/)) xpc10nz <= 10'sd283/*283:xpc10nz*/; if ((xpc10nz==10'sd283/*283:xpc10nz*/)) xpc10nz <= 10'sd284/*284:xpc10nz*/; if ((xpc10nz==10'sd286/*286:xpc10nz*/)) xpc10nz <= 10'sd287/*287:xpc10nz*/; if ((xpc10nz==10'sd287/*287:xpc10nz*/)) xpc10nz <= 10'sd288/*288:xpc10nz*/; if ((xpc10nz==10'sd290/*290:xpc10nz*/)) xpc10nz <= 10'sd291/*291:xpc10nz*/; if ((xpc10nz==10'sd291/*291:xpc10nz*/)) xpc10nz <= 10'sd292/*292:xpc10nz*/; if ((xpc10nz==10'sd294/*294:xpc10nz*/)) xpc10nz <= 10'sd295/*295:xpc10nz*/; if ((xpc10nz==10'sd295/*295:xpc10nz*/)) xpc10nz <= 10'sd296/*296:xpc10nz*/; if ((xpc10nz==10'sd298/*298:xpc10nz*/)) xpc10nz <= 10'sd299/*299:xpc10nz*/; if ((xpc10nz==10'sd299/*299:xpc10nz*/)) xpc10nz <= 10'sd300/*300:xpc10nz*/; if ((xpc10nz==10'sd302/*302:xpc10nz*/)) xpc10nz <= 10'sd303/*303:xpc10nz*/; if ((xpc10nz==10'sd303/*303:xpc10nz*/)) xpc10nz <= 10'sd304/*304:xpc10nz*/; if ((xpc10nz==10'sd306/*306:xpc10nz*/)) xpc10nz <= 10'sd307/*307:xpc10nz*/; if ((xpc10nz==10'sd307/*307:xpc10nz*/)) xpc10nz <= 10'sd308/*308:xpc10nz*/; if ((xpc10nz==10'sd312/*312:xpc10nz*/)) xpc10nz <= 10'sd313/*313:xpc10nz*/; if ((xpc10nz==10'sd314/*314:xpc10nz*/)) xpc10nz <= 10'sd315/*315:xpc10nz*/; if ((xpc10nz==10'sd315/*315:xpc10nz*/)) xpc10nz <= 10'sd316/*316:xpc10nz*/; if ((xpc10nz==10'sd316/*316:xpc10nz*/)) xpc10nz <= 10'sd317/*317:xpc10nz*/; if ((xpc10nz==10'sd317/*317:xpc10nz*/)) xpc10nz <= 10'sd318/*318:xpc10nz*/; if ((xpc10nz==10'sd318/*318:xpc10nz*/)) xpc10nz <= 10'sd319/*319:xpc10nz*/; if ((xpc10nz==10'sd319/*319:xpc10nz*/)) xpc10nz <= 10'sd320/*320:xpc10nz*/; if ((xpc10nz==10'sd321/*321:xpc10nz*/)) xpc10nz <= 10'sd322/*322:xpc10nz*/; if ((xpc10nz==10'sd323/*323:xpc10nz*/)) xpc10nz <= 10'sd324/*324:xpc10nz*/; if ((xpc10nz==10'sd324/*324:xpc10nz*/)) xpc10nz <= 10'sd325/*325:xpc10nz*/; if ((xpc10nz==10'sd325/*325:xpc10nz*/)) xpc10nz <= 10'sd326/*326:xpc10nz*/; if ((xpc10nz==10'sd326/*326:xpc10nz*/)) xpc10nz <= 10'sd327/*327:xpc10nz*/; if ((xpc10nz==10'sd327/*327:xpc10nz*/)) xpc10nz <= 10'sd328/*328:xpc10nz*/; if ((xpc10nz==10'sd328/*328:xpc10nz*/)) xpc10nz <= 10'sd329/*329:xpc10nz*/; if ((xpc10nz==10'sd330/*330:xpc10nz*/)) xpc10nz <= 10'sd331/*331:xpc10nz*/; if ((xpc10nz==10'sd332/*332:xpc10nz*/)) xpc10nz <= 10'sd333/*333:xpc10nz*/; if ((xpc10nz==10'sd333/*333:xpc10nz*/)) xpc10nz <= 10'sd334/*334:xpc10nz*/; if ((xpc10nz==10'sd334/*334:xpc10nz*/)) xpc10nz <= 10'sd335/*335:xpc10nz*/; if ((xpc10nz==10'sd335/*335:xpc10nz*/)) xpc10nz <= 10'sd336/*336:xpc10nz*/; if ((xpc10nz==10'sd336/*336:xpc10nz*/)) xpc10nz <= 10'sd337/*337:xpc10nz*/; if ((xpc10nz==10'sd337/*337:xpc10nz*/)) xpc10nz <= 10'sd338/*338:xpc10nz*/; if ((xpc10nz==10'sd339/*339:xpc10nz*/)) xpc10nz <= 10'sd340/*340:xpc10nz*/; if ((xpc10nz==10'sd341/*341:xpc10nz*/)) xpc10nz <= 10'sd342/*342:xpc10nz*/; if ((xpc10nz==10'sd342/*342:xpc10nz*/)) xpc10nz <= 10'sd343/*343:xpc10nz*/; if ((xpc10nz==10'sd343/*343:xpc10nz*/)) xpc10nz <= 10'sd344/*344:xpc10nz*/; if ((xpc10nz==10'sd344/*344:xpc10nz*/)) xpc10nz <= 10'sd345/*345:xpc10nz*/; if ((xpc10nz==10'sd345/*345:xpc10nz*/)) xpc10nz <= 10'sd346/*346:xpc10nz*/; if ((xpc10nz==10'sd346/*346:xpc10nz*/)) xpc10nz <= 10'sd347/*347:xpc10nz*/; if ((xpc10nz==10'sd348/*348:xpc10nz*/)) xpc10nz <= 10'sd349/*349:xpc10nz*/; if ((xpc10nz==10'sd350/*350:xpc10nz*/)) xpc10nz <= 10'sd351/*351:xpc10nz*/; if ((xpc10nz==10'sd351/*351:xpc10nz*/)) xpc10nz <= 10'sd352/*352:xpc10nz*/; if ((xpc10nz==10'sd352/*352:xpc10nz*/)) xpc10nz <= 10'sd353/*353:xpc10nz*/; if ((xpc10nz==10'sd353/*353:xpc10nz*/)) xpc10nz <= 10'sd354/*354:xpc10nz*/; if ((xpc10nz==10'sd354/*354:xpc10nz*/)) xpc10nz <= 10'sd355/*355:xpc10nz*/; if ((xpc10nz==10'sd355/*355:xpc10nz*/)) xpc10nz <= 10'sd356/*356:xpc10nz*/; if ((xpc10nz==10'sd357/*357:xpc10nz*/)) xpc10nz <= 10'sd358/*358:xpc10nz*/; if ((xpc10nz==10'sd359/*359:xpc10nz*/)) xpc10nz <= 10'sd360/*360:xpc10nz*/; if ((xpc10nz==10'sd360/*360:xpc10nz*/)) xpc10nz <= 10'sd361/*361:xpc10nz*/; if ((xpc10nz==10'sd361/*361:xpc10nz*/)) xpc10nz <= 10'sd362/*362:xpc10nz*/; if ((xpc10nz==10'sd362/*362:xpc10nz*/)) xpc10nz <= 10'sd363/*363:xpc10nz*/; if ((xpc10nz==10'sd363/*363:xpc10nz*/)) xpc10nz <= 10'sd364/*364:xpc10nz*/; if ((xpc10nz==10'sd364/*364:xpc10nz*/)) xpc10nz <= 10'sd365/*365:xpc10nz*/; if ((xpc10nz==10'sd366/*366:xpc10nz*/)) xpc10nz <= 10'sd367/*367:xpc10nz*/; if ((xpc10nz==10'sd368/*368:xpc10nz*/)) xpc10nz <= 10'sd369/*369:xpc10nz*/; if ((xpc10nz==10'sd369/*369:xpc10nz*/)) xpc10nz <= 10'sd370/*370:xpc10nz*/; if ((xpc10nz==10'sd370/*370:xpc10nz*/)) xpc10nz <= 10'sd371/*371:xpc10nz*/; if ((xpc10nz==10'sd371/*371:xpc10nz*/)) xpc10nz <= 10'sd372/*372:xpc10nz*/; if ((xpc10nz==10'sd372/*372:xpc10nz*/)) xpc10nz <= 10'sd373/*373:xpc10nz*/; if ((xpc10nz==10'sd373/*373:xpc10nz*/)) xpc10nz <= 10'sd374/*374:xpc10nz*/; if ((xpc10nz==10'sd375/*375:xpc10nz*/)) xpc10nz <= 10'sd376/*376:xpc10nz*/; if ((xpc10nz==10'sd377/*377:xpc10nz*/)) xpc10nz <= 10'sd378/*378:xpc10nz*/; if ((xpc10nz==10'sd378/*378:xpc10nz*/)) xpc10nz <= 10'sd379/*379:xpc10nz*/; if ((xpc10nz==10'sd379/*379:xpc10nz*/)) xpc10nz <= 10'sd380/*380:xpc10nz*/; if ((xpc10nz==10'sd380/*380:xpc10nz*/)) xpc10nz <= 10'sd381/*381:xpc10nz*/; if ((xpc10nz==10'sd381/*381:xpc10nz*/)) xpc10nz <= 10'sd382/*382:xpc10nz*/; if ((xpc10nz==10'sd382/*382:xpc10nz*/)) xpc10nz <= 10'sd383/*383:xpc10nz*/; if ((xpc10nz==10'sd386/*386:xpc10nz*/)) xpc10nz <= 10'sd387/*387:xpc10nz*/; if ((xpc10nz==10'sd387/*387:xpc10nz*/)) xpc10nz <= 10'sd388/*388:xpc10nz*/; if ((xpc10nz==10'sd388/*388:xpc10nz*/)) xpc10nz <= 10'sd389/*389:xpc10nz*/; if ((xpc10nz==10'sd390/*390:xpc10nz*/)) xpc10nz <= 10'sd391/*391:xpc10nz*/; if ((xpc10nz==10'sd391/*391:xpc10nz*/)) xpc10nz <= 10'sd392/*392:xpc10nz*/; if ((xpc10nz==10'sd392/*392:xpc10nz*/)) xpc10nz <= 10'sd393/*393:xpc10nz*/; if ((xpc10nz==10'sd394/*394:xpc10nz*/)) xpc10nz <= 10'sd395/*395:xpc10nz*/; if ((xpc10nz==10'sd395/*395:xpc10nz*/)) xpc10nz <= 10'sd396/*396:xpc10nz*/; if ((xpc10nz==10'sd396/*396:xpc10nz*/)) xpc10nz <= 10'sd397/*397:xpc10nz*/; if ((xpc10nz==10'sd398/*398:xpc10nz*/)) xpc10nz <= 10'sd399/*399:xpc10nz*/; if ((xpc10nz==10'sd399/*399:xpc10nz*/)) xpc10nz <= 10'sd400/*400:xpc10nz*/; if ((xpc10nz==10'sd400/*400:xpc10nz*/)) xpc10nz <= 10'sd401/*401:xpc10nz*/; if ((xpc10nz==10'sd402/*402:xpc10nz*/)) xpc10nz <= 10'sd403/*403:xpc10nz*/; if ((xpc10nz==10'sd403/*403:xpc10nz*/)) xpc10nz <= 10'sd404/*404:xpc10nz*/; if ((xpc10nz==10'sd404/*404:xpc10nz*/)) xpc10nz <= 10'sd405/*405:xpc10nz*/; if ((xpc10nz==10'sd406/*406:xpc10nz*/)) xpc10nz <= 10'sd407/*407:xpc10nz*/; if ((xpc10nz==10'sd407/*407:xpc10nz*/)) xpc10nz <= 10'sd408/*408:xpc10nz*/; if ((xpc10nz==10'sd408/*408:xpc10nz*/)) xpc10nz <= 10'sd409/*409:xpc10nz*/; if ((xpc10nz==10'sd410/*410:xpc10nz*/)) xpc10nz <= 10'sd411/*411:xpc10nz*/; if ((xpc10nz==10'sd411/*411:xpc10nz*/)) xpc10nz <= 10'sd412/*412:xpc10nz*/; if ((xpc10nz==10'sd412/*412:xpc10nz*/)) xpc10nz <= 10'sd413/*413:xpc10nz*/; if ((xpc10nz==10'sd414/*414:xpc10nz*/)) xpc10nz <= 10'sd415/*415:xpc10nz*/; if ((xpc10nz==10'sd415/*415:xpc10nz*/)) xpc10nz <= 10'sd416/*416:xpc10nz*/; if ((xpc10nz==10'sd416/*416:xpc10nz*/)) xpc10nz <= 10'sd417/*417:xpc10nz*/; if ((xpc10nz==10'sd420/*420:xpc10nz*/)) xpc10nz <= 10'sd421/*421:xpc10nz*/; if ((xpc10nz==10'sd421/*421:xpc10nz*/)) xpc10nz <= 10'sd422/*422:xpc10nz*/; if ((xpc10nz==10'sd422/*422:xpc10nz*/)) xpc10nz <= 10'sd423/*423:xpc10nz*/; if ((xpc10nz==10'sd424/*424:xpc10nz*/)) xpc10nz <= 10'sd425/*425:xpc10nz*/; if ((xpc10nz==10'sd425/*425:xpc10nz*/)) xpc10nz <= 10'sd426/*426:xpc10nz*/; if ((xpc10nz==10'sd426/*426:xpc10nz*/)) xpc10nz <= 10'sd427/*427:xpc10nz*/; if ((xpc10nz==10'sd428/*428:xpc10nz*/)) xpc10nz <= 10'sd429/*429:xpc10nz*/; if ((xpc10nz==10'sd429/*429:xpc10nz*/)) xpc10nz <= 10'sd430/*430:xpc10nz*/; if ((xpc10nz==10'sd430/*430:xpc10nz*/)) xpc10nz <= 10'sd431/*431:xpc10nz*/; if ((xpc10nz==10'sd432/*432:xpc10nz*/)) xpc10nz <= 10'sd433/*433:xpc10nz*/; if ((xpc10nz==10'sd433/*433:xpc10nz*/)) xpc10nz <= 10'sd434/*434:xpc10nz*/; if ((xpc10nz==10'sd434/*434:xpc10nz*/)) xpc10nz <= 10'sd435/*435:xpc10nz*/; if ((xpc10nz==10'sd436/*436:xpc10nz*/)) xpc10nz <= 10'sd437/*437:xpc10nz*/; if ((xpc10nz==10'sd437/*437:xpc10nz*/)) xpc10nz <= 10'sd438/*438:xpc10nz*/; if ((xpc10nz==10'sd438/*438:xpc10nz*/)) xpc10nz <= 10'sd439/*439:xpc10nz*/; if ((xpc10nz==10'sd440/*440:xpc10nz*/)) xpc10nz <= 10'sd441/*441:xpc10nz*/; if ((xpc10nz==10'sd441/*441:xpc10nz*/)) xpc10nz <= 10'sd442/*442:xpc10nz*/; if ((xpc10nz==10'sd442/*442:xpc10nz*/)) xpc10nz <= 10'sd443/*443:xpc10nz*/; if ((xpc10nz==10'sd444/*444:xpc10nz*/)) xpc10nz <= 10'sd445/*445:xpc10nz*/; if ((xpc10nz==10'sd445/*445:xpc10nz*/)) xpc10nz <= 10'sd446/*446:xpc10nz*/; if ((xpc10nz==10'sd446/*446:xpc10nz*/)) xpc10nz <= 10'sd447/*447:xpc10nz*/; if ((xpc10nz==10'sd448/*448:xpc10nz*/)) xpc10nz <= 10'sd449/*449:xpc10nz*/; if ((xpc10nz==10'sd449/*449:xpc10nz*/)) xpc10nz <= 10'sd450/*450:xpc10nz*/; if ((xpc10nz==10'sd450/*450:xpc10nz*/)) xpc10nz <= 10'sd451/*451:xpc10nz*/; if ((xpc10nz==10'sd454/*454:xpc10nz*/)) xpc10nz <= 10'sd455/*455:xpc10nz*/; if ((xpc10nz==10'sd455/*455:xpc10nz*/)) xpc10nz <= 10'sd456/*456:xpc10nz*/; if ((xpc10nz==10'sd456/*456:xpc10nz*/)) xpc10nz <= 10'sd457/*457:xpc10nz*/; if ((xpc10nz==10'sd458/*458:xpc10nz*/)) xpc10nz <= 10'sd459/*459:xpc10nz*/; if ((xpc10nz==10'sd459/*459:xpc10nz*/)) xpc10nz <= 10'sd460/*460:xpc10nz*/; if ((xpc10nz==10'sd460/*460:xpc10nz*/)) xpc10nz <= 10'sd461/*461:xpc10nz*/; if ((xpc10nz==10'sd462/*462:xpc10nz*/)) xpc10nz <= 10'sd463/*463:xpc10nz*/; if ((xpc10nz==10'sd463/*463:xpc10nz*/)) xpc10nz <= 10'sd464/*464:xpc10nz*/; if ((xpc10nz==10'sd464/*464:xpc10nz*/)) xpc10nz <= 10'sd465/*465:xpc10nz*/; if ((xpc10nz==10'sd466/*466:xpc10nz*/)) xpc10nz <= 10'sd467/*467:xpc10nz*/; if ((xpc10nz==10'sd467/*467:xpc10nz*/)) xpc10nz <= 10'sd468/*468:xpc10nz*/; if ((xpc10nz==10'sd468/*468:xpc10nz*/)) xpc10nz <= 10'sd469/*469:xpc10nz*/; if ((xpc10nz==10'sd470/*470:xpc10nz*/)) xpc10nz <= 10'sd471/*471:xpc10nz*/; if ((xpc10nz==10'sd471/*471:xpc10nz*/)) xpc10nz <= 10'sd472/*472:xpc10nz*/; if ((xpc10nz==10'sd472/*472:xpc10nz*/)) xpc10nz <= 10'sd473/*473:xpc10nz*/; if ((xpc10nz==10'sd474/*474:xpc10nz*/)) xpc10nz <= 10'sd475/*475:xpc10nz*/; if ((xpc10nz==10'sd475/*475:xpc10nz*/)) xpc10nz <= 10'sd476/*476:xpc10nz*/; if ((xpc10nz==10'sd476/*476:xpc10nz*/)) xpc10nz <= 10'sd477/*477:xpc10nz*/; if ((xpc10nz==10'sd478/*478:xpc10nz*/)) xpc10nz <= 10'sd479/*479:xpc10nz*/; if ((xpc10nz==10'sd479/*479:xpc10nz*/)) xpc10nz <= 10'sd480/*480:xpc10nz*/; if ((xpc10nz==10'sd480/*480:xpc10nz*/)) xpc10nz <= 10'sd481/*481:xpc10nz*/; if ((xpc10nz==10'sd482/*482:xpc10nz*/)) xpc10nz <= 10'sd483/*483:xpc10nz*/; if ((xpc10nz==10'sd483/*483:xpc10nz*/)) xpc10nz <= 10'sd484/*484:xpc10nz*/; if ((xpc10nz==10'sd484/*484:xpc10nz*/)) xpc10nz <= 10'sd485/*485:xpc10nz*/; if ((xpc10nz==10'sd488/*488:xpc10nz*/)) xpc10nz <= 10'sd489/*489:xpc10nz*/; if ((xpc10nz==10'sd489/*489:xpc10nz*/)) xpc10nz <= 10'sd490/*490:xpc10nz*/; if ((xpc10nz==10'sd490/*490:xpc10nz*/)) xpc10nz <= 10'sd491/*491:xpc10nz*/; if ((xpc10nz==10'sd492/*492:xpc10nz*/)) xpc10nz <= 10'sd493/*493:xpc10nz*/; if ((xpc10nz==10'sd493/*493:xpc10nz*/)) xpc10nz <= 10'sd494/*494:xpc10nz*/; if ((xpc10nz==10'sd494/*494:xpc10nz*/)) xpc10nz <= 10'sd495/*495:xpc10nz*/; if ((xpc10nz==10'sd496/*496:xpc10nz*/)) xpc10nz <= 10'sd497/*497:xpc10nz*/; if ((xpc10nz==10'sd497/*497:xpc10nz*/)) xpc10nz <= 10'sd498/*498:xpc10nz*/; if ((xpc10nz==10'sd498/*498:xpc10nz*/)) xpc10nz <= 10'sd499/*499:xpc10nz*/; if ((xpc10nz==10'sd500/*500:xpc10nz*/)) xpc10nz <= 10'sd501/*501:xpc10nz*/; if ((xpc10nz==10'sd501/*501:xpc10nz*/)) xpc10nz <= 10'sd502/*502:xpc10nz*/; if ((xpc10nz==10'sd502/*502:xpc10nz*/)) xpc10nz <= 10'sd503/*503:xpc10nz*/; if ((xpc10nz==10'sd504/*504:xpc10nz*/)) xpc10nz <= 10'sd505/*505:xpc10nz*/; if ((xpc10nz==10'sd505/*505:xpc10nz*/)) xpc10nz <= 10'sd506/*506:xpc10nz*/; if ((xpc10nz==10'sd506/*506:xpc10nz*/)) xpc10nz <= 10'sd507/*507:xpc10nz*/; if ((xpc10nz==10'sd508/*508:xpc10nz*/)) xpc10nz <= 10'sd509/*509:xpc10nz*/; if ((xpc10nz==10'sd509/*509:xpc10nz*/)) xpc10nz <= 10'sd510/*510:xpc10nz*/; if ((xpc10nz==10'sd510/*510:xpc10nz*/)) xpc10nz <= 10'sd511/*511:xpc10nz*/; if ((xpc10nz==10'sd512/*512:xpc10nz*/)) xpc10nz <= 10'sd513/*513:xpc10nz*/; if ((xpc10nz==10'sd513/*513:xpc10nz*/)) xpc10nz <= 10'sd514/*514:xpc10nz*/; if ((xpc10nz==10'sd514/*514:xpc10nz*/)) xpc10nz <= 10'sd515/*515:xpc10nz*/; if ((xpc10nz==10'sd516/*516:xpc10nz*/)) xpc10nz <= 10'sd517/*517:xpc10nz*/; if ((xpc10nz==10'sd517/*517:xpc10nz*/)) xpc10nz <= 10'sd518/*518:xpc10nz*/; if ((xpc10nz==10'sd518/*518:xpc10nz*/)) xpc10nz <= 10'sd519/*519:xpc10nz*/; if ((xpc10nz==10'sd522/*522:xpc10nz*/)) xpc10nz <= 10'sd523/*523:xpc10nz*/; if ((xpc10nz==10'sd523/*523:xpc10nz*/)) xpc10nz <= 10'sd524/*524:xpc10nz*/; if ((xpc10nz==10'sd524/*524:xpc10nz*/)) xpc10nz <= 10'sd525/*525:xpc10nz*/; if ((xpc10nz==10'sd526/*526:xpc10nz*/)) xpc10nz <= 10'sd527/*527:xpc10nz*/; if ((xpc10nz==10'sd527/*527:xpc10nz*/)) xpc10nz <= 10'sd528/*528:xpc10nz*/; if ((xpc10nz==10'sd528/*528:xpc10nz*/)) xpc10nz <= 10'sd529/*529:xpc10nz*/; if ((xpc10nz==10'sd530/*530:xpc10nz*/)) xpc10nz <= 10'sd531/*531:xpc10nz*/; if ((xpc10nz==10'sd531/*531:xpc10nz*/)) xpc10nz <= 10'sd532/*532:xpc10nz*/; if ((xpc10nz==10'sd532/*532:xpc10nz*/)) xpc10nz <= 10'sd533/*533:xpc10nz*/; if ((xpc10nz==10'sd534/*534:xpc10nz*/)) xpc10nz <= 10'sd535/*535:xpc10nz*/; if ((xpc10nz==10'sd535/*535:xpc10nz*/)) xpc10nz <= 10'sd536/*536:xpc10nz*/; if ((xpc10nz==10'sd536/*536:xpc10nz*/)) xpc10nz <= 10'sd537/*537:xpc10nz*/; if ((xpc10nz==10'sd538/*538:xpc10nz*/)) xpc10nz <= 10'sd539/*539:xpc10nz*/; if ((xpc10nz==10'sd539/*539:xpc10nz*/)) xpc10nz <= 10'sd540/*540:xpc10nz*/; if ((xpc10nz==10'sd540/*540:xpc10nz*/)) xpc10nz <= 10'sd541/*541:xpc10nz*/; if ((xpc10nz==10'sd542/*542:xpc10nz*/)) xpc10nz <= 10'sd543/*543:xpc10nz*/; if ((xpc10nz==10'sd543/*543:xpc10nz*/)) xpc10nz <= 10'sd544/*544:xpc10nz*/; if ((xpc10nz==10'sd544/*544:xpc10nz*/)) xpc10nz <= 10'sd545/*545:xpc10nz*/; if ((xpc10nz==10'sd546/*546:xpc10nz*/)) xpc10nz <= 10'sd547/*547:xpc10nz*/; if ((xpc10nz==10'sd547/*547:xpc10nz*/)) xpc10nz <= 10'sd548/*548:xpc10nz*/; if ((xpc10nz==10'sd548/*548:xpc10nz*/)) xpc10nz <= 10'sd549/*549:xpc10nz*/; if ((xpc10nz==10'sd550/*550:xpc10nz*/)) xpc10nz <= 10'sd551/*551:xpc10nz*/; if ((xpc10nz==10'sd551/*551:xpc10nz*/)) xpc10nz <= 10'sd552/*552:xpc10nz*/; if ((xpc10nz==10'sd552/*552:xpc10nz*/)) xpc10nz <= 10'sd553/*553:xpc10nz*/; if ((xpc10nz==10'sd556/*556:xpc10nz*/)) xpc10nz <= 10'sd557/*557:xpc10nz*/; if ((xpc10nz==10'sd557/*557:xpc10nz*/)) xpc10nz <= 10'sd558/*558:xpc10nz*/; if ((xpc10nz==10'sd558/*558:xpc10nz*/)) xpc10nz <= 10'sd559/*559:xpc10nz*/; if ((xpc10nz==10'sd560/*560:xpc10nz*/)) xpc10nz <= 10'sd561/*561:xpc10nz*/; if ((xpc10nz==10'sd561/*561:xpc10nz*/)) xpc10nz <= 10'sd562/*562:xpc10nz*/; if ((xpc10nz==10'sd562/*562:xpc10nz*/)) xpc10nz <= 10'sd563/*563:xpc10nz*/; if ((xpc10nz==10'sd564/*564:xpc10nz*/)) xpc10nz <= 10'sd565/*565:xpc10nz*/; if ((xpc10nz==10'sd565/*565:xpc10nz*/)) xpc10nz <= 10'sd566/*566:xpc10nz*/; if ((xpc10nz==10'sd566/*566:xpc10nz*/)) xpc10nz <= 10'sd567/*567:xpc10nz*/; if ((xpc10nz==10'sd568/*568:xpc10nz*/)) xpc10nz <= 10'sd569/*569:xpc10nz*/; if ((xpc10nz==10'sd569/*569:xpc10nz*/)) xpc10nz <= 10'sd570/*570:xpc10nz*/; if ((xpc10nz==10'sd570/*570:xpc10nz*/)) xpc10nz <= 10'sd571/*571:xpc10nz*/; if ((xpc10nz==10'sd572/*572:xpc10nz*/)) xpc10nz <= 10'sd573/*573:xpc10nz*/; if ((xpc10nz==10'sd573/*573:xpc10nz*/)) xpc10nz <= 10'sd574/*574:xpc10nz*/; if ((xpc10nz==10'sd574/*574:xpc10nz*/)) xpc10nz <= 10'sd575/*575:xpc10nz*/; if ((xpc10nz==10'sd576/*576:xpc10nz*/)) xpc10nz <= 10'sd577/*577:xpc10nz*/; if ((xpc10nz==10'sd577/*577:xpc10nz*/)) xpc10nz <= 10'sd578/*578:xpc10nz*/; if ((xpc10nz==10'sd578/*578:xpc10nz*/)) xpc10nz <= 10'sd579/*579:xpc10nz*/; if ((xpc10nz==10'sd580/*580:xpc10nz*/)) xpc10nz <= 10'sd581/*581:xpc10nz*/; if ((xpc10nz==10'sd581/*581:xpc10nz*/)) xpc10nz <= 10'sd582/*582:xpc10nz*/; if ((xpc10nz==10'sd582/*582:xpc10nz*/)) xpc10nz <= 10'sd583/*583:xpc10nz*/; if ((xpc10nz==10'sd584/*584:xpc10nz*/)) xpc10nz <= 10'sd585/*585:xpc10nz*/; if ((xpc10nz==10'sd585/*585:xpc10nz*/)) xpc10nz <= 10'sd586/*586:xpc10nz*/; if ((xpc10nz==10'sd586/*586:xpc10nz*/)) xpc10nz <= 10'sd587/*587:xpc10nz*/; if ((xpc10nz==10'sd590/*590:xpc10nz*/)) xpc10nz <= 10'sd591/*591:xpc10nz*/; if ((xpc10nz==10'sd591/*591:xpc10nz*/)) xpc10nz <= 10'sd592/*592:xpc10nz*/; if ((xpc10nz==10'sd592/*592:xpc10nz*/)) xpc10nz <= 10'sd593/*593:xpc10nz*/; if ((xpc10nz==10'sd594/*594:xpc10nz*/)) xpc10nz <= 10'sd595/*595:xpc10nz*/; if ((xpc10nz==10'sd595/*595:xpc10nz*/)) xpc10nz <= 10'sd596/*596:xpc10nz*/; if ((xpc10nz==10'sd596/*596:xpc10nz*/)) xpc10nz <= 10'sd597/*597:xpc10nz*/; if ((xpc10nz==10'sd598/*598:xpc10nz*/)) xpc10nz <= 10'sd599/*599:xpc10nz*/; if ((xpc10nz==10'sd599/*599:xpc10nz*/)) xpc10nz <= 10'sd600/*600:xpc10nz*/; if ((xpc10nz==10'sd600/*600:xpc10nz*/)) xpc10nz <= 10'sd601/*601:xpc10nz*/; if ((xpc10nz==10'sd602/*602:xpc10nz*/)) xpc10nz <= 10'sd603/*603:xpc10nz*/; if ((xpc10nz==10'sd603/*603:xpc10nz*/)) xpc10nz <= 10'sd604/*604:xpc10nz*/; if ((xpc10nz==10'sd604/*604:xpc10nz*/)) xpc10nz <= 10'sd605/*605:xpc10nz*/; if ((xpc10nz==10'sd606/*606:xpc10nz*/)) xpc10nz <= 10'sd607/*607:xpc10nz*/; if ((xpc10nz==10'sd607/*607:xpc10nz*/)) xpc10nz <= 10'sd608/*608:xpc10nz*/; if ((xpc10nz==10'sd608/*608:xpc10nz*/)) xpc10nz <= 10'sd609/*609:xpc10nz*/; if ((xpc10nz==10'sd610/*610:xpc10nz*/)) xpc10nz <= 10'sd611/*611:xpc10nz*/; if ((xpc10nz==10'sd611/*611:xpc10nz*/)) xpc10nz <= 10'sd612/*612:xpc10nz*/; if ((xpc10nz==10'sd612/*612:xpc10nz*/)) xpc10nz <= 10'sd613/*613:xpc10nz*/; if ((xpc10nz==10'sd614/*614:xpc10nz*/)) xpc10nz <= 10'sd615/*615:xpc10nz*/; if ((xpc10nz==10'sd615/*615:xpc10nz*/)) xpc10nz <= 10'sd616/*616:xpc10nz*/; if ((xpc10nz==10'sd616/*616:xpc10nz*/)) xpc10nz <= 10'sd617/*617:xpc10nz*/; if ((xpc10nz==10'sd618/*618:xpc10nz*/)) xpc10nz <= 10'sd619/*619:xpc10nz*/; if ((xpc10nz==10'sd619/*619:xpc10nz*/)) xpc10nz <= 10'sd620/*620:xpc10nz*/; if ((xpc10nz==10'sd620/*620:xpc10nz*/)) xpc10nz <= 10'sd621/*621:xpc10nz*/; if ((xpc10nz==10'sd624/*624:xpc10nz*/)) xpc10nz <= 10'sd625/*625:xpc10nz*/; if ((xpc10nz==10'sd625/*625:xpc10nz*/)) xpc10nz <= 10'sd626/*626:xpc10nz*/; if ((xpc10nz==10'sd626/*626:xpc10nz*/)) xpc10nz <= 10'sd627/*627:xpc10nz*/; if ((xpc10nz==10'sd628/*628:xpc10nz*/)) xpc10nz <= 10'sd629/*629:xpc10nz*/; if ((xpc10nz==10'sd629/*629:xpc10nz*/)) xpc10nz <= 10'sd630/*630:xpc10nz*/; if ((xpc10nz==10'sd630/*630:xpc10nz*/)) xpc10nz <= 10'sd631/*631:xpc10nz*/; if ((xpc10nz==10'sd632/*632:xpc10nz*/)) xpc10nz <= 10'sd633/*633:xpc10nz*/; if ((xpc10nz==10'sd633/*633:xpc10nz*/)) xpc10nz <= 10'sd634/*634:xpc10nz*/; if ((xpc10nz==10'sd634/*634:xpc10nz*/)) xpc10nz <= 10'sd635/*635:xpc10nz*/; if ((xpc10nz==10'sd636/*636:xpc10nz*/)) xpc10nz <= 10'sd637/*637:xpc10nz*/; if ((xpc10nz==10'sd637/*637:xpc10nz*/)) xpc10nz <= 10'sd638/*638:xpc10nz*/; if ((xpc10nz==10'sd638/*638:xpc10nz*/)) xpc10nz <= 10'sd639/*639:xpc10nz*/; if ((xpc10nz==10'sd640/*640:xpc10nz*/)) xpc10nz <= 10'sd641/*641:xpc10nz*/; if ((xpc10nz==10'sd641/*641:xpc10nz*/)) xpc10nz <= 10'sd642/*642:xpc10nz*/; if ((xpc10nz==10'sd642/*642:xpc10nz*/)) xpc10nz <= 10'sd643/*643:xpc10nz*/; if ((xpc10nz==10'sd644/*644:xpc10nz*/)) xpc10nz <= 10'sd645/*645:xpc10nz*/; if ((xpc10nz==10'sd645/*645:xpc10nz*/)) xpc10nz <= 10'sd646/*646:xpc10nz*/; if ((xpc10nz==10'sd646/*646:xpc10nz*/)) xpc10nz <= 10'sd647/*647:xpc10nz*/; if ((xpc10nz==10'sd648/*648:xpc10nz*/)) xpc10nz <= 10'sd649/*649:xpc10nz*/; if ((xpc10nz==10'sd649/*649:xpc10nz*/)) xpc10nz <= 10'sd650/*650:xpc10nz*/; if ((xpc10nz==10'sd650/*650:xpc10nz*/)) xpc10nz <= 10'sd651/*651:xpc10nz*/; if ((xpc10nz==10'sd652/*652:xpc10nz*/)) xpc10nz <= 10'sd653/*653:xpc10nz*/; if ((xpc10nz==10'sd653/*653:xpc10nz*/)) xpc10nz <= 10'sd654/*654:xpc10nz*/; if ((xpc10nz==10'sd654/*654:xpc10nz*/)) xpc10nz <= 10'sd655/*655:xpc10nz*/; if ((xpc10nz==10'sd660/*660:xpc10nz*/)) xpc10nz <= 10'sd661/*661:xpc10nz*/; if ((xpc10nz==10'sd663/*663:xpc10nz*/)) xpc10nz <= 10'sd664/*664:xpc10nz*/; if ((xpc10nz==10'sd666/*666:xpc10nz*/)) xpc10nz <= 10'sd667/*667:xpc10nz*/; if ((xpc10nz==10'sd669/*669:xpc10nz*/)) xpc10nz <= 10'sd670/*670:xpc10nz*/; if ((xpc10nz==10'sd672/*672:xpc10nz*/)) xpc10nz <= 10'sd673/*673:xpc10nz*/; if ((xpc10nz==10'sd675/*675:xpc10nz*/)) xpc10nz <= 10'sd676/*676:xpc10nz*/; if ((xpc10nz==10'sd678/*678:xpc10nz*/)) xpc10nz <= 10'sd679/*679:xpc10nz*/; if ((xpc10nz==10'sd681/*681:xpc10nz*/)) xpc10nz <= 10'sd682/*682:xpc10nz*/; if ((xpc10nz==10'sd689/*689:xpc10nz*/)) xpc10nz <= 10'sd984/*984:xpc10nz*/; if ((xpc10nz==10'sd704/*704:xpc10nz*/)) xpc10nz <= 10'sd719/*719:xpc10nz*/; if ((xpc10nz==10'sd705/*705:xpc10nz*/)) xpc10nz <= 10'sd706/*706:xpc10nz*/; if ((xpc10nz==10'sd706/*706:xpc10nz*/)) xpc10nz <= 10'sd707/*707:xpc10nz*/; if ((xpc10nz==10'sd707/*707:xpc10nz*/)) xpc10nz <= 10'sd708/*708:xpc10nz*/; if ((xpc10nz==10'sd708/*708:xpc10nz*/)) xpc10nz <= 10'sd709/*709:xpc10nz*/; if ((xpc10nz==10'sd709/*709:xpc10nz*/)) xpc10nz <= 10'sd710/*710:xpc10nz*/; if ((xpc10nz==10'sd710/*710:xpc10nz*/)) xpc10nz <= 10'sd711/*711:xpc10nz*/; if ((xpc10nz==10'sd711/*711:xpc10nz*/)) xpc10nz <= 10'sd712/*712:xpc10nz*/; if ((xpc10nz==10'sd712/*712:xpc10nz*/)) xpc10nz <= 10'sd713/*713:xpc10nz*/; if ((xpc10nz==10'sd713/*713:xpc10nz*/)) xpc10nz <= 10'sd714/*714:xpc10nz*/; if ((xpc10nz==10'sd714/*714:xpc10nz*/)) xpc10nz <= 10'sd715/*715:xpc10nz*/; if ((xpc10nz==10'sd715/*715:xpc10nz*/)) xpc10nz <= 10'sd716/*716:xpc10nz*/; if ((xpc10nz==10'sd716/*716:xpc10nz*/)) xpc10nz <= 10'sd717/*717:xpc10nz*/; if ((xpc10nz==10'sd717/*717:xpc10nz*/)) xpc10nz <= 10'sd718/*718:xpc10nz*/; if ((xpc10nz==10'sd718/*718:xpc10nz*/)) xpc10nz <= 10'sd864/*864:xpc10nz*/; if ((xpc10nz==10'sd721/*721:xpc10nz*/)) xpc10nz <= 10'sd722/*722:xpc10nz*/; if ((xpc10nz==10'sd722/*722:xpc10nz*/)) xpc10nz <= 10'sd725/*725:xpc10nz*/; if ((xpc10nz==10'sd723/*723:xpc10nz*/)) xpc10nz <= 10'sd724/*724:xpc10nz*/; if ((xpc10nz==10'sd750/*750:xpc10nz*/)) xpc10nz <= 10'sd759/*759:xpc10nz*/; if ((xpc10nz==10'sd751/*751:xpc10nz*/)) xpc10nz <= 10'sd752/*752:xpc10nz*/; if ((xpc10nz==10'sd752/*752:xpc10nz*/)) xpc10nz <= 10'sd753/*753:xpc10nz*/; if ((xpc10nz==10'sd753/*753:xpc10nz*/)) xpc10nz <= 10'sd754/*754:xpc10nz*/; if ((xpc10nz==10'sd754/*754:xpc10nz*/)) xpc10nz <= 10'sd755/*755:xpc10nz*/; if ((xpc10nz==10'sd755/*755:xpc10nz*/)) xpc10nz <= 10'sd756/*756:xpc10nz*/; if ((xpc10nz==10'sd756/*756:xpc10nz*/)) xpc10nz <= 10'sd757/*757:xpc10nz*/; if ((xpc10nz==10'sd757/*757:xpc10nz*/)) xpc10nz <= 10'sd758/*758:xpc10nz*/; if ((xpc10nz==10'sd763/*763:xpc10nz*/)) xpc10nz <= 10'sd759/*759:xpc10nz*/; if ((xpc10nz==10'sd764/*764:xpc10nz*/)) xpc10nz <= 10'sd765/*765:xpc10nz*/; if ((xpc10nz==10'sd765/*765:xpc10nz*/)) xpc10nz <= 10'sd766/*766:xpc10nz*/; if ((xpc10nz==10'sd766/*766:xpc10nz*/)) xpc10nz <= 10'sd767/*767:xpc10nz*/; if ((xpc10nz==10'sd767/*767:xpc10nz*/)) xpc10nz <= 10'sd768/*768:xpc10nz*/; if ((xpc10nz==10'sd768/*768:xpc10nz*/)) xpc10nz <= 10'sd769/*769:xpc10nz*/; if ((xpc10nz==10'sd769/*769:xpc10nz*/)) xpc10nz <= 10'sd770/*770:xpc10nz*/; if ((xpc10nz==10'sd770/*770:xpc10nz*/)) xpc10nz <= 10'sd771/*771:xpc10nz*/; if ((xpc10nz==10'sd777/*777:xpc10nz*/)) xpc10nz <= 10'sd778/*778:xpc10nz*/; if ((xpc10nz==10'sd778/*778:xpc10nz*/)) xpc10nz <= 10'sd779/*779:xpc10nz*/; if ((xpc10nz==10'sd779/*779:xpc10nz*/)) xpc10nz <= 10'sd780/*780:xpc10nz*/; if ((xpc10nz==10'sd780/*780:xpc10nz*/)) xpc10nz <= 10'sd781/*781:xpc10nz*/; if ((xpc10nz==10'sd781/*781:xpc10nz*/)) xpc10nz <= 10'sd782/*782:xpc10nz*/; if ((xpc10nz==10'sd782/*782:xpc10nz*/)) xpc10nz <= 10'sd783/*783:xpc10nz*/; if ((xpc10nz==10'sd783/*783:xpc10nz*/)) xpc10nz <= 10'sd784/*784:xpc10nz*/; if ((xpc10nz==10'sd784/*784:xpc10nz*/)) xpc10nz <= 10'sd785/*785:xpc10nz*/; if ((xpc10nz==10'sd785/*785:xpc10nz*/)) xpc10nz <= 10'sd786/*786:xpc10nz*/; if ((xpc10nz==10'sd786/*786:xpc10nz*/)) xpc10nz <= 10'sd787/*787:xpc10nz*/; if ((xpc10nz==10'sd787/*787:xpc10nz*/)) xpc10nz <= 10'sd797/*797:xpc10nz*/; if ((xpc10nz==10'sd788/*788:xpc10nz*/)) xpc10nz <= 10'sd789/*789:xpc10nz*/; if ((xpc10nz==10'sd789/*789:xpc10nz*/)) xpc10nz <= 10'sd790/*790:xpc10nz*/; if ((xpc10nz==10'sd790/*790:xpc10nz*/)) xpc10nz <= 10'sd791/*791:xpc10nz*/; if ((xpc10nz==10'sd791/*791:xpc10nz*/)) xpc10nz <= 10'sd792/*792:xpc10nz*/; if ((xpc10nz==10'sd792/*792:xpc10nz*/)) xpc10nz <= 10'sd793/*793:xpc10nz*/; if ((xpc10nz==10'sd793/*793:xpc10nz*/)) xpc10nz <= 10'sd794/*794:xpc10nz*/; if ((xpc10nz==10'sd794/*794:xpc10nz*/)) xpc10nz <= 10'sd795/*795:xpc10nz*/; if ((xpc10nz==10'sd795/*795:xpc10nz*/)) xpc10nz <= 10'sd796/*796:xpc10nz*/; if ((xpc10nz==10'sd801/*801:xpc10nz*/)) xpc10nz <= 10'sd802/*802:xpc10nz*/; if ((xpc10nz==10'sd802/*802:xpc10nz*/)) xpc10nz <= 10'sd803/*803:xpc10nz*/; if ((xpc10nz==10'sd803/*803:xpc10nz*/)) xpc10nz <= 10'sd804/*804:xpc10nz*/; if ((xpc10nz==10'sd804/*804:xpc10nz*/)) xpc10nz <= 10'sd805/*805:xpc10nz*/; if ((xpc10nz==10'sd805/*805:xpc10nz*/)) xpc10nz <= 10'sd806/*806:xpc10nz*/; if ((xpc10nz==10'sd806/*806:xpc10nz*/)) xpc10nz <= 10'sd807/*807:xpc10nz*/; if ((xpc10nz==10'sd807/*807:xpc10nz*/)) xpc10nz <= 10'sd808/*808:xpc10nz*/; if ((xpc10nz==10'sd808/*808:xpc10nz*/)) xpc10nz <= 10'sd809/*809:xpc10nz*/; if ((xpc10nz==10'sd809/*809:xpc10nz*/)) xpc10nz <= 10'sd810/*810:xpc10nz*/; if ((xpc10nz==10'sd810/*810:xpc10nz*/)) xpc10nz <= 10'sd811/*811:xpc10nz*/; if ((xpc10nz==10'sd811/*811:xpc10nz*/)) xpc10nz <= 10'sd797/*797:xpc10nz*/; if ((xpc10nz==10'sd812/*812:xpc10nz*/)) xpc10nz <= 10'sd813/*813:xpc10nz*/; if ((xpc10nz==10'sd813/*813:xpc10nz*/)) xpc10nz <= 10'sd814/*814:xpc10nz*/; if ((xpc10nz==10'sd814/*814:xpc10nz*/)) xpc10nz <= 10'sd815/*815:xpc10nz*/; if ((xpc10nz==10'sd815/*815:xpc10nz*/)) xpc10nz <= 10'sd816/*816:xpc10nz*/; if ((xpc10nz==10'sd816/*816:xpc10nz*/)) xpc10nz <= 10'sd817/*817:xpc10nz*/; if ((xpc10nz==10'sd817/*817:xpc10nz*/)) xpc10nz <= 10'sd818/*818:xpc10nz*/; if ((xpc10nz==10'sd818/*818:xpc10nz*/)) xpc10nz <= 10'sd819/*819:xpc10nz*/; if ((xpc10nz==10'sd819/*819:xpc10nz*/)) xpc10nz <= 10'sd820/*820:xpc10nz*/; if ((xpc10nz==10'sd826/*826:xpc10nz*/)) xpc10nz <= 10'sd827/*827:xpc10nz*/; if ((xpc10nz==10'sd827/*827:xpc10nz*/)) xpc10nz <= 10'sd828/*828:xpc10nz*/; if ((xpc10nz==10'sd828/*828:xpc10nz*/)) xpc10nz <= 10'sd829/*829:xpc10nz*/; if ((xpc10nz==10'sd829/*829:xpc10nz*/)) xpc10nz <= 10'sd830/*830:xpc10nz*/; if ((xpc10nz==10'sd830/*830:xpc10nz*/)) xpc10nz <= 10'sd831/*831:xpc10nz*/; if ((xpc10nz==10'sd831/*831:xpc10nz*/)) xpc10nz <= 10'sd840/*840:xpc10nz*/; if ((xpc10nz==10'sd832/*832:xpc10nz*/)) xpc10nz <= 10'sd833/*833:xpc10nz*/; if ((xpc10nz==10'sd833/*833:xpc10nz*/)) xpc10nz <= 10'sd834/*834:xpc10nz*/; if ((xpc10nz==10'sd834/*834:xpc10nz*/)) xpc10nz <= 10'sd835/*835:xpc10nz*/; if ((xpc10nz==10'sd835/*835:xpc10nz*/)) xpc10nz <= 10'sd836/*836:xpc10nz*/; if ((xpc10nz==10'sd836/*836:xpc10nz*/)) xpc10nz <= 10'sd837/*837:xpc10nz*/; if ((xpc10nz==10'sd837/*837:xpc10nz*/)) xpc10nz <= 10'sd838/*838:xpc10nz*/; if ((xpc10nz==10'sd838/*838:xpc10nz*/)) xpc10nz <= 10'sd839/*839:xpc10nz*/; if ((xpc10nz==10'sd844/*844:xpc10nz*/)) xpc10nz <= 10'sd845/*845:xpc10nz*/; if ((xpc10nz==10'sd845/*845:xpc10nz*/)) xpc10nz <= 10'sd846/*846:xpc10nz*/; if ((xpc10nz==10'sd846/*846:xpc10nz*/)) xpc10nz <= 10'sd847/*847:xpc10nz*/; if ((xpc10nz==10'sd847/*847:xpc10nz*/)) xpc10nz <= 10'sd848/*848:xpc10nz*/; if ((xpc10nz==10'sd848/*848:xpc10nz*/)) xpc10nz <= 10'sd849/*849:xpc10nz*/; if ((xpc10nz==10'sd849/*849:xpc10nz*/)) xpc10nz <= 10'sd840/*840:xpc10nz*/; if ((xpc10nz==10'sd850/*850:xpc10nz*/)) xpc10nz <= 10'sd851/*851:xpc10nz*/; if ((xpc10nz==10'sd851/*851:xpc10nz*/)) xpc10nz <= 10'sd852/*852:xpc10nz*/; if ((xpc10nz==10'sd852/*852:xpc10nz*/)) xpc10nz <= 10'sd853/*853:xpc10nz*/; if ((xpc10nz==10'sd853/*853:xpc10nz*/)) xpc10nz <= 10'sd854/*854:xpc10nz*/; if ((xpc10nz==10'sd854/*854:xpc10nz*/)) xpc10nz <= 10'sd855/*855:xpc10nz*/; if ((xpc10nz==10'sd855/*855:xpc10nz*/)) xpc10nz <= 10'sd856/*856:xpc10nz*/; if ((xpc10nz==10'sd856/*856:xpc10nz*/)) xpc10nz <= 10'sd857/*857:xpc10nz*/; if ((xpc10nz==10'sd860/*860:xpc10nz*/)) xpc10nz <= 10'sd861/*861:xpc10nz*/; if ((xpc10nz==10'sd861/*861:xpc10nz*/)) xpc10nz <= 10'sd725/*725:xpc10nz*/; if ((xpc10nz==10'sd862/*862:xpc10nz*/)) xpc10nz <= 10'sd863/*863:xpc10nz*/; if ((xpc10nz==10'sd866/*866:xpc10nz*/)) xpc10nz <= 10'sd719/*719:xpc10nz*/; if ((xpc10nz==10'sd867/*867:xpc10nz*/)) xpc10nz <= 10'sd868/*868:xpc10nz*/; if ((xpc10nz==10'sd868/*868:xpc10nz*/)) xpc10nz <= 10'sd869/*869:xpc10nz*/; if ((xpc10nz==10'sd869/*869:xpc10nz*/)) xpc10nz <= 10'sd870/*870:xpc10nz*/; if ((xpc10nz==10'sd870/*870:xpc10nz*/)) xpc10nz <= 10'sd871/*871:xpc10nz*/; if ((xpc10nz==10'sd871/*871:xpc10nz*/)) xpc10nz <= 10'sd872/*872:xpc10nz*/; if ((xpc10nz==10'sd872/*872:xpc10nz*/)) xpc10nz <= 10'sd873/*873:xpc10nz*/; if ((xpc10nz==10'sd873/*873:xpc10nz*/)) xpc10nz <= 10'sd874/*874:xpc10nz*/; if ((xpc10nz==10'sd874/*874:xpc10nz*/)) xpc10nz <= 10'sd875/*875:xpc10nz*/; if ((xpc10nz==10'sd875/*875:xpc10nz*/)) xpc10nz <= 10'sd876/*876:xpc10nz*/; if ((xpc10nz==10'sd876/*876:xpc10nz*/)) xpc10nz <= 10'sd877/*877:xpc10nz*/; if ((xpc10nz==10'sd877/*877:xpc10nz*/)) xpc10nz <= 10'sd878/*878:xpc10nz*/; if ((xpc10nz==10'sd878/*878:xpc10nz*/)) xpc10nz <= 10'sd879/*879:xpc10nz*/; if ((xpc10nz==10'sd879/*879:xpc10nz*/)) xpc10nz <= 10'sd880/*880:xpc10nz*/; if ((xpc10nz==10'sd880/*880:xpc10nz*/)) xpc10nz <= 10'sd864/*864:xpc10nz*/; if ((xpc10nz==10'sd884/*884:xpc10nz*/)) xpc10nz <= 10'sd885/*885:xpc10nz*/; if ((xpc10nz==10'sd894/*894:xpc10nz*/)) xpc10nz <= 10'sd903/*903:xpc10nz*/; if ((xpc10nz==10'sd895/*895:xpc10nz*/)) xpc10nz <= 10'sd896/*896:xpc10nz*/; if ((xpc10nz==10'sd896/*896:xpc10nz*/)) xpc10nz <= 10'sd897/*897:xpc10nz*/; if ((xpc10nz==10'sd897/*897:xpc10nz*/)) xpc10nz <= 10'sd898/*898:xpc10nz*/; if ((xpc10nz==10'sd898/*898:xpc10nz*/)) xpc10nz <= 10'sd899/*899:xpc10nz*/; if ((xpc10nz==10'sd899/*899:xpc10nz*/)) xpc10nz <= 10'sd900/*900:xpc10nz*/; if ((xpc10nz==10'sd900/*900:xpc10nz*/)) xpc10nz <= 10'sd901/*901:xpc10nz*/; if ((xpc10nz==10'sd901/*901:xpc10nz*/)) xpc10nz <= 10'sd902/*902:xpc10nz*/; if ((xpc10nz==10'sd907/*907:xpc10nz*/)) xpc10nz <= 10'sd903/*903:xpc10nz*/; if ((xpc10nz==10'sd908/*908:xpc10nz*/)) xpc10nz <= 10'sd909/*909:xpc10nz*/; if ((xpc10nz==10'sd909/*909:xpc10nz*/)) xpc10nz <= 10'sd910/*910:xpc10nz*/; if ((xpc10nz==10'sd910/*910:xpc10nz*/)) xpc10nz <= 10'sd911/*911:xpc10nz*/; if ((xpc10nz==10'sd911/*911:xpc10nz*/)) xpc10nz <= 10'sd912/*912:xpc10nz*/; if ((xpc10nz==10'sd912/*912:xpc10nz*/)) xpc10nz <= 10'sd913/*913:xpc10nz*/; if ((xpc10nz==10'sd913/*913:xpc10nz*/)) xpc10nz <= 10'sd914/*914:xpc10nz*/; if ((xpc10nz==10'sd914/*914:xpc10nz*/)) xpc10nz <= 10'sd915/*915:xpc10nz*/; if ((xpc10nz==10'sd919/*919:xpc10nz*/)) xpc10nz <= 10'sd920/*920:xpc10nz*/; if ((xpc10nz==10'sd928/*928:xpc10nz*/)) xpc10nz <= 10'sd929/*929:xpc10nz*/; if ((xpc10nz==10'sd935/*935:xpc10nz*/)) xpc10nz <= 10'sd981/*981:xpc10nz*/; if ((xpc10nz==10'sd937/*937:xpc10nz*/)) xpc10nz <= 10'sd938/*938:xpc10nz*/; if ((xpc10nz==10'sd938/*938:xpc10nz*/)) xpc10nz <= 10'sd939/*939:xpc10nz*/; if ((xpc10nz==10'sd939/*939:xpc10nz*/)) xpc10nz <= 10'sd940/*940:xpc10nz*/; if ((xpc10nz==10'sd940/*940:xpc10nz*/)) xpc10nz <= 10'sd941/*941:xpc10nz*/; if ((xpc10nz==10'sd941/*941:xpc10nz*/)) xpc10nz <= 10'sd942/*942:xpc10nz*/; if ((xpc10nz==10'sd942/*942:xpc10nz*/)) xpc10nz <= 10'sd943/*943:xpc10nz*/; if ((xpc10nz==10'sd945/*945:xpc10nz*/)) xpc10nz <= 10'sd946/*946:xpc10nz*/; if ((xpc10nz==10'sd946/*946:xpc10nz*/)) xpc10nz <= 10'sd947/*947:xpc10nz*/; if ((xpc10nz==10'sd947/*947:xpc10nz*/)) xpc10nz <= 10'sd948/*948:xpc10nz*/; if ((xpc10nz==10'sd948/*948:xpc10nz*/)) xpc10nz <= 10'sd949/*949:xpc10nz*/; if ((xpc10nz==10'sd951/*951:xpc10nz*/)) xpc10nz <= 10'sd952/*952:xpc10nz*/; if ((xpc10nz==10'sd952/*952:xpc10nz*/)) xpc10nz <= 10'sd953/*953:xpc10nz*/; if ((xpc10nz==10'sd953/*953:xpc10nz*/)) xpc10nz <= 10'sd954/*954:xpc10nz*/; if ((xpc10nz==10'sd954/*954:xpc10nz*/)) xpc10nz <= 10'sd955/*955:xpc10nz*/; if ((xpc10nz==10'sd955/*955:xpc10nz*/)) xpc10nz <= 10'sd956/*956:xpc10nz*/; if ((xpc10nz==10'sd956/*956:xpc10nz*/)) xpc10nz <= 10'sd957/*957:xpc10nz*/; if ((xpc10nz==10'sd957/*957:xpc10nz*/)) xpc10nz <= 10'sd958/*958:xpc10nz*/; if ((xpc10nz==10'sd958/*958:xpc10nz*/)) xpc10nz <= 10'sd959/*959:xpc10nz*/; if ((xpc10nz==10'sd959/*959:xpc10nz*/)) xpc10nz <= 10'sd960/*960:xpc10nz*/; if ((xpc10nz==10'sd960/*960:xpc10nz*/)) xpc10nz <= 10'sd969/*969:xpc10nz*/; if ((xpc10nz==10'sd962/*962:xpc10nz*/)) xpc10nz <= 10'sd963/*963:xpc10nz*/; if ((xpc10nz==10'sd963/*963:xpc10nz*/)) xpc10nz <= 10'sd964/*964:xpc10nz*/; if ((xpc10nz==10'sd964/*964:xpc10nz*/)) xpc10nz <= 10'sd965/*965:xpc10nz*/; if ((xpc10nz==10'sd965/*965:xpc10nz*/)) xpc10nz <= 10'sd966/*966:xpc10nz*/; if ((xpc10nz==10'sd966/*966:xpc10nz*/)) xpc10nz <= 10'sd967/*967:xpc10nz*/; if ((xpc10nz==10'sd967/*967:xpc10nz*/)) xpc10nz <= 10'sd968/*968:xpc10nz*/; if ((xpc10nz==10'sd971/*971:xpc10nz*/)) xpc10nz <= 10'sd972/*972:xpc10nz*/; if ((xpc10nz==10'sd972/*972:xpc10nz*/)) xpc10nz <= 10'sd973/*973:xpc10nz*/; if ((xpc10nz==10'sd973/*973:xpc10nz*/)) xpc10nz <= 10'sd974/*974:xpc10nz*/; if ((xpc10nz==10'sd974/*974:xpc10nz*/)) xpc10nz <= 10'sd975/*975:xpc10nz*/; if ((xpc10nz==10'sd975/*975:xpc10nz*/)) xpc10nz <= 10'sd976/*976:xpc10nz*/; if ((xpc10nz==10'sd976/*976:xpc10nz*/)) xpc10nz <= 10'sd977/*977:xpc10nz*/; if ((xpc10nz==10'sd977/*977:xpc10nz*/)) xpc10nz <= 10'sd978/*978:xpc10nz*/; if ((xpc10nz==10'sd978/*978:xpc10nz*/)) xpc10nz <= 10'sd979/*979:xpc10nz*/; if ((xpc10nz==10'sd979/*979:xpc10nz*/)) xpc10nz <= 10'sd980/*980:xpc10nz*/; if ((xpc10nz==10'sd980/*980:xpc10nz*/)) xpc10nz <= 10'sd969/*969:xpc10nz*/; if ((xpc10nz==10'sd983/*983:xpc10nz*/)) xpc10nz <= 10'sd981/*981:xpc10nz*/; if ((xpc10nz==10'sd986/*986:xpc10nz*/)) xpc10nz <= 10'sd984/*984:xpc10nz*/; if ((xpc10nz==10'sd990/*990:xpc10nz*/)) xpc10nz <= 10'sd685/*685:xpc10nz*/; end //End structure HPR lu-decomp end CV_SP_SSRAM_FL1 #(32'sd64, 32'sd6, 32'sd64, 32'sd64) A_FPD_CC_SCALbx44_ARG0(clk, reset, A_FPD_CC_SCALbx44_ARG0_RDD0, A_FPD_CC_SCALbx44_ARG0_AD0 , A_FPD_CC_SCALbx44_ARG0_WEN0, A_FPD_CC_SCALbx44_ARG0_REN0, A_FPD_CC_SCALbx44_ARG0_WRD0); CV_FP_FL4_DP_ADDER CVFPADDER10(clk, reset, CVFPADDER10_FPRR, CVFPADDER10_A0, CVFPADDER10_A1, CVFPADDER10_fail); CV_FP_FL4_DP_ADDER CVFPADDER12(clk, reset, CVFPADDER12_FPRR, CVFPADDER12_A0, CVFPADDER12_A1, CVFPADDER12_fail); CV_FP_FL4_DP_ADDER CVFPADDER14(clk, reset, CVFPADDER14_FPRR, CVFPADDER14_A0, CVFPADDER14_A1, CVFPADDER14_fail); CV_FP_FL4_DP_ADDER CVFPADDER16(clk, reset, CVFPADDER16_FPRR, CVFPADDER16_A0, CVFPADDER16_A1, CVFPADDER16_fail); CV_FP_FL4_DP_ADDER CVFPADDER18(clk, reset, CVFPADDER18_FPRR, CVFPADDER18_A0, CVFPADDER18_A1, CVFPADDER18_fail); CV_FP_FL4_DP_ADDER CVFPADDER20(clk, reset, CVFPADDER20_FPRR, CVFPADDER20_A0, CVFPADDER20_A1, CVFPADDER20_fail); CV_SP_SSRAM_FL1 #(32'sd64, 32'sd6, 32'sd64, 32'sd64) A_FPD_CC_SCALbx34_ARB0(clk, reset, A_FPD_CC_SCALbx34_ARB0_RDD0, A_FPD_CC_SCALbx34_ARB0_AD0 , A_FPD_CC_SCALbx34_ARB0_WEN0, A_FPD_CC_SCALbx34_ARB0_REN0, A_FPD_CC_SCALbx34_ARB0_WRD0); CV_SP_SSRAM_FL1 #(32'sd64, 32'sd6, 32'sd64, 32'sd64) A_FPD_CC_SCALbx32_ARA0(clk, reset, A_FPD_CC_SCALbx32_ARA0_RDD0, A_FPD_CC_SCALbx32_ARA0_AD0 , A_FPD_CC_SCALbx32_ARA0_WEN0, A_FPD_CC_SCALbx32_ARA0_REN0, A_FPD_CC_SCALbx32_ARA0_WRD0); CV_SP_SSRAM_FL1 #(32'sd64, 32'sd3, 32'sd8, 32'sd64) A_FPD_CC_SCALbx38_ARD0(clk, reset, A_FPD_CC_SCALbx38_ARD0_RDD0, A_FPD_CC_SCALbx38_ARD0_AD0 , A_FPD_CC_SCALbx38_ARD0_WEN0, A_FPD_CC_SCALbx38_ARD0_REN0, A_FPD_CC_SCALbx38_ARD0_WRD0); CV_FP_CVT_FL2_F64_I32 ifpcvt10(clk, fpcvt10_result, fpcvt10_arg, fpcvt10_fail); CV_FP_FL3_DP_MULTIPLIER CVFPMULTIPLIER10(clk, reset, CVFPMULTIPLIER10_FPRR, CVFPMULTIPLIER10_A0, CVFPMULTIPLIER10_A1, CVFPMULTIPLIER10_fail ); CV_FP_CVT_FL2_F64_I32 ifpcvt12(clk, fpcvt12_result, fpcvt12_arg, fpcvt12_fail); CV_FP_FL3_DP_MULTIPLIER CVFPMULTIPLIER12(clk, reset, CVFPMULTIPLIER12_FPRR, CVFPMULTIPLIER12_A0, CVFPMULTIPLIER12_A1, CVFPMULTIPLIER12_fail ); CV_SP_SSRAM_FL1 #(32'sd64, 32'sd3, 32'sd8, 32'sd64) A_FPD_CC_SCALbx40_ARE0(clk, reset, A_FPD_CC_SCALbx40_ARE0_RDD0, A_FPD_CC_SCALbx40_ARE0_AD0 , A_FPD_CC_SCALbx40_ARE0_WEN0, A_FPD_CC_SCALbx40_ARE0_REN0, A_FPD_CC_SCALbx40_ARE0_WRD0); CV_SP_SSRAM_FL1 #(32'sd64, 32'sd3, 32'sd8, 32'sd64) A_FPD_CC_SCALbx42_ARF0(clk, reset, A_FPD_CC_SCALbx42_ARF0_RDD0, A_FPD_CC_SCALbx42_ARF0_AD0 , A_FPD_CC_SCALbx42_ARF0_WEN0, A_FPD_CC_SCALbx42_ARF0_REN0, A_FPD_CC_SCALbx42_ARF0_WRD0); CV_SP_SSRAM_FL1 #(32'sd64, 32'sd3, 32'sd8, 32'sd64) A_FPD_CC_SCALbx46_ARH0(clk, reset, A_FPD_CC_SCALbx46_ARH0_RDD0, A_FPD_CC_SCALbx46_ARH0_AD0 , A_FPD_CC_SCALbx46_ARH0_WEN0, A_FPD_CC_SCALbx46_ARH0_REN0, A_FPD_CC_SCALbx46_ARH0_WRD0); CV_FP_FL3_DP_MULTIPLIER CVFPMULTIPLIER14(clk, reset, CVFPMULTIPLIER14_FPRR, CVFPMULTIPLIER14_A0, CVFPMULTIPLIER14_A1, CVFPMULTIPLIER14_fail ); CV_FP_FL3_DP_MULTIPLIER CVFPMULTIPLIER16(clk, reset, CVFPMULTIPLIER16_FPRR, CVFPMULTIPLIER16_A0, CVFPMULTIPLIER16_A1, CVFPMULTIPLIER16_fail ); CV_FP_FL5_DP_DIVIDER CVFPDIVIDER10(clk, reset, CVFPDIVIDER10_FPRR, CVFPDIVIDER10_NN, CVFPDIVIDER10_DD, CVFPDIVIDER10_fail); CV_FP_FL3_DP_MULTIPLIER CVFPMULTIPLIER18(clk, reset, CVFPMULTIPLIER18_FPRR, CVFPMULTIPLIER18_A0, CVFPMULTIPLIER18_A1, CVFPMULTIPLIER18_fail ); CV_FP_FL5_DP_DIVIDER CVFPDIVIDER12(clk, reset, CVFPDIVIDER12_FPRR, CVFPDIVIDER12_NN, CVFPDIVIDER12_DD, CVFPDIVIDER12_fail); CV_FP_FL3_DP_MULTIPLIER CVFPMULTIPLIER20(clk, reset, CVFPMULTIPLIER20_FPRR, CVFPMULTIPLIER20_A0, CVFPMULTIPLIER20_A1, CVFPMULTIPLIER20_fail ); CV_FP_FL3_DP_MULTIPLIER CVFPMULTIPLIER22(clk, reset, CVFPMULTIPLIER22_FPRR, CVFPMULTIPLIER22_A0, CVFPMULTIPLIER22_A1, CVFPMULTIPLIER22_fail ); CV_FP_FL3_DP_MULTIPLIER CVFPMULTIPLIER24(clk, reset, CVFPMULTIPLIER24_FPRR, CVFPMULTIPLIER24_A0, CVFPMULTIPLIER24_A1, CVFPMULTIPLIER24_fail ); CV_FP_CVT_FL2_F64_I32 ifpcvt14(clk, fpcvt14_result, fpcvt14_arg, fpcvt14_fail); CV_FP_FL3_DP_MULTIPLIER CVFPMULTIPLIER26(clk, reset, CVFPMULTIPLIER26_FPRR, CVFPMULTIPLIER26_A0, CVFPMULTIPLIER26_A1, CVFPMULTIPLIER26_fail ); CV_FP_CVT_FL2_F64_I32 ifpcvt16(clk, fpcvt16_result, fpcvt16_arg, fpcvt16_fail); CV_FP_FL3_DP_MULTIPLIER CVFPMULTIPLIER28(clk, reset, CVFPMULTIPLIER28_FPRR, CVFPMULTIPLIER28_A0, CVFPMULTIPLIER28_A1, CVFPMULTIPLIER28_fail ); CV_SP_SSRAM_FL1 #(32'sd64, 32'sd6, 32'sd64, 32'sd64) A_FPD_CC_SCALbx36_ARC0(clk, reset, A_FPD_CC_SCALbx36_ARC0_RDD0, A_FPD_CC_SCALbx36_ARC0_AD0 , A_FPD_CC_SCALbx36_ARC0_WEN0, A_FPD_CC_SCALbx36_ARC0_REN0, A_FPD_CC_SCALbx36_ARC0_WRD0); CV_FP_FL5_DP_DIVIDER CVFPDIVIDER14(clk, reset, CVFPDIVIDER14_FPRR, CVFPDIVIDER14_NN, CVFPDIVIDER14_DD, CVFPDIVIDER14_fail); CV_FP_FL5_DP_DIVIDER CVFPDIVIDER16(clk, reset, CVFPDIVIDER16_FPRR, CVFPDIVIDER16_NN, CVFPDIVIDER16_DD, CVFPDIVIDER16_fail); // 1 vectors of width 10 // 107 vectors of width 1 // 83 vectors of width 64 // 4 vectors of width 6 // 4 vectors of width 32 // 4 vectors of width 3 // 96 bits in scalar variables // Total state bits in module = 5689 bits. // 2136 continuously assigned (wire/non-state) bits // cell CV_SP_SSRAM_FL1 count=8 // cell CV_FP_FL4_DP_ADDER count=6 // cell CV_FP_CVT_FL2_F64_I32 count=4 // cell CV_FP_FL3_DP_MULTIPLIER count=10 // cell CV_FP_FL5_DP_DIVIDER count=4 // Total number of leaf cells = 32 endmodule // // LCP delay estimations included: turn off with -vnl-lcp-delay-estimate=disable //HPR L/S (orangepath) auxiliary reports. //KiwiC compilation report //Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 2.16a : 25th-August-2016 //26/08/2016 18:50:10 //Cmd line args: /home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/kiwic.exe -give-backtrace -vnl-rootmodname=DUT -vnl=lu-decomp.v lu-decomp.exe -vnl-resets=synchronous -kiwic-cil-dump=combined -kiwic-kcode-dump=enable -res2-loadstore-port-count=0 -vnl-roundtrip=disable -max_no_int_divs=10 -max_no_fp_divs=10 -max_no_int_muls=10 -max_no_fp_muls=10 -int_fl_limit_mul=20 -bevelab-default-pause-mode=soft -bevelab-soft-pause-threshold=5 -kiwic-register-colours=1 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation KiKiwi for prefix KiwiSystem/Kiwi //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation SyBitConverter for prefix System/BitConverter //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation CS0.2 for prefix CS/0.2 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation CS0.5 for prefix CS/0.5 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation T.cCZ:0:9 for prefix T402/.cctor/CZ:0:9 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation CS0.13 for prefix CS/0.13 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation T.cCZ:0:13 for prefix T402/.cctor/CZ:0:13 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation T.cCZ:0:17 for prefix T402/.cctor/CZ:0:17 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation @$s@ for prefix @/$star1$/@ //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation lTMT4Main for prefix luTest/T403/Main/T403/Main //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation lTMaCZ:0:5 for prefix luTest/T403/Main/CZ:0:5 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation S.cCZ:0:11 for prefix SimuSolve/.ctor/CZ:0:11 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation CS0.16 for prefix CS/0.16 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation CS0.21 for prefix CS/0.21 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation Tlge0.9 for prefix T403/luTest/generate_example_coefficients/0.9 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TMco0.12 for prefix T403/MatrixLib/copy2d/0.12 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TKG3._SPILL for prefix T403/KIWIARRAY2D`1/GetLength/3.4/_SPILL //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TKG5._SPILL for prefix T403/KIWIARRAY2D`1/GetLength/5.4/_SPILL //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TMpr0.6 for prefix T403/MatrixLib/printa/0.6 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TSLU0.11 for prefix T403/SimuSolve/LUdecompose/0.11 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TMpr0.15 for prefix T403/MatrixLib/printa/0.15 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TMpr0.19 for prefix T403/MatrixLib/printa/0.19 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TMmp0.26 for prefix T403/MatrixLib/mpx/0.26 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TKG4._SPILL for prefix T403/KIWIARRAY2D`1/GetLength/4.4/_SPILL //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TKG6._SPILL for prefix T403/KIWIARRAY2D`1/GetLength/6.4/_SPILL //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TKG8._SPILL for prefix T403/KIWIARRAY2D`1/GetLength/8.4/_SPILL //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TMpr0.30 for prefix T403/MatrixLib/printa/0.30 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation Tlge1.7 for prefix T403/luTest/generate_example_rhs/1.7 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TSSo1.12 for prefix T403/SimuSolve/SolveVerbose/1.12 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TSFw0.4 for prefix T403/SimuSolve/FwdsSubst/0.4 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TMpr0.9 for prefix T403/MatrixLib/printa/0.9 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TSBa0.13 for prefix T403/SimuSolve/BackSubst/0.13 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TMpr0.18 for prefix T403/MatrixLib/printa/0.18 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TMmp1.19 for prefix T403/MatrixLib/mpx/1.19 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TMpr1.20 for prefix T403/MatrixLib/printa/1.20 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation @$sKIWIARRAY2D`1 for prefix @/$star1$/KIWIARRAY2D`1 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TMm1.V_1 for prefix T403/MatrixLib/mpx/1.19/V_1 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TMm1.V_2 for prefix T403/MatrixLib/mpx/1.19/V_2 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TMp1.V_0 for prefix T403/MatrixLib/printa/1.20/V_0 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation $s@ for prefix $star1$/@ //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation lTMTMaV_1 for prefix luTest/T403/Main/T403/Main/V_1 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation $sKIWIARRAY2D`1 for prefix $star1$/KIWIARRAY2D`1 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation lTMTMaV_2 for prefix luTest/T403/Main/T403/Main/V_2 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation KIFPD/CT for prefix KIWIARRAY2D`1/FPD/CT //---------------------------------------------------------- //Report from KiwiC-fe.rpt::: //KiwiC: front end input processing of class or method called KiwiSystem/Kiwi // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor10 // //KiwiC start_thread (or entry point) id=cctor10 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+0 // //KiwiC: front end input processing of class or method called System/BitConverter // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor12 // //KiwiC start_thread (or entry point) id=cctor12 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+1 // //KiwiC: front end input processing of class or method called luTest // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor14 // //KiwiC start_thread (or entry point) id=cctor14 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+2 // //KiwiC: front end input processing of class or method called luTest // //root_compiler: start elaborating class 'luTest' // //elaborating class 'luTest' // //compiling static method as entry point: style=Root idl=luTest/Main // //Performing root elaboration of method Main // //KiwiC start_thread (or entry point) id=Main10 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_1/GP used for T403/MatrixLib/mpx/1.19/V_1 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_1/GP used for T403/MatrixLib/mpx/1.19/V_1 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_1/GP used for T403/SimuSolve/BackSubst/0.13/V_1 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_1/GP used for T403/SimuSolve/BackSubst/0.13/V_1 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_1/GP used for T403/SimuSolve/FwdsSubst/0.4/V_1 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_1/GP used for T403/SimuSolve/FwdsSubst/0.4/V_1 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_1/GP used for T403/MatrixLib/mpx/0.26/V_2 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_1/GP used for T403/MatrixLib/mpx/0.26/V_2 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_1/GP used for T403/SimuSolve/LUdecompose/0.11/V_4 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_1/GP used for T403/SimuSolve/LUdecompose/0.11/V_4 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_1/GP used for T403/luTest/generate_example_coefficients/0.9/V_0 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_1/GP used for T403/luTest/generate_example_coefficients/0.9/V_0 // //Register sharing: general luTest/T403/Main/T403/Main/V_1/GP used for luTest/T403/Main/T403/Main/V_1 // //Register sharing: general luTest/T403/Main/T403/Main/V_1/GP used for luTest/T403/Main/T403/Main/V_1 // //Register sharing: general luTest/T403/Main/T403/Main/V_1/GP used for T403/MatrixLib/printa/0.30/V_0 // //Register sharing: general luTest/T403/Main/T403/Main/V_1/GP used for T403/MatrixLib/printa/0.30/V_0 // //Register sharing: general luTest/T403/Main/T403/Main/V_1/GP used for T403/MatrixLib/mpx/0.26/V_0 // //Register sharing: general luTest/T403/Main/T403/Main/V_1/GP used for T403/MatrixLib/mpx/0.26/V_0 // //Register sharing: general luTest/T403/Main/T403/Main/V_1/GP used for T403/MatrixLib/printa/0.19/V_0 // //Register sharing: general luTest/T403/Main/T403/Main/V_1/GP used for T403/MatrixLib/printa/0.19/V_0 // //Register sharing: general luTest/T403/Main/T403/Main/V_1/GP used for T403/MatrixLib/printa/0.15/V_0 // //Register sharing: general luTest/T403/Main/T403/Main/V_1/GP used for T403/MatrixLib/printa/0.15/V_0 // //Register sharing: general luTest/T403/Main/T403/Main/V_1/GP used for T403/SimuSolve/LUdecompose/0.11/V_5 // //Register sharing: general luTest/T403/Main/T403/Main/V_1/GP used for T403/SimuSolve/LUdecompose/0.11/V_5 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/printa/1.20/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/printa/1.20/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/mpx/1.19/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/mpx/1.19/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/printa/0.18/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/printa/0.18/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/SimuSolve/BackSubst/0.13/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/SimuSolve/BackSubst/0.13/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/printa/0.9/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/printa/0.9/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/SimuSolve/FwdsSubst/0.4/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/SimuSolve/FwdsSubst/0.4/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/luTest/generate_example_rhs/1.7/V_1 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/luTest/generate_example_rhs/1.7/V_1 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/luTest/generate_example_rhs/1.7/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/luTest/generate_example_rhs/1.7/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/printa/0.30/V_1 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/printa/0.30/V_1 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/mpx/0.26/V_1 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/mpx/0.26/V_1 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/printa/0.19/V_1 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/printa/0.19/V_1 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/printa/0.15/V_1 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/printa/0.15/V_1 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/SimuSolve/LUdecompose/0.11/V_1 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/SimuSolve/LUdecompose/0.11/V_1 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/SimuSolve/LUdecompose/0.11/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/SimuSolve/LUdecompose/0.11/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/printa/0.6/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/printa/0.6/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/copy2d/0.12/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/MatrixLib/copy2d/0.12/V_0 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/luTest/generate_example_coefficients/0.9/V_3 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/luTest/generate_example_coefficients/0.9/V_3 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/luTest/generate_example_coefficients/0.9/V_2 // //Register sharing: general T403/MatrixLib/printa/1.20/V_0/GP used for T403/luTest/generate_example_coefficients/0.9/V_2 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/MatrixLib/mpx/1.19/V_2 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/MatrixLib/mpx/1.19/V_2 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/SimuSolve/BackSubst/0.13/V_2 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/SimuSolve/BackSubst/0.13/V_2 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/SimuSolve/FwdsSubst/0.4/V_2 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/SimuSolve/FwdsSubst/0.4/V_2 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/MatrixLib/mpx/0.26/V_3 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/MatrixLib/mpx/0.26/V_3 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/SimuSolve/LUdecompose/0.11/V_3 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/SimuSolve/LUdecompose/0.11/V_3 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/SimuSolve/LUdecompose/0.11/V_2 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/SimuSolve/LUdecompose/0.11/V_2 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/MatrixLib/printa/0.6/V_1 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/MatrixLib/printa/0.6/V_1 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/MatrixLib/copy2d/0.12/V_1 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/MatrixLib/copy2d/0.12/V_1 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/luTest/generate_example_coefficients/0.9/V_1 // //Register sharing: general T403/MatrixLib/mpx/1.19/V_2/GP used for T403/luTest/generate_example_coefficients/0.9/V_1 // //Register sharing: general luTest/T403/Main/T403/Main/V_2/GP used for luTest/T403/Main/T403/Main/V_2 // //Register sharing: general luTest/T403/Main/T403/Main/V_2/GP used for luTest/T403/Main/T403/Main/V_2 // //Register sharing: general luTest/T403/Main/T403/Main/V_2/GP used for T403/SimuSolve/SolveVerbose/1.12/V_1 // //Register sharing: general luTest/T403/Main/T403/Main/V_2/GP used for T403/SimuSolve/SolveVerbose/1.12/V_1 // //Register sharing: general luTest/T403/Main/T403/Main/V_2/GP used for T403/SimuSolve/SolveVerbose/1.12/V_0 // //Register sharing: general luTest/T403/Main/T403/Main/V_2/GP used for T403/SimuSolve/SolveVerbose/1.12/V_0 // //root_compiler class done: luTest // //Report of all settings used from the recipe or command line: // // cil-uwind-budget=10000 // // kiwic-finish=enable // // kiwic-cil-dump=combined // // kiwic-kcode-dump=enable // // kiwic-register-colours=1 // // array-4d-name=KIWIARRAY4D // // array-3d-name=KIWIARRAY3D // // array-2d-name=KIWIARRAY2D // // kiwi-dll=Kiwi.dll // // kiwic-dll=Kiwic.dll // // kiwic-zerolength-arrays=disable // // kiwic-fpgaconsole-default=enable // // postgen-optimise=enable // // gtrace-loglevel=20 // // firstpass-loglevel=20 // // root=$attributeroot // // srcfile=lu-decomp.exe // //END OF KIWIC REPORT FILE // //---------------------------------------------------------- //Report from enumbers::: //Concise expression alias report. // // -- No expression aliases to report // //---------------------------------------------------------- //Report from restructure2::: //Offchip Load/Store (and other) Ports = Nothing to Report // //---------------------------------------------------------- //Report from restructure2::: //Restructure Technology Settings //*---------------------------+---------+---------------------------------------------------------------------------------* //| Key | Value | Description | //*---------------------------+---------+---------------------------------------------------------------------------------* //| int_flr_mul | -3000 | | //| max_no_fp_addsubs | 6 | Maximum number of adders and subtractors (or combos) to instantiate per thread. | //| max_no_fp_muls | 10 | Maximum number of f/p multipliers or dividers to instantiate per thread. | //| max_no_int_muls | 10 | Maximum number of int multipliers to instantiate per thread. | //| max_no_fp_divs | 10 | Maximum number of f/p dividers to instantiate per thread. | //| max_no_int_divs | 10 | Maximum number of int dividers to instantiate per thread. | //| fp_fl_dp_div | 5 | | //| fp_fl_dp_add | 4 | | //| fp_fl_dp_mul | 3 | | //| fp_fl_sp_div | 5 | | //| fp_fl_sp_add | 4 | | //| fp_fl_sp_mul | 3 | | //| res2-loadstore-port-count | 0 | | //| res2-offchip-threshold | 1000000 | | //| res2-combrom-threshold | 64 | | //| res2-combram-threshold | 32 | | //| res2-regfile-threshold | 8 | | //*---------------------------+---------+---------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: //PC codings points for xpc10 //*--------------------+------+--------------+------+------+-------+-----+-------------+------* //| gb-flag/Pause | eno | hwm | root | exec | start | end | antecedants | next | //*--------------------+------+--------------+------+------+-------+-----+-------------+------* //| X0:"0:xpc10" | 900 | hwm=0.0.0 | 0 | 0 | - | - | --- | 1 | //| X1:"1:xpc10" | 901 | hwm=0.0.0 | 1 | 1 | - | - | --- | 2 | //| X2:"2:xpc10" | 902 | hwm=0.0.0 | 2 | 2 | - | - | --- | 3 | //| X3:"3:xpc10" | 903 | hwm=0.0.0 | 3 | 3 | - | - | --- | 4 | //| X4:"4:xpc10" | 904 | hwm=0.0.0 | 4 | 4 | - | - | --- | 5 | //| X5:"5:xpc10" | 905 | hwm=0.0.0 | 5 | 5 | - | - | --- | 6 | //| X6:"6:xpc10" | 906 | hwm=0.0.0 | 6 | 6 | - | - | --- | 7 | //| X7:"7:xpc10" | 907 | hwm=0.0.0 | 7 | 7 | - | - | --- | 8 | //| X8:"8:xpc10" | 908 | hwm=0.0.0 | 8 | 8 | - | - | --- | 9 | //| X9:"9:xpc10" | 909 | hwm=0.0.0 | 9 | 9 | - | - | --- | 10 | //| X10:"10:xpc10" | 910 | hwm=0.0.0 | 10 | 10 | - | - | --- | 11 | //| X11:"11:xpc10" | 911 | hwm=0.0.0 | 11 | 11 | - | - | --- | 12 | //| X12:"12:xpc10" | 912 | hwm=0.0.0 | 12 | 12 | - | - | --- | 13 | //| X13:"13:xpc10" | 913 | hwm=0.0.0 | 13 | 13 | - | - | --- | 14 | //| X14:"14:xpc10" | 914 | hwm=0.0.0 | 14 | 14 | - | - | --- | 15 | //| X15:"15:xpc10" | 915 | hwm=0.0.0 | 15 | 15 | - | - | --- | 16 | //| X16:"16:xpc10" | 916 | hwm=0.0.0 | 16 | 16 | - | - | --- | 17 | //| X17:"17:xpc10" | 917 | hwm=0.0.0 | 17 | 17 | - | - | --- | 18 | //| X18:"18:xpc10" | 918 | hwm=0.0.0 | 18 | 18 | - | - | --- | 19 | //| X19:"19:xpc10" | 919 | hwm=0.0.0 | 19 | 19 | - | - | --- | 20 | //| X20:"20:xpc10" | 920 | hwm=0.0.0 | 20 | 20 | - | - | --- | 21 | //| X21:"21:xpc10" | 921 | hwm=0.0.0 | 21 | 21 | - | - | --- | 22 | //| X22:"22:xpc10" | 922 | hwm=0.0.0 | 22 | 22 | - | - | --- | 23 | //| X23:"23:xpc10" | 923 | hwm=0.0.0 | 23 | 23 | - | - | --- | 24 | //| X24:"24:xpc10" | 924 | hwm=0.0.0 | 24 | 24 | - | - | --- | 25 | //| X25:"25:xpc10" | 925 | hwm=0.0.0 | 25 | 25 | - | - | --- | 26 | //| X26:"26:xpc10" | 926 | hwm=0.0.0 | 26 | 26 | - | - | --- | 27 | //| X27:"27:xpc10" | 927 | hwm=0.0.0 | 27 | 27 | - | - | --- | 28 | //| X28:"28:xpc10" | 928 | hwm=0.0.0 | 28 | 28 | - | - | --- | 29 | //| X29:"29:xpc10" | 929 | hwm=0.0.0 | 29 | 29 | - | - | --- | 30 | //| X30:"30:xpc10" | 930 | hwm=0.0.0 | 30 | 30 | - | - | --- | 31 | //| X31:"31:xpc10" | 931 | hwm=0.0.0 | 31 | 31 | - | - | --- | 32 | //| X32:"32:xpc10" | 932 | hwm=0.0.0 | 32 | 32 | - | - | --- | 33 | //| X33:"33:xpc10" | 933 | hwm=0.0.0 | 33 | 33 | - | - | --- | 34 | //| X34:"34:xpc10" | 934 | hwm=0.0.0 | 34 | 34 | - | - | --- | 35 | //| X35:"35:xpc10" | 935 | hwm=0.0.0 | 35 | 35 | - | - | --- | 36 | //| X36:"36:xpc10" | 936 | hwm=0.0.0 | 36 | 36 | - | - | --- | 37 | //| X37:"37:xpc10" | 937 | hwm=0.0.0 | 37 | 37 | - | - | --- | 38 | //| X38:"38:xpc10" | 938 | hwm=0.0.0 | 38 | 38 | - | - | --- | 39 | //| X39:"39:xpc10" | 939 | hwm=0.0.0 | 39 | 39 | - | - | --- | 40 | //| X40:"40:xpc10" | 940 | hwm=0.0.1 | 40 | 40 | 41 | 41 | --- | 42 | //| X41:"41:xpc10" | 941 | hwm=0.0.0 | 42 | 42 | - | - | --- | 43 | //| X42:"42:xpc10" | 942 | hwm=0.0.0 | 43 | 43 | - | - | --- | 44 | //| X43:"43:xpc10" | 943 | hwm=0.0.1 | 44 | 44 | 45 | 45 | --- | 46 | //| X44:"44:xpc10" | 944 | hwm=0.0.0 | 46 | 46 | - | - | --- | 47 | //| X45:"45:xpc10" | 945 | hwm=0.0.0 | 47 | 47 | - | - | --- | 48 | //| X46:"46:xpc10" | 946 | hwm=0.0.1 | 48 | 48 | 49 | 49 | --- | 50 | //| X47:"47:xpc10" | 947 | hwm=0.0.0 | 50 | 50 | - | - | --- | 51 | //| X48:"48:xpc10" | 948 | hwm=0.0.0 | 51 | 51 | - | - | --- | 52 | //| X49:"49:xpc10" | 949 | hwm=0.0.1 | 52 | 52 | 53 | 53 | --- | 54 | //| X50:"50:xpc10" | 950 | hwm=0.0.0 | 54 | 54 | - | - | --- | 55 | //| X51:"51:xpc10" | 951 | hwm=0.0.0 | 55 | 55 | - | - | --- | 56 | //| X52:"52:xpc10" | 952 | hwm=0.0.1 | 56 | 56 | 57 | 57 | --- | 58 | //| X53:"53:xpc10" | 953 | hwm=0.0.0 | 58 | 58 | - | - | --- | 59 | //| X54:"54:xpc10" | 954 | hwm=0.0.0 | 59 | 59 | - | - | --- | 60 | //| X55:"55:xpc10" | 955 | hwm=0.0.1 | 60 | 60 | 61 | 61 | --- | 62 | //| X56:"56:xpc10" | 956 | hwm=0.0.0 | 62 | 62 | - | - | --- | 63 | //| X57:"57:xpc10" | 957 | hwm=0.0.0 | 63 | 63 | - | - | --- | 64 | //| X58:"58:xpc10" | 958 | hwm=0.0.1 | 64 | 64 | 65 | 65 | --- | 66 | //| X59:"59:xpc10" | 959 | hwm=0.0.0 | 66 | 66 | - | - | --- | 67 | //| X60:"60:xpc10" | 960 | hwm=0.0.0 | 67 | 67 | - | - | --- | 68 | //| X61:"61:xpc10" | 961 | hwm=0.0.1 | 68 | 68 | 69 | 69 | --- | 70 | //| X62:"62:xpc10" | 962 | hwm=0.0.0 | 70 | 70 | - | - | --- | 71 | //| X63:"63:xpc10" | 963 | hwm=0.0.0 | 71 | 71 | - | - | --- | 72 | //| X64:"64:xpc10" | 964 | hwm=0.0.0 | 72 | 72 | - | - | --- | 73 | //| X65:"65:xpc10" | 965 | hwm=0.0.0 | 73 | 73 | - | - | --- | 74 | //| X66:"66:xpc10" | 966 | hwm=0.0.1 | 74 | 74 | 75 | 75 | --- | 76 | //| X67:"67:xpc10" | 967 | hwm=0.0.0 | 76 | 76 | - | - | --- | 77 | //| X68:"68:xpc10" | 968 | hwm=0.0.0 | 77 | 77 | - | - | --- | 78 | //| X69:"69:xpc10" | 969 | hwm=0.0.1 | 78 | 78 | 79 | 79 | --- | 80 | //| X70:"70:xpc10" | 970 | hwm=0.0.0 | 80 | 80 | - | - | --- | 81 | //| X71:"71:xpc10" | 971 | hwm=0.0.0 | 81 | 81 | - | - | --- | 82 | //| X72:"72:xpc10" | 972 | hwm=0.0.1 | 82 | 82 | 83 | 83 | --- | 84 | //| X73:"73:xpc10" | 973 | hwm=0.0.0 | 84 | 84 | - | - | --- | 85 | //| X74:"74:xpc10" | 974 | hwm=0.0.0 | 85 | 85 | - | - | --- | 86 | //| X75:"75:xpc10" | 975 | hwm=0.0.1 | 86 | 86 | 87 | 87 | --- | 88 | //| X76:"76:xpc10" | 976 | hwm=0.0.0 | 88 | 88 | - | - | --- | 89 | //| X77:"77:xpc10" | 977 | hwm=0.0.0 | 89 | 89 | - | - | --- | 90 | //| X78:"78:xpc10" | 978 | hwm=0.0.1 | 90 | 90 | 91 | 91 | --- | 92 | //| X79:"79:xpc10" | 979 | hwm=0.0.0 | 92 | 92 | - | - | --- | 93 | //| X80:"80:xpc10" | 980 | hwm=0.0.0 | 93 | 93 | - | - | --- | 94 | //| X81:"81:xpc10" | 981 | hwm=0.0.1 | 94 | 94 | 95 | 95 | --- | 96 | //| X82:"82:xpc10" | 982 | hwm=0.0.0 | 96 | 96 | - | - | --- | 97 | //| X83:"83:xpc10" | 983 | hwm=0.0.0 | 97 | 97 | - | - | --- | 98 | //| X84:"84:xpc10" | 984 | hwm=0.0.1 | 98 | 98 | 99 | 99 | --- | 100 | //| X85:"85:xpc10" | 985 | hwm=0.0.0 | 100 | 100 | - | - | --- | 101 | //| X86:"86:xpc10" | 986 | hwm=0.0.0 | 101 | 101 | - | - | --- | 102 | //| X87:"87:xpc10" | 987 | hwm=0.0.1 | 102 | 102 | 103 | 103 | --- | 104 | //| X88:"88:xpc10" | 988 | hwm=0.0.0 | 104 | 104 | - | - | --- | 105 | //| X89:"89:xpc10" | 989 | hwm=0.0.0 | 105 | 105 | - | - | --- | 106 | //| X90:"90:xpc10" | 990 | hwm=0.0.0 | 106 | 106 | - | - | --- | 107 | //| X91:"91:xpc10" | 991 | hwm=0.0.0 | 107 | 107 | - | - | --- | 108 | //| X92:"92:xpc10" | 992 | hwm=0.0.1 | 108 | 108 | 109 | 109 | --- | 110 | //| X93:"93:xpc10" | 993 | hwm=0.0.0 | 110 | 110 | - | - | --- | 111 | //| X94:"94:xpc10" | 994 | hwm=0.0.0 | 111 | 111 | - | - | --- | 112 | //| X95:"95:xpc10" | 995 | hwm=0.0.1 | 112 | 112 | 113 | 113 | --- | 114 | //| X96:"96:xpc10" | 996 | hwm=0.0.0 | 114 | 114 | - | - | --- | 115 | //| X97:"97:xpc10" | 997 | hwm=0.0.0 | 115 | 115 | - | - | --- | 116 | //| X98:"98:xpc10" | 998 | hwm=0.0.1 | 116 | 116 | 117 | 117 | --- | 118 | //| X99:"99:xpc10" | 999 | hwm=0.0.0 | 118 | 118 | - | - | --- | 119 | //| X100:"100:xpc10" | 1000 | hwm=0.0.0 | 119 | 119 | - | - | --- | 120 | //| X101:"101:xpc10" | 1001 | hwm=0.0.1 | 120 | 120 | 121 | 121 | --- | 122 | //| X102:"102:xpc10" | 1002 | hwm=0.0.0 | 122 | 122 | - | - | --- | 123 | //| X103:"103:xpc10" | 1003 | hwm=0.0.0 | 123 | 123 | - | - | --- | 124 | //| X104:"104:xpc10" | 1004 | hwm=0.0.1 | 124 | 124 | 125 | 125 | --- | 126 | //| X105:"105:xpc10" | 1005 | hwm=0.0.0 | 126 | 126 | - | - | --- | 127 | //| X106:"106:xpc10" | 1006 | hwm=0.0.0 | 127 | 127 | - | - | --- | 128 | //| X107:"107:xpc10" | 1007 | hwm=0.0.1 | 128 | 128 | 129 | 129 | --- | 130 | //| X108:"108:xpc10" | 1008 | hwm=0.0.0 | 130 | 130 | - | - | --- | 131 | //| X109:"109:xpc10" | 1009 | hwm=0.0.0 | 131 | 131 | - | - | --- | 132 | //| X110:"110:xpc10" | 1010 | hwm=0.0.1 | 132 | 132 | 133 | 133 | --- | 134 | //| X111:"111:xpc10" | 1011 | hwm=0.0.0 | 134 | 134 | - | - | --- | 135 | //| X112:"112:xpc10" | 1012 | hwm=0.0.0 | 135 | 135 | - | - | --- | 136 | //| X113:"113:xpc10" | 1013 | hwm=0.0.1 | 136 | 136 | 137 | 137 | --- | 138 | //| X114:"114:xpc10" | 1014 | hwm=0.0.0 | 138 | 138 | - | - | --- | 139 | //| X115:"115:xpc10" | 1015 | hwm=0.0.0 | 139 | 139 | - | - | --- | 140 | //| X116:"116:xpc10" | 1016 | hwm=0.0.0 | 140 | 140 | - | - | --- | 141 | //| X117:"117:xpc10" | 1017 | hwm=0.0.0 | 141 | 141 | - | - | --- | 142 | //| X118:"118:xpc10" | 1018 | hwm=0.0.1 | 142 | 142 | 143 | 143 | --- | 144 | //| X119:"119:xpc10" | 1019 | hwm=0.0.0 | 144 | 144 | - | - | --- | 145 | //| X120:"120:xpc10" | 1020 | hwm=0.0.0 | 145 | 145 | - | - | --- | 146 | //| X121:"121:xpc10" | 1021 | hwm=0.0.1 | 146 | 146 | 147 | 147 | --- | 148 | //| X122:"122:xpc10" | 1022 | hwm=0.0.0 | 148 | 148 | - | - | --- | 149 | //| X123:"123:xpc10" | 1023 | hwm=0.0.0 | 149 | 149 | - | - | --- | 150 | //| X124:"124:xpc10" | 1024 | hwm=0.0.1 | 150 | 150 | 151 | 151 | --- | 152 | //| X125:"125:xpc10" | 1025 | hwm=0.0.0 | 152 | 152 | - | - | --- | 153 | //| X126:"126:xpc10" | 1026 | hwm=0.0.0 | 153 | 153 | - | - | --- | 154 | //| X127:"127:xpc10" | 1027 | hwm=0.0.1 | 154 | 154 | 155 | 155 | --- | 156 | //| X128:"128:xpc10" | 1028 | hwm=0.0.0 | 156 | 156 | - | - | --- | 157 | //| X129:"129:xpc10" | 1029 | hwm=0.0.0 | 157 | 157 | - | - | --- | 158 | //| X130:"130:xpc10" | 1030 | hwm=0.0.1 | 158 | 158 | 159 | 159 | --- | 160 | //| X131:"131:xpc10" | 1031 | hwm=0.0.0 | 160 | 160 | - | - | --- | 161 | //| X132:"132:xpc10" | 1032 | hwm=0.0.0 | 161 | 161 | - | - | --- | 162 | //| X133:"133:xpc10" | 1033 | hwm=0.0.1 | 162 | 162 | 163 | 163 | --- | 164 | //| X134:"134:xpc10" | 1034 | hwm=0.0.0 | 164 | 164 | - | - | --- | 165 | //| X135:"135:xpc10" | 1035 | hwm=0.0.0 | 165 | 165 | - | - | --- | 166 | //| X136:"136:xpc10" | 1036 | hwm=0.0.1 | 166 | 166 | 167 | 167 | --- | 168 | //| X137:"137:xpc10" | 1037 | hwm=0.0.0 | 168 | 168 | - | - | --- | 169 | //| X138:"138:xpc10" | 1038 | hwm=0.0.0 | 169 | 169 | - | - | --- | 170 | //| X139:"139:xpc10" | 1039 | hwm=0.0.1 | 170 | 170 | 171 | 171 | --- | 172 | //| X140:"140:xpc10" | 1040 | hwm=0.0.0 | 172 | 172 | - | - | --- | 173 | //| X141:"141:xpc10" | 1041 | hwm=0.0.0 | 173 | 173 | - | - | --- | 174 | //| X142:"142:xpc10" | 1042 | hwm=0.0.0 | 174 | 174 | - | - | --- | 175 | //| X143:"143:xpc10" | 1043 | hwm=0.0.0 | 175 | 175 | - | - | --- | 176 | //| X144:"144:xpc10" | 1044 | hwm=0.0.1 | 176 | 176 | 177 | 177 | --- | 178 | //| X145:"145:xpc10" | 1045 | hwm=0.0.0 | 178 | 178 | - | - | --- | 179 | //| X146:"146:xpc10" | 1046 | hwm=0.0.0 | 179 | 179 | - | - | --- | 180 | //| X147:"147:xpc10" | 1047 | hwm=0.0.1 | 180 | 180 | 181 | 181 | --- | 182 | //| X148:"148:xpc10" | 1048 | hwm=0.0.0 | 182 | 182 | - | - | --- | 183 | //| X149:"149:xpc10" | 1049 | hwm=0.0.0 | 183 | 183 | - | - | --- | 184 | //| X150:"150:xpc10" | 1050 | hwm=0.0.1 | 184 | 184 | 185 | 185 | --- | 186 | //| X151:"151:xpc10" | 1051 | hwm=0.0.0 | 186 | 186 | - | - | --- | 187 | //| X152:"152:xpc10" | 1052 | hwm=0.0.0 | 187 | 187 | - | - | --- | 188 | //| X153:"153:xpc10" | 1053 | hwm=0.0.1 | 188 | 188 | 189 | 189 | --- | 190 | //| X154:"154:xpc10" | 1054 | hwm=0.0.0 | 190 | 190 | - | - | --- | 191 | //| X155:"155:xpc10" | 1055 | hwm=0.0.0 | 191 | 191 | - | - | --- | 192 | //| X156:"156:xpc10" | 1056 | hwm=0.0.1 | 192 | 192 | 193 | 193 | --- | 194 | //| X157:"157:xpc10" | 1057 | hwm=0.0.0 | 194 | 194 | - | - | --- | 195 | //| X158:"158:xpc10" | 1058 | hwm=0.0.0 | 195 | 195 | - | - | --- | 196 | //| X159:"159:xpc10" | 1059 | hwm=0.0.1 | 196 | 196 | 197 | 197 | --- | 198 | //| X160:"160:xpc10" | 1060 | hwm=0.0.0 | 198 | 198 | - | - | --- | 199 | //| X161:"161:xpc10" | 1061 | hwm=0.0.0 | 199 | 199 | - | - | --- | 200 | //| X162:"162:xpc10" | 1062 | hwm=0.0.1 | 200 | 200 | 201 | 201 | --- | 202 | //| X163:"163:xpc10" | 1063 | hwm=0.0.0 | 202 | 202 | - | - | --- | 203 | //| X164:"164:xpc10" | 1064 | hwm=0.0.0 | 203 | 203 | - | - | --- | 204 | //| X165:"165:xpc10" | 1065 | hwm=0.0.1 | 204 | 204 | 205 | 205 | --- | 206 | //| X166:"166:xpc10" | 1066 | hwm=0.0.0 | 206 | 206 | - | - | --- | 207 | //| X167:"167:xpc10" | 1067 | hwm=0.0.0 | 207 | 207 | - | - | --- | 208 | //| X168:"168:xpc10" | 1068 | hwm=0.0.0 | 208 | 208 | - | - | --- | 209 | //| X169:"169:xpc10" | 1069 | hwm=0.0.0 | 209 | 209 | - | - | --- | 210 | //| X170:"170:xpc10" | 1070 | hwm=0.0.1 | 210 | 210 | 211 | 211 | --- | 212 | //| X171:"171:xpc10" | 1071 | hwm=0.0.0 | 212 | 212 | - | - | --- | 213 | //| X172:"172:xpc10" | 1072 | hwm=0.0.0 | 213 | 213 | - | - | --- | 214 | //| X173:"173:xpc10" | 1073 | hwm=0.0.1 | 214 | 214 | 215 | 215 | --- | 216 | //| X174:"174:xpc10" | 1074 | hwm=0.0.0 | 216 | 216 | - | - | --- | 217 | //| X175:"175:xpc10" | 1075 | hwm=0.0.0 | 217 | 217 | - | - | --- | 218 | //| X176:"176:xpc10" | 1076 | hwm=0.0.1 | 218 | 218 | 219 | 219 | --- | 220 | //| X177:"177:xpc10" | 1077 | hwm=0.0.0 | 220 | 220 | - | - | --- | 221 | //| X178:"178:xpc10" | 1078 | hwm=0.0.0 | 221 | 221 | - | - | --- | 222 | //| X179:"179:xpc10" | 1079 | hwm=0.0.1 | 222 | 222 | 223 | 223 | --- | 224 | //| X180:"180:xpc10" | 1080 | hwm=0.0.0 | 224 | 224 | - | - | --- | 225 | //| X181:"181:xpc10" | 1081 | hwm=0.0.0 | 225 | 225 | - | - | --- | 226 | //| X182:"182:xpc10" | 1082 | hwm=0.0.1 | 226 | 226 | 227 | 227 | --- | 228 | //| X183:"183:xpc10" | 1083 | hwm=0.0.0 | 228 | 228 | - | - | --- | 229 | //| X184:"184:xpc10" | 1084 | hwm=0.0.0 | 229 | 229 | - | - | --- | 230 | //| X185:"185:xpc10" | 1085 | hwm=0.0.1 | 230 | 230 | 231 | 231 | --- | 232 | //| X186:"186:xpc10" | 1086 | hwm=0.0.0 | 232 | 232 | - | - | --- | 233 | //| X187:"187:xpc10" | 1087 | hwm=0.0.0 | 233 | 233 | - | - | --- | 234 | //| X188:"188:xpc10" | 1088 | hwm=0.0.1 | 234 | 234 | 235 | 235 | --- | 236 | //| X189:"189:xpc10" | 1089 | hwm=0.0.0 | 236 | 236 | - | - | --- | 237 | //| X190:"190:xpc10" | 1090 | hwm=0.0.0 | 237 | 237 | - | - | --- | 238 | //| X191:"191:xpc10" | 1091 | hwm=0.0.1 | 238 | 238 | 239 | 239 | --- | 240 | //| X192:"192:xpc10" | 1092 | hwm=0.0.0 | 240 | 240 | - | - | --- | 241 | //| X193:"193:xpc10" | 1093 | hwm=0.0.0 | 241 | 241 | - | - | --- | 242 | //| X194:"194:xpc10" | 1094 | hwm=0.0.0 | 242 | 242 | - | - | --- | 243 | //| X195:"195:xpc10" | 1095 | hwm=0.0.0 | 243 | 243 | - | - | --- | 244 | //| X196:"196:xpc10" | 1096 | hwm=0.0.1 | 244 | 244 | 245 | 245 | --- | 246 | //| X197:"197:xpc10" | 1097 | hwm=0.0.0 | 246 | 246 | - | - | --- | 247 | //| X198:"198:xpc10" | 1098 | hwm=0.0.0 | 247 | 247 | - | - | --- | 248 | //| X199:"199:xpc10" | 1099 | hwm=0.0.1 | 248 | 248 | 249 | 249 | --- | 250 | //| X200:"200:xpc10" | 1100 | hwm=0.0.0 | 250 | 250 | - | - | --- | 251 | //| X201:"201:xpc10" | 1101 | hwm=0.0.0 | 251 | 251 | - | - | --- | 252 | //| X202:"202:xpc10" | 1102 | hwm=0.0.1 | 252 | 252 | 253 | 253 | --- | 254 | //| X203:"203:xpc10" | 1103 | hwm=0.0.0 | 254 | 254 | - | - | --- | 255 | //| X204:"204:xpc10" | 1104 | hwm=0.0.0 | 255 | 255 | - | - | --- | 256 | //| X205:"205:xpc10" | 1105 | hwm=0.0.1 | 256 | 256 | 257 | 257 | --- | 258 | //| X206:"206:xpc10" | 1106 | hwm=0.0.0 | 258 | 258 | - | - | --- | 259 | //| X207:"207:xpc10" | 1107 | hwm=0.0.0 | 259 | 259 | - | - | --- | 260 | //| X208:"208:xpc10" | 1108 | hwm=0.0.1 | 260 | 260 | 261 | 261 | --- | 262 | //| X209:"209:xpc10" | 1109 | hwm=0.0.0 | 262 | 262 | - | - | --- | 263 | //| X210:"210:xpc10" | 1110 | hwm=0.0.0 | 263 | 263 | - | - | --- | 264 | //| X211:"211:xpc10" | 1111 | hwm=0.0.1 | 264 | 264 | 265 | 265 | --- | 266 | //| X212:"212:xpc10" | 1112 | hwm=0.0.0 | 266 | 266 | - | - | --- | 267 | //| X213:"213:xpc10" | 1113 | hwm=0.0.0 | 267 | 267 | - | - | --- | 268 | //| X214:"214:xpc10" | 1114 | hwm=0.0.1 | 268 | 268 | 269 | 269 | --- | 270 | //| X215:"215:xpc10" | 1115 | hwm=0.0.0 | 270 | 270 | - | - | --- | 271 | //| X216:"216:xpc10" | 1116 | hwm=0.0.0 | 271 | 271 | - | - | --- | 272 | //| X217:"217:xpc10" | 1117 | hwm=0.0.1 | 272 | 272 | 273 | 273 | --- | 274 | //| X218:"218:xpc10" | 1118 | hwm=0.0.0 | 274 | 274 | - | - | --- | 275 | //| X219:"219:xpc10" | 1119 | hwm=0.0.0 | 275 | 275 | - | - | --- | 276 | //| X220:"220:xpc10" | 1120 | hwm=0.0.0 | 276 | 276 | - | - | --- | 277 | //| X221:"221:xpc10" | 1121 | hwm=0.0.0 | 277 | 277 | - | - | --- | 278 | //| X222:"222:xpc10" | 1122 | hwm=0.0.1 | 278 | 278 | 279 | 279 | --- | 280 | //| X223:"223:xpc10" | 1123 | hwm=0.0.0 | 280 | 280 | - | - | --- | 281 | //| X224:"224:xpc10" | 1124 | hwm=0.0.0 | 281 | 281 | - | - | --- | 282 | //| X225:"225:xpc10" | 1125 | hwm=0.0.1 | 282 | 282 | 283 | 283 | --- | 284 | //| X226:"226:xpc10" | 1126 | hwm=0.0.0 | 284 | 284 | - | - | --- | 285 | //| X227:"227:xpc10" | 1127 | hwm=0.0.0 | 285 | 285 | - | - | --- | 286 | //| X228:"228:xpc10" | 1128 | hwm=0.0.1 | 286 | 286 | 287 | 287 | --- | 288 | //| X229:"229:xpc10" | 1129 | hwm=0.0.0 | 288 | 288 | - | - | --- | 289 | //| X230:"230:xpc10" | 1130 | hwm=0.0.0 | 289 | 289 | - | - | --- | 290 | //| X231:"231:xpc10" | 1131 | hwm=0.0.1 | 290 | 290 | 291 | 291 | --- | 292 | //| X232:"232:xpc10" | 1132 | hwm=0.0.0 | 292 | 292 | - | - | --- | 293 | //| X233:"233:xpc10" | 1133 | hwm=0.0.0 | 293 | 293 | - | - | --- | 294 | //| X234:"234:xpc10" | 1134 | hwm=0.0.1 | 294 | 294 | 295 | 295 | --- | 296 | //| X235:"235:xpc10" | 1135 | hwm=0.0.0 | 296 | 296 | - | - | --- | 297 | //| X236:"236:xpc10" | 1136 | hwm=0.0.0 | 297 | 297 | - | - | --- | 298 | //| X237:"237:xpc10" | 1137 | hwm=0.0.1 | 298 | 298 | 299 | 299 | --- | 300 | //| X238:"238:xpc10" | 1138 | hwm=0.0.0 | 300 | 300 | - | - | --- | 301 | //| X239:"239:xpc10" | 1139 | hwm=0.0.0 | 301 | 301 | - | - | --- | 302 | //| X240:"240:xpc10" | 1140 | hwm=0.0.1 | 302 | 302 | 303 | 303 | --- | 304 | //| X241:"241:xpc10" | 1141 | hwm=0.0.0 | 304 | 304 | - | - | --- | 305 | //| X242:"242:xpc10" | 1142 | hwm=0.0.0 | 305 | 305 | - | - | --- | 306 | //| X243:"243:xpc10" | 1143 | hwm=0.0.1 | 306 | 306 | 307 | 307 | --- | 308 | //| X244:"244:xpc10" | 1144 | hwm=0.0.0 | 308 | 308 | - | - | --- | 309 | //| X245:"245:xpc10" | 1145 | hwm=0.0.0 | 309 | 309 | - | - | --- | 310 | //| X246:"246:xpc10" | 1146 | hwm=0.0.0 | 310 | 310 | - | - | --- | 311 | //| X247:"247:xpc10" | 1147 | hwm=0.0.0 | 311 | 311 | - | - | --- | 312 | //| X248:"248:xpc10" | 1148 | hwm=0.1.0 | 312 | 313 | 313 | 313 | --- | 314 | //| X249:"249:xpc10" | 1149 | hwm=0.4.1 | 314 | 318 | 315 | 319 | --- | 320 | //| X250:"250:xpc10" | 1150 | hwm=0.0.0 | 320 | 320 | - | - | --- | 321 | //| X251:"251:xpc10" | 1151 | hwm=0.1.0 | 321 | 322 | 322 | 322 | --- | 323 | //| X252:"252:xpc10" | 1152 | hwm=0.4.1 | 323 | 327 | 324 | 328 | --- | 329 | //| X253:"253:xpc10" | 1153 | hwm=0.0.0 | 329 | 329 | - | - | --- | 330 | //| X254:"254:xpc10" | 1154 | hwm=0.1.0 | 330 | 331 | 331 | 331 | --- | 332 | //| X255:"255:xpc10" | 1155 | hwm=0.4.1 | 332 | 336 | 333 | 337 | --- | 338 | //| X256:"256:xpc10" | 1156 | hwm=0.0.0 | 338 | 338 | - | - | --- | 339 | //| X257:"257:xpc10" | 1157 | hwm=0.1.0 | 339 | 340 | 340 | 340 | --- | 341 | //| X258:"258:xpc10" | 1158 | hwm=0.4.1 | 341 | 345 | 342 | 346 | --- | 347 | //| X259:"259:xpc10" | 1159 | hwm=0.0.0 | 347 | 347 | - | - | --- | 348 | //| X260:"260:xpc10" | 1160 | hwm=0.1.0 | 348 | 349 | 349 | 349 | --- | 350 | //| X261:"261:xpc10" | 1161 | hwm=0.4.1 | 350 | 354 | 351 | 355 | --- | 356 | //| X262:"262:xpc10" | 1162 | hwm=0.0.0 | 356 | 356 | - | - | --- | 357 | //| X263:"263:xpc10" | 1163 | hwm=0.1.0 | 357 | 358 | 358 | 358 | --- | 359 | //| X264:"264:xpc10" | 1164 | hwm=0.4.1 | 359 | 363 | 360 | 364 | --- | 365 | //| X265:"265:xpc10" | 1165 | hwm=0.0.0 | 365 | 365 | - | - | --- | 366 | //| X266:"266:xpc10" | 1166 | hwm=0.1.0 | 366 | 367 | 367 | 367 | --- | 368 | //| X267:"267:xpc10" | 1167 | hwm=0.4.1 | 368 | 372 | 369 | 373 | --- | 374 | //| X268:"268:xpc10" | 1168 | hwm=0.0.0 | 374 | 374 | - | - | --- | 375 | //| X269:"269:xpc10" | 1169 | hwm=0.1.0 | 375 | 376 | 376 | 376 | --- | 377 | //| X270:"270:xpc10" | 1170 | hwm=0.4.1 | 377 | 381 | 378 | 382 | --- | 383 | //| X271:"271:xpc10" | 1171 | hwm=0.0.0 | 383 | 383 | - | - | --- | 384 | //| X272:"272:xpc10" | 1172 | hwm=0.0.0 | 384 | 384 | - | - | --- | 385 | //| X273:"273:xpc10" | 1173 | hwm=0.0.0 | 385 | 385 | - | - | --- | 386 | //| X274:"274:xpc10" | 1174 | hwm=0.1.1 | 386 | 387 | 387 | 388 | --- | 389 | //| X275:"275:xpc10" | 1175 | hwm=0.0.0 | 389 | 389 | - | - | --- | 390 | //| X276:"276:xpc10" | 1176 | hwm=0.1.1 | 390 | 391 | 391 | 392 | --- | 393 | //| X277:"277:xpc10" | 1177 | hwm=0.0.0 | 393 | 393 | - | - | --- | 394 | //| X278:"278:xpc10" | 1178 | hwm=0.1.1 | 394 | 395 | 395 | 396 | --- | 397 | //| X279:"279:xpc10" | 1179 | hwm=0.0.0 | 397 | 397 | - | - | --- | 398 | //| X280:"280:xpc10" | 1180 | hwm=0.1.1 | 398 | 399 | 399 | 400 | --- | 401 | //| X281:"281:xpc10" | 1181 | hwm=0.0.0 | 401 | 401 | - | - | --- | 402 | //| X282:"282:xpc10" | 1182 | hwm=0.1.1 | 402 | 403 | 403 | 404 | --- | 405 | //| X283:"283:xpc10" | 1183 | hwm=0.0.0 | 405 | 405 | - | - | --- | 406 | //| X284:"284:xpc10" | 1184 | hwm=0.1.1 | 406 | 407 | 407 | 408 | --- | 409 | //| X285:"285:xpc10" | 1185 | hwm=0.0.0 | 409 | 409 | - | - | --- | 410 | //| X286:"286:xpc10" | 1186 | hwm=0.1.1 | 410 | 411 | 411 | 412 | --- | 413 | //| X287:"287:xpc10" | 1187 | hwm=0.0.0 | 413 | 413 | - | - | --- | 414 | //| X288:"288:xpc10" | 1188 | hwm=0.1.1 | 414 | 415 | 415 | 416 | --- | 417 | //| X289:"289:xpc10" | 1189 | hwm=0.0.0 | 417 | 417 | - | - | --- | 418 | //| X290:"290:xpc10" | 1190 | hwm=0.0.0 | 418 | 418 | - | - | --- | 419 | //| X291:"291:xpc10" | 1191 | hwm=0.0.0 | 419 | 419 | - | - | --- | 420 | //| X292:"292:xpc10" | 1192 | hwm=0.1.1 | 420 | 421 | 421 | 422 | --- | 423 | //| X293:"293:xpc10" | 1193 | hwm=0.0.0 | 423 | 423 | - | - | --- | 424 | //| X294:"294:xpc10" | 1194 | hwm=0.1.1 | 424 | 425 | 425 | 426 | --- | 427 | //| X295:"295:xpc10" | 1195 | hwm=0.0.0 | 427 | 427 | - | - | --- | 428 | //| X296:"296:xpc10" | 1196 | hwm=0.1.1 | 428 | 429 | 429 | 430 | --- | 431 | //| X297:"297:xpc10" | 1197 | hwm=0.0.0 | 431 | 431 | - | - | --- | 432 | //| X298:"298:xpc10" | 1198 | hwm=0.1.1 | 432 | 433 | 433 | 434 | --- | 435 | //| X299:"299:xpc10" | 1199 | hwm=0.0.0 | 435 | 435 | - | - | --- | 436 | //| X300:"300:xpc10" | 1200 | hwm=0.1.1 | 436 | 437 | 437 | 438 | --- | 439 | //| X301:"301:xpc10" | 1201 | hwm=0.0.0 | 439 | 439 | - | - | --- | 440 | //| X302:"302:xpc10" | 1202 | hwm=0.1.1 | 440 | 441 | 441 | 442 | --- | 443 | //| X303:"303:xpc10" | 1203 | hwm=0.0.0 | 443 | 443 | - | - | --- | 444 | //| X304:"304:xpc10" | 1204 | hwm=0.1.1 | 444 | 445 | 445 | 446 | --- | 447 | //| X305:"305:xpc10" | 1205 | hwm=0.0.0 | 447 | 447 | - | - | --- | 448 | //| X306:"306:xpc10" | 1206 | hwm=0.1.1 | 448 | 449 | 449 | 450 | --- | 451 | //| X307:"307:xpc10" | 1207 | hwm=0.0.0 | 451 | 451 | - | - | --- | 452 | //| X308:"308:xpc10" | 1208 | hwm=0.0.0 | 452 | 452 | - | - | --- | 453 | //| X309:"309:xpc10" | 1209 | hwm=0.0.0 | 453 | 453 | - | - | --- | 454 | //| X310:"310:xpc10" | 1210 | hwm=0.1.1 | 454 | 455 | 455 | 456 | --- | 457 | //| X311:"311:xpc10" | 1211 | hwm=0.0.0 | 457 | 457 | - | - | --- | 458 | //| X312:"312:xpc10" | 1212 | hwm=0.1.1 | 458 | 459 | 459 | 460 | --- | 461 | //| X313:"313:xpc10" | 1213 | hwm=0.0.0 | 461 | 461 | - | - | --- | 462 | //| X314:"314:xpc10" | 1214 | hwm=0.1.1 | 462 | 463 | 463 | 464 | --- | 465 | //| X315:"315:xpc10" | 1215 | hwm=0.0.0 | 465 | 465 | - | - | --- | 466 | //| X316:"316:xpc10" | 1216 | hwm=0.1.1 | 466 | 467 | 467 | 468 | --- | 469 | //| X317:"317:xpc10" | 1217 | hwm=0.0.0 | 469 | 469 | - | - | --- | 470 | //| X318:"318:xpc10" | 1218 | hwm=0.1.1 | 470 | 471 | 471 | 472 | --- | 473 | //| X319:"319:xpc10" | 1219 | hwm=0.0.0 | 473 | 473 | - | - | --- | 474 | //| X320:"320:xpc10" | 1220 | hwm=0.1.1 | 474 | 475 | 475 | 476 | --- | 477 | //| X321:"321:xpc10" | 1221 | hwm=0.0.0 | 477 | 477 | - | - | --- | 478 | //| X322:"322:xpc10" | 1222 | hwm=0.1.1 | 478 | 479 | 479 | 480 | --- | 481 | //| X323:"323:xpc10" | 1223 | hwm=0.0.0 | 481 | 481 | - | - | --- | 482 | //| X324:"324:xpc10" | 1224 | hwm=0.1.1 | 482 | 483 | 483 | 484 | --- | 485 | //| X325:"325:xpc10" | 1225 | hwm=0.0.0 | 485 | 485 | - | - | --- | 486 | //| X326:"326:xpc10" | 1226 | hwm=0.0.0 | 486 | 486 | - | - | --- | 487 | //| X327:"327:xpc10" | 1227 | hwm=0.0.0 | 487 | 487 | - | - | --- | 488 | //| X328:"328:xpc10" | 1228 | hwm=0.1.1 | 488 | 489 | 489 | 490 | --- | 491 | //| X329:"329:xpc10" | 1229 | hwm=0.0.0 | 491 | 491 | - | - | --- | 492 | //| X330:"330:xpc10" | 1230 | hwm=0.1.1 | 492 | 493 | 493 | 494 | --- | 495 | //| X331:"331:xpc10" | 1231 | hwm=0.0.0 | 495 | 495 | - | - | --- | 496 | //| X332:"332:xpc10" | 1232 | hwm=0.1.1 | 496 | 497 | 497 | 498 | --- | 499 | //| X333:"333:xpc10" | 1233 | hwm=0.0.0 | 499 | 499 | - | - | --- | 500 | //| X334:"334:xpc10" | 1234 | hwm=0.1.1 | 500 | 501 | 501 | 502 | --- | 503 | //| X335:"335:xpc10" | 1235 | hwm=0.0.0 | 503 | 503 | - | - | --- | 504 | //| X336:"336:xpc10" | 1236 | hwm=0.1.1 | 504 | 505 | 505 | 506 | --- | 507 | //| X337:"337:xpc10" | 1237 | hwm=0.0.0 | 507 | 507 | - | - | --- | 508 | //| X338:"338:xpc10" | 1238 | hwm=0.1.1 | 508 | 509 | 509 | 510 | --- | 511 | //| X339:"339:xpc10" | 1239 | hwm=0.0.0 | 511 | 511 | - | - | --- | 512 | //| X340:"340:xpc10" | 1240 | hwm=0.1.1 | 512 | 513 | 513 | 514 | --- | 515 | //| X341:"341:xpc10" | 1241 | hwm=0.0.0 | 515 | 515 | - | - | --- | 516 | //| X342:"342:xpc10" | 1242 | hwm=0.1.1 | 516 | 517 | 517 | 518 | --- | 519 | //| X343:"343:xpc10" | 1243 | hwm=0.0.0 | 519 | 519 | - | - | --- | 520 | //| X344:"344:xpc10" | 1244 | hwm=0.0.0 | 520 | 520 | - | - | --- | 521 | //| X345:"345:xpc10" | 1245 | hwm=0.0.0 | 521 | 521 | - | - | --- | 522 | //| X346:"346:xpc10" | 1246 | hwm=0.1.1 | 522 | 523 | 523 | 524 | --- | 525 | //| X347:"347:xpc10" | 1247 | hwm=0.0.0 | 525 | 525 | - | - | --- | 526 | //| X348:"348:xpc10" | 1248 | hwm=0.1.1 | 526 | 527 | 527 | 528 | --- | 529 | //| X349:"349:xpc10" | 1249 | hwm=0.0.0 | 529 | 529 | - | - | --- | 530 | //| X350:"350:xpc10" | 1250 | hwm=0.1.1 | 530 | 531 | 531 | 532 | --- | 533 | //| X351:"351:xpc10" | 1251 | hwm=0.0.0 | 533 | 533 | - | - | --- | 534 | //| X352:"352:xpc10" | 1252 | hwm=0.1.1 | 534 | 535 | 535 | 536 | --- | 537 | //| X353:"353:xpc10" | 1253 | hwm=0.0.0 | 537 | 537 | - | - | --- | 538 | //| X354:"354:xpc10" | 1254 | hwm=0.1.1 | 538 | 539 | 539 | 540 | --- | 541 | //| X355:"355:xpc10" | 1255 | hwm=0.0.0 | 541 | 541 | - | - | --- | 542 | //| X356:"356:xpc10" | 1256 | hwm=0.1.1 | 542 | 543 | 543 | 544 | --- | 545 | //| X357:"357:xpc10" | 1257 | hwm=0.0.0 | 545 | 545 | - | - | --- | 546 | //| X358:"358:xpc10" | 1258 | hwm=0.1.1 | 546 | 547 | 547 | 548 | --- | 549 | //| X359:"359:xpc10" | 1259 | hwm=0.0.0 | 549 | 549 | - | - | --- | 550 | //| X360:"360:xpc10" | 1260 | hwm=0.1.1 | 550 | 551 | 551 | 552 | --- | 553 | //| X361:"361:xpc10" | 1261 | hwm=0.0.0 | 553 | 553 | - | - | --- | 554 | //| X362:"362:xpc10" | 1262 | hwm=0.0.0 | 554 | 554 | - | - | --- | 555 | //| X363:"363:xpc10" | 1263 | hwm=0.0.0 | 555 | 555 | - | - | --- | 556 | //| X364:"364:xpc10" | 1264 | hwm=0.1.1 | 556 | 557 | 557 | 558 | --- | 559 | //| X365:"365:xpc10" | 1265 | hwm=0.0.0 | 559 | 559 | - | - | --- | 560 | //| X366:"366:xpc10" | 1266 | hwm=0.1.1 | 560 | 561 | 561 | 562 | --- | 563 | //| X367:"367:xpc10" | 1267 | hwm=0.0.0 | 563 | 563 | - | - | --- | 564 | //| X368:"368:xpc10" | 1268 | hwm=0.1.1 | 564 | 565 | 565 | 566 | --- | 567 | //| X369:"369:xpc10" | 1269 | hwm=0.0.0 | 567 | 567 | - | - | --- | 568 | //| X370:"370:xpc10" | 1270 | hwm=0.1.1 | 568 | 569 | 569 | 570 | --- | 571 | //| X371:"371:xpc10" | 1271 | hwm=0.0.0 | 571 | 571 | - | - | --- | 572 | //| X372:"372:xpc10" | 1272 | hwm=0.1.1 | 572 | 573 | 573 | 574 | --- | 575 | //| X373:"373:xpc10" | 1273 | hwm=0.0.0 | 575 | 575 | - | - | --- | 576 | //| X374:"374:xpc10" | 1274 | hwm=0.1.1 | 576 | 577 | 577 | 578 | --- | 579 | //| X375:"375:xpc10" | 1275 | hwm=0.0.0 | 579 | 579 | - | - | --- | 580 | //| X376:"376:xpc10" | 1276 | hwm=0.1.1 | 580 | 581 | 581 | 582 | --- | 583 | //| X377:"377:xpc10" | 1277 | hwm=0.0.0 | 583 | 583 | - | - | --- | 584 | //| X378:"378:xpc10" | 1278 | hwm=0.1.1 | 584 | 585 | 585 | 586 | --- | 587 | //| X379:"379:xpc10" | 1279 | hwm=0.0.0 | 587 | 587 | - | - | --- | 588 | //| X380:"380:xpc10" | 1280 | hwm=0.0.0 | 588 | 588 | - | - | --- | 589 | //| X381:"381:xpc10" | 1281 | hwm=0.0.0 | 589 | 589 | - | - | --- | 590 | //| X382:"382:xpc10" | 1282 | hwm=0.1.1 | 590 | 591 | 591 | 592 | --- | 593 | //| X383:"383:xpc10" | 1283 | hwm=0.0.0 | 593 | 593 | - | - | --- | 594 | //| X384:"384:xpc10" | 1284 | hwm=0.1.1 | 594 | 595 | 595 | 596 | --- | 597 | //| X385:"385:xpc10" | 1285 | hwm=0.0.0 | 597 | 597 | - | - | --- | 598 | //| X386:"386:xpc10" | 1286 | hwm=0.1.1 | 598 | 599 | 599 | 600 | --- | 601 | //| X387:"387:xpc10" | 1287 | hwm=0.0.0 | 601 | 601 | - | - | --- | 602 | //| X388:"388:xpc10" | 1288 | hwm=0.1.1 | 602 | 603 | 603 | 604 | --- | 605 | //| X389:"389:xpc10" | 1289 | hwm=0.0.0 | 605 | 605 | - | - | --- | 606 | //| X390:"390:xpc10" | 1290 | hwm=0.1.1 | 606 | 607 | 607 | 608 | --- | 609 | //| X391:"391:xpc10" | 1291 | hwm=0.0.0 | 609 | 609 | - | - | --- | 610 | //| X392:"392:xpc10" | 1292 | hwm=0.1.1 | 610 | 611 | 611 | 612 | --- | 613 | //| X393:"393:xpc10" | 1293 | hwm=0.0.0 | 613 | 613 | - | - | --- | 614 | //| X394:"394:xpc10" | 1294 | hwm=0.1.1 | 614 | 615 | 615 | 616 | --- | 617 | //| X395:"395:xpc10" | 1295 | hwm=0.0.0 | 617 | 617 | - | - | --- | 618 | //| X396:"396:xpc10" | 1296 | hwm=0.1.1 | 618 | 619 | 619 | 620 | --- | 621 | //| X397:"397:xpc10" | 1297 | hwm=0.0.0 | 621 | 621 | - | - | --- | 622 | //| X398:"398:xpc10" | 1298 | hwm=0.0.0 | 622 | 622 | - | - | --- | 623 | //| X399:"399:xpc10" | 1299 | hwm=0.0.0 | 623 | 623 | - | - | --- | 624 | //| X400:"400:xpc10" | 1300 | hwm=0.1.1 | 624 | 625 | 625 | 626 | --- | 627 | //| X401:"401:xpc10" | 1301 | hwm=0.0.0 | 627 | 627 | - | - | --- | 628 | //| X402:"402:xpc10" | 1302 | hwm=0.1.1 | 628 | 629 | 629 | 630 | --- | 631 | //| X403:"403:xpc10" | 1303 | hwm=0.0.0 | 631 | 631 | - | - | --- | 632 | //| X404:"404:xpc10" | 1304 | hwm=0.1.1 | 632 | 633 | 633 | 634 | --- | 635 | //| X405:"405:xpc10" | 1305 | hwm=0.0.0 | 635 | 635 | - | - | --- | 636 | //| X406:"406:xpc10" | 1306 | hwm=0.1.1 | 636 | 637 | 637 | 638 | --- | 639 | //| X407:"407:xpc10" | 1307 | hwm=0.0.0 | 639 | 639 | - | - | --- | 640 | //| X408:"408:xpc10" | 1308 | hwm=0.1.1 | 640 | 641 | 641 | 642 | --- | 643 | //| X409:"409:xpc10" | 1309 | hwm=0.0.0 | 643 | 643 | - | - | --- | 644 | //| X410:"410:xpc10" | 1310 | hwm=0.1.1 | 644 | 645 | 645 | 646 | --- | 647 | //| X411:"411:xpc10" | 1311 | hwm=0.0.0 | 647 | 647 | - | - | --- | 648 | //| X412:"412:xpc10" | 1312 | hwm=0.1.1 | 648 | 649 | 649 | 650 | --- | 651 | //| X413:"413:xpc10" | 1313 | hwm=0.0.0 | 651 | 651 | - | - | --- | 652 | //| X414:"414:xpc10" | 1314 | hwm=0.1.1 | 652 | 653 | 653 | 654 | --- | 655 | //| X415:"415:xpc10" | 1315 | hwm=0.0.0 | 655 | 655 | - | - | --- | 656 | //| X416:"416:xpc10" | 1316 | hwm=0.0.0 | 656 | 656 | - | - | --- | 657 | //| X417:"417:xpc10" | 1317 | hwm=0.0.0 | 657 | 657 | - | - | --- | 658 | //| X418:"418:xpc10" | 1318 | hwm=0.0.0 | 658 | 658 | - | - | --- | 659 | //| X419:"419:xpc10" | 1319 | hwm=0.0.0 | 659 | 659 | - | - | --- | 660 | //| X420:"420:xpc10" | 1320 | hwm=0.1.0 | 660 | 661 | 661 | 661 | --- | 662 | //| X421:"421:xpc10" | 1321 | hwm=0.0.0 | 662 | 662 | - | - | --- | 663 | //| X422:"422:xpc10" | 1322 | hwm=0.1.0 | 663 | 664 | 664 | 664 | --- | 665 | //| X423:"423:xpc10" | 1323 | hwm=0.0.0 | 665 | 665 | - | - | --- | 666 | //| X424:"424:xpc10" | 1324 | hwm=0.1.0 | 666 | 667 | 667 | 667 | --- | 668 | //| X425:"425:xpc10" | 1325 | hwm=0.0.0 | 668 | 668 | - | - | --- | 669 | //| X426:"426:xpc10" | 1326 | hwm=0.1.0 | 669 | 670 | 670 | 670 | --- | 671 | //| X427:"427:xpc10" | 1327 | hwm=0.0.0 | 671 | 671 | - | - | --- | 672 | //| X428:"428:xpc10" | 1328 | hwm=0.1.0 | 672 | 673 | 673 | 673 | --- | 674 | //| X429:"429:xpc10" | 1329 | hwm=0.0.0 | 674 | 674 | - | - | --- | 675 | //| X430:"430:xpc10" | 1330 | hwm=0.1.0 | 675 | 676 | 676 | 676 | --- | 677 | //| X431:"431:xpc10" | 1331 | hwm=0.0.0 | 677 | 677 | - | - | --- | 678 | //| X432:"432:xpc10" | 1332 | hwm=0.1.0 | 678 | 679 | 679 | 679 | --- | 680 | //| X433:"433:xpc10" | 1333 | hwm=0.0.0 | 680 | 680 | - | - | --- | 681 | //| X434:"434:xpc10" | 1334 | hwm=0.1.0 | 681 | 682 | 682 | 682 | --- | 683 | //| X435:"435:xpc10" | 1335 | hwm=0.0.0 | 683 | 683 | - | - | --- | 684 | //| X436:"436:xpc10" | 1336 | hwm=0.0.0 | 684 | 684 | - | - | --- | 685 | //| X437:"437:xpc10" | 1337 | hwm=0.0.0 | 685 | 685 | - | - | --- | 686 | //| X438:"438:xpc10" | 1339 | hwm=0.0.0 | 686 | 686 | - | - | --- | 987 | //| X438:"438:xpc10" | 1338 | hwm=0.0.0 | 686 | 686 | - | - | --- | 687 | //| X439:"439:xpc10" | 1340 | hwm=0.0.0 | 687 | 687 | - | - | --- | 688 | //| X440:"440:xpc10" | 1342 | hwm=0.0.1 | 688 | 688 | 689 | 689 | --- | 984 | //| X440:"440:xpc10" | 1341 | hwm=0.0.0 | 688 | 688 | - | - | --- | 690 | //| X441:"441:xpc10" | 1344 | hwm=0.0.0 | 690 | 690 | - | - | --- | 934 | //| X441:"441:xpc10" | 1343 | hwm=0.0.0 | 690 | 690 | - | - | --- | 691 | //| X442:"442:xpc10" | 1345 | hwm=0.0.0 | 691 | 691 | - | - | --- | 692 | //| X443:"443:xpc10" | 1347 | hwm=0.0.0 | 692 | 692 | - | - | --- | 925 | //| X443:"443:xpc10" | 1346 | hwm=0.0.0 | 692 | 692 | - | - | --- | 693 | //| X444:"444:xpc10" | 1348 | hwm=0.0.0 | 693 | 693 | - | - | --- | 694 | //| X445:"445:xpc10" | 1350 | hwm=0.0.0 | 694 | 694 | - | - | --- | 916 | //| X445:"445:xpc10" | 1349 | hwm=0.0.0 | 694 | 694 | - | - | --- | 695 | //| X446:"446:xpc10" | 1351 | hwm=0.0.0 | 695 | 695 | - | - | --- | 696 | //| X447:"447:xpc10" | 1353 | hwm=0.0.0 | 696 | 696 | - | - | --- | 890 | //| X447:"447:xpc10" | 1352 | hwm=0.0.0 | 696 | 696 | - | - | --- | 697 | //| X448:"448:xpc10" | 1355 | hwm=0.0.0 | 697 | 697 | - | - | --- | 881 | //| X448:"448:xpc10" | 1354 | hwm=0.0.0 | 697 | 697 | - | - | --- | 698 | //| X449:"449:xpc10" | 1356 | hwm=0.0.0 | 698 | 698 | - | - | --- | 699 | //| X450:"450:xpc10" | 1357 | hwm=0.0.0 | 699 | 699 | - | - | --- | 700 | //| X451:"451:xpc10" | 1359 | hwm=0.0.0 | 700 | 700 | - | - | --- | 702 | //| X451:"451:xpc10" | 1358 | hwm=0.0.0 | 700 | 700 | - | - | --- | 701 | //| X452:"452:xpc10" | 1360 | hwm=0.0.0 | 701 | 701 | - | - | --- | 701 | //| X453:"453:xpc10" | 1361 | hwm=0.0.0 | 702 | 702 | - | - | --- | 703 | //| X454:"454:xpc10" | 1363 | hwm=0.13.1 | 703 | 717 | 705 | 718 | --- | 864 | //| X454:"454:xpc10" | 1362 | hwm=0.0.1 | 703 | 703 | 704 | 704 | --- | 719 | //| X455:"455:xpc10" | 1364 | hwm=0.0.0 | 719 | 719 | - | - | --- | 720 | //| X456:"456:xpc10" | 1366 | hwm=0.2.0 | 720 | 724 | 723 | 724 | --- | 858 | //| X456:"456:xpc10" | 1365 | hwm=0.1.1 | 720 | 721 | 721 | 722 | --- | 725 | //| X457:"457:xpc10" | 1367 | hwm=0.0.0 | 725 | 725 | - | - | --- | 726 | //| X458:"458:xpc10" | 1369 | hwm=0.0.0 | 726 | 726 | - | - | --- | 824 | //| X458:"458:xpc10" | 1368 | hwm=0.0.0 | 726 | 726 | - | - | --- | 727 | //| X459:"459:xpc10" | 1370 | hwm=0.0.0 | 727 | 727 | - | - | --- | 728 | //| X460:"460:xpc10" | 1371 | hwm=0.0.0 | 728 | 728 | - | - | --- | 729 | //| X461:"461:xpc10" | 1373 | hwm=0.1.0 | 729 | 730 | 730 | 730 | --- | 821 | //| X461:"461:xpc10" | 1372 | hwm=0.0.0 | 729 | 729 | - | - | --- | 731 | //| X462:"462:xpc10" | 1374 | hwm=0.0.0 | 731 | 731 | - | - | --- | 732 | //| X463:"463:xpc10" | 1376 | hwm=0.0.0 | 732 | 732 | - | - | --- | 775 | //| X463:"463:xpc10" | 1375 | hwm=0.0.0 | 732 | 732 | - | - | --- | 733 | //| X464:"464:xpc10" | 1377 | hwm=0.0.0 | 733 | 733 | - | - | --- | 734 | //| X465:"465:xpc10" | 1378 | hwm=0.0.0 | 734 | 734 | - | - | --- | 735 | //| X466:"466:xpc10" | 1380 | hwm=0.1.0 | 735 | 736 | 736 | 736 | --- | 772 | //| X466:"466:xpc10" | 1379 | hwm=0.0.0 | 735 | 735 | - | - | --- | 737 | //| X467:"467:xpc10" | 1381 | hwm=0.0.0 | 737 | 737 | - | - | --- | 738 | //| X468:"468:xpc10" | 1382 | hwm=0.0.0 | 738 | 738 | - | - | --- | 739 | //| X469:"469:xpc10" | 1384 | hwm=0.0.0 | 739 | 739 | - | - | --- | 748 | //| X469:"469:xpc10" | 1383 | hwm=0.0.0 | 739 | 739 | - | - | --- | 740 | //| X470:"470:xpc10" | 1385 | hwm=0.0.0 | 740 | 740 | - | - | --- | 741 | //| X471:"471:xpc10" | 1387 | hwm=0.1.0 | 741 | 742 | 742 | 742 | --- | 745 | //| X471:"471:xpc10" | 1386 | hwm=0.0.0 | 741 | 741 | - | - | --- | 743 | //| X472:"472:xpc10" | 1388 | hwm=0.0.0 | 743 | 743 | - | - | --- | 744 | //| X473:"473:xpc10" | 1390 | hwm=0.0.0 | 744 | 744 | - | - | --- | 702 | //| X473:"473:xpc10" | 1389 | hwm=0.0.0 | 744 | 744 | - | - | --- | 701 | //| X474:"474:xpc10" | 1391 | hwm=0.0.0 | 745 | 745 | - | - | --- | 746 | //| X475:"475:xpc10" | 1393 | hwm=0.1.0 | 746 | 747 | 747 | 747 | --- | 745 | //| X475:"475:xpc10" | 1392 | hwm=0.0.0 | 746 | 746 | - | - | --- | 743 | //| X476:"476:xpc10" | 1394 | hwm=0.0.0 | 748 | 748 | - | - | --- | 749 | //| X477:"477:xpc10" | 1396 | hwm=0.8.0 | 749 | 758 | 751 | 758 | --- | 761 | //| X477:"477:xpc10" | 1395 | hwm=0.0.1 | 749 | 749 | 750 | 750 | --- | 759 | //| X478:"478:xpc10" | 1397 | hwm=0.0.0 | 759 | 759 | - | - | --- | 760 | //| X479:"479:xpc10" | 1399 | hwm=0.0.0 | 760 | 760 | - | - | --- | 748 | //| X479:"479:xpc10" | 1398 | hwm=0.0.0 | 760 | 760 | - | - | --- | 740 | //| X480:"480:xpc10" | 1400 | hwm=0.0.0 | 761 | 761 | - | - | --- | 762 | //| X481:"481:xpc10" | 1402 | hwm=0.8.0 | 762 | 771 | 764 | 771 | --- | 761 | //| X481:"481:xpc10" | 1401 | hwm=0.0.1 | 762 | 762 | 763 | 763 | --- | 759 | //| X482:"482:xpc10" | 1403 | hwm=0.0.0 | 772 | 772 | - | - | --- | 773 | //| X483:"483:xpc10" | 1405 | hwm=0.1.0 | 773 | 774 | 774 | 774 | --- | 772 | //| X483:"483:xpc10" | 1404 | hwm=0.0.0 | 773 | 773 | - | - | --- | 737 | //| X484:"484:xpc10" | 1406 | hwm=0.0.0 | 775 | 775 | - | - | --- | 776 | //| X485:"485:xpc10" | 1408 | hwm=0.9.0 | 776 | 796 | 788 | 796 | --- | 799 | //| X485:"485:xpc10" | 1407 | hwm=0.10.1 | 776 | 786 | 777 | 787 | --- | 797 | //| X486:"486:xpc10" | 1409 | hwm=0.0.0 | 797 | 797 | - | - | --- | 798 | //| X487:"487:xpc10" | 1411 | hwm=0.0.0 | 798 | 798 | - | - | --- | 775 | //| X487:"487:xpc10" | 1410 | hwm=0.0.0 | 798 | 798 | - | - | --- | 733 | //| X488:"488:xpc10" | 1412 | hwm=0.0.0 | 799 | 799 | - | - | --- | 800 | //| X489:"489:xpc10" | 1414 | hwm=0.9.0 | 800 | 820 | 812 | 820 | --- | 799 | //| X489:"489:xpc10" | 1413 | hwm=0.10.1 | 800 | 810 | 801 | 811 | --- | 797 | //| X490:"490:xpc10" | 1415 | hwm=0.0.0 | 821 | 821 | - | - | --- | 822 | //| X491:"491:xpc10" | 1417 | hwm=0.1.0 | 822 | 823 | 823 | 823 | --- | 821 | //| X491:"491:xpc10" | 1416 | hwm=0.0.0 | 822 | 822 | - | - | --- | 731 | //| X492:"492:xpc10" | 1418 | hwm=0.0.0 | 824 | 824 | - | - | --- | 825 | //| X493:"493:xpc10" | 1420 | hwm=0.8.0 | 825 | 839 | 832 | 839 | --- | 842 | //| X493:"493:xpc10" | 1419 | hwm=0.5.1 | 825 | 830 | 826 | 831 | --- | 840 | //| X494:"494:xpc10" | 1421 | hwm=0.0.0 | 840 | 840 | - | - | --- | 841 | //| X495:"495:xpc10" | 1423 | hwm=0.0.0 | 841 | 841 | - | - | --- | 824 | //| X495:"495:xpc10" | 1422 | hwm=0.0.0 | 841 | 841 | - | - | --- | 727 | //| X496:"496:xpc10" | 1424 | hwm=0.0.0 | 842 | 842 | - | - | --- | 843 | //| X497:"497:xpc10" | 1426 | hwm=0.8.0 | 843 | 857 | 850 | 857 | --- | 842 | //| X497:"497:xpc10" | 1425 | hwm=0.5.1 | 843 | 848 | 844 | 849 | --- | 840 | //| X498:"498:xpc10" | 1427 | hwm=0.0.0 | 858 | 858 | - | - | --- | 859 | //| X499:"499:xpc10" | 1429 | hwm=0.2.0 | 859 | 863 | 862 | 863 | --- | 858 | //| X499:"499:xpc10" | 1428 | hwm=0.1.1 | 859 | 860 | 860 | 861 | --- | 725 | //| X500:"500:xpc10" | 1430 | hwm=0.0.0 | 864 | 864 | - | - | --- | 865 | //| X501:"501:xpc10" | 1432 | hwm=0.13.1 | 865 | 879 | 867 | 880 | --- | 864 | //| X501:"501:xpc10" | 1431 | hwm=0.0.1 | 865 | 865 | 866 | 866 | --- | 719 | //| X502:"502:xpc10" | 1433 | hwm=0.0.0 | 881 | 881 | - | - | --- | 882 | //| X503:"503:xpc10" | 1435 | hwm=0.1.0 | 882 | 883 | 883 | 883 | --- | 887 | //| X503:"503:xpc10" | 1434 | hwm=0.0.0 | 882 | 882 | - | - | --- | 884 | //| X504:"504:xpc10" | 1436 | hwm=0.0.0 | 884 | 884 | - | - | --- | 885 | //| X505:"505:xpc10" | 1437 | hwm=0.0.0 | 885 | 885 | - | - | --- | 886 | //| X506:"506:xpc10" | 1439 | hwm=0.0.0 | 886 | 886 | - | - | --- | 881 | //| X506:"506:xpc10" | 1438 | hwm=0.0.0 | 886 | 886 | - | - | --- | 698 | //| X507:"507:xpc10" | 1440 | hwm=0.0.0 | 887 | 887 | - | - | --- | 888 | //| X508:"508:xpc10" | 1442 | hwm=0.1.0 | 888 | 889 | 889 | 889 | --- | 887 | //| X508:"508:xpc10" | 1441 | hwm=0.0.0 | 888 | 888 | - | - | --- | 884 | //| X509:"509:xpc10" | 1444 | hwm=0.0.0 | 890 | 890 | - | - | --- | 892 | //| X509:"509:xpc10" | 1443 | hwm=0.0.0 | 890 | 890 | - | - | --- | 891 | //| X510:"510:xpc10" | 1446 | hwm=0.0.0 | 891 | 891 | - | - | --- | 890 | //| X510:"510:xpc10" | 1445 | hwm=0.0.0 | 891 | 891 | - | - | --- | 697 | //| X511:"511:xpc10" | 1447 | hwm=0.0.0 | 892 | 892 | - | - | --- | 893 | //| X512:"512:xpc10" | 1449 | hwm=0.8.0 | 893 | 902 | 895 | 902 | --- | 905 | //| X512:"512:xpc10" | 1448 | hwm=0.0.1 | 893 | 893 | 894 | 894 | --- | 903 | //| X513:"513:xpc10" | 1450 | hwm=0.0.0 | 903 | 903 | - | - | --- | 904 | //| X514:"514:xpc10" | 1452 | hwm=0.0.0 | 904 | 904 | - | - | --- | 892 | //| X514:"514:xpc10" | 1451 | hwm=0.0.0 | 904 | 904 | - | - | --- | 891 | //| X515:"515:xpc10" | 1453 | hwm=0.0.0 | 905 | 905 | - | - | --- | 906 | //| X516:"516:xpc10" | 1455 | hwm=0.8.0 | 906 | 915 | 908 | 915 | --- | 905 | //| X516:"516:xpc10" | 1454 | hwm=0.0.1 | 906 | 906 | 907 | 907 | --- | 903 | //| X517:"517:xpc10" | 1456 | hwm=0.0.0 | 916 | 916 | - | - | --- | 917 | //| X518:"518:xpc10" | 1458 | hwm=0.1.0 | 917 | 918 | 918 | 918 | --- | 922 | //| X518:"518:xpc10" | 1457 | hwm=0.0.0 | 917 | 917 | - | - | --- | 919 | //| X519:"519:xpc10" | 1459 | hwm=0.0.0 | 919 | 919 | - | - | --- | 920 | //| X520:"520:xpc10" | 1460 | hwm=0.0.0 | 920 | 920 | - | - | --- | 921 | //| X521:"521:xpc10" | 1462 | hwm=0.0.0 | 921 | 921 | - | - | --- | 916 | //| X521:"521:xpc10" | 1461 | hwm=0.0.0 | 921 | 921 | - | - | --- | 695 | //| X522:"522:xpc10" | 1463 | hwm=0.0.0 | 922 | 922 | - | - | --- | 923 | //| X523:"523:xpc10" | 1465 | hwm=0.1.0 | 923 | 924 | 924 | 924 | --- | 922 | //| X523:"523:xpc10" | 1464 | hwm=0.0.0 | 923 | 923 | - | - | --- | 919 | //| X524:"524:xpc10" | 1466 | hwm=0.0.0 | 925 | 925 | - | - | --- | 926 | //| X525:"525:xpc10" | 1468 | hwm=0.1.0 | 926 | 927 | 927 | 927 | --- | 931 | //| X525:"525:xpc10" | 1467 | hwm=0.0.0 | 926 | 926 | - | - | --- | 928 | //| X526:"526:xpc10" | 1469 | hwm=0.0.0 | 928 | 928 | - | - | --- | 929 | //| X527:"527:xpc10" | 1470 | hwm=0.0.0 | 929 | 929 | - | - | --- | 930 | //| X528:"528:xpc10" | 1472 | hwm=0.0.0 | 930 | 930 | - | - | --- | 925 | //| X528:"528:xpc10" | 1471 | hwm=0.0.0 | 930 | 930 | - | - | --- | 693 | //| X529:"529:xpc10" | 1473 | hwm=0.0.0 | 931 | 931 | - | - | --- | 932 | //| X530:"530:xpc10" | 1475 | hwm=0.1.0 | 932 | 933 | 933 | 933 | --- | 931 | //| X530:"530:xpc10" | 1474 | hwm=0.0.0 | 932 | 932 | - | - | --- | 928 | //| X531:"531:xpc10" | 1477 | hwm=0.0.1 | 934 | 934 | 935 | 935 | --- | 981 | //| X531:"531:xpc10" | 1476 | hwm=0.0.0 | 934 | 934 | - | - | --- | 936 | //| X532:"532:xpc10" | 1479 | hwm=0.7.0 | 936 | 943 | 937 | 943 | --- | 945 | //| X532:"532:xpc10" | 1478 | hwm=0.0.0 | 936 | 936 | - | - | --- | 944 | //| X533:"533:xpc10" | 1481 | hwm=0.0.0 | 944 | 944 | - | - | --- | 934 | //| X533:"533:xpc10" | 1480 | hwm=0.0.0 | 944 | 944 | - | - | --- | 691 | //| X534:"534:xpc10" | 1482 | hwm=0.0.1 | 945 | 945 | 946 | 946 | --- | 947 | //| X535:"535:xpc10" | 1483 | hwm=0.0.1 | 947 | 947 | 948 | 948 | --- | 949 | //| X536:"536:xpc10" | 1484 | hwm=0.0.0 | 949 | 949 | - | - | --- | 950 | //| X537:"537:xpc10" | 1486 | hwm=0.9.1 | 950 | 959 | 951 | 960 | --- | 969 | //| X537:"537:xpc10" | 1485 | hwm=0.0.0 | 950 | 950 | - | - | --- | 961 | //| X538:"538:xpc10" | 1488 | hwm=0.7.0 | 961 | 968 | 962 | 968 | --- | 945 | //| X538:"538:xpc10" | 1487 | hwm=0.0.0 | 961 | 961 | - | - | --- | 944 | //| X539:"539:xpc10" | 1489 | hwm=0.0.0 | 969 | 969 | - | - | --- | 970 | //| X540:"540:xpc10" | 1491 | hwm=0.9.1 | 970 | 979 | 971 | 980 | --- | 969 | //| X540:"540:xpc10" | 1490 | hwm=0.0.0 | 970 | 970 | - | - | --- | 961 | //| X541:"541:xpc10" | 1492 | hwm=0.0.0 | 981 | 981 | - | - | --- | 982 | //| X542:"542:xpc10" | 1494 | hwm=0.0.1 | 982 | 982 | 983 | 983 | --- | 981 | //| X542:"542:xpc10" | 1493 | hwm=0.0.0 | 982 | 982 | - | - | --- | 936 | //| X543:"543:xpc10" | 1495 | hwm=0.0.0 | 984 | 984 | - | - | --- | 985 | //| X544:"544:xpc10" | 1497 | hwm=0.0.1 | 985 | 985 | 986 | 986 | --- | 984 | //| X544:"544:xpc10" | 1496 | hwm=0.0.0 | 985 | 985 | - | - | --- | 690 | //| X545:"545:xpc10" | 1498 | hwm=0.0.0 | 987 | 987 | - | - | --- | 988 | //| X546:"546:xpc10" | 1500 | hwm=0.1.0 | 988 | 989 | 989 | 989 | --- | 991 | //| X546:"546:xpc10" | 1499 | hwm=0.0.0 | 988 | 988 | - | - | --- | 990 | //| X547:"547:xpc10" | 1501 | hwm=0.0.0 | 990 | 990 | - | - | --- | 685 | //| X548:"548:xpc10" | 1502 | hwm=0.0.0 | 991 | 991 | - | - | --- | 992 | //| X549:"549:xpc10" | 1504 | hwm=0.1.0 | 992 | 993 | 993 | 993 | --- | 991 | //| X549:"549:xpc10" | 1503 | hwm=0.0.0 | 992 | 992 | - | - | --- | 990 | //*--------------------+------+--------------+------+------+-------+-----+-------------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X0:"0:xpc10" 900 : major_start_pcl=0 edge_private_start/end=-1/-1 exec=0 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X0:"0:xpc10" //res2: Thread=xpc10 state=X0:"0:xpc10" //*-----+-----+---------+------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------* //| 0 | - | R0 CTRL | | //| 0 | 900 | R0 DATA | | //| 0+E | 900 | W0 DATA | | //*-----+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X1:"1:xpc10" 901 : major_start_pcl=1 edge_private_start/end=-1/-1 exec=1 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X1:"1:xpc10" //res2: Thread=xpc10 state=X1:"1:xpc10" //*-----+-----+---------+------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------* //| 1 | - | R0 CTRL | | //| 1 | 901 | R0 DATA | | //| 1+E | 901 | W0 DATA | | //*-----+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X2:"2:xpc10" 902 : major_start_pcl=2 edge_private_start/end=-1/-1 exec=2 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X2:"2:xpc10" //res2: Thread=xpc10 state=X2:"2:xpc10" //*-----+-----+---------+------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------* //| 2 | - | R0 CTRL | | //| 2 | 902 | R0 DATA | | //| 2+E | 902 | W0 DATA | | //*-----+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X3:"3:xpc10" 903 : major_start_pcl=3 edge_private_start/end=-1/-1 exec=3 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X3:"3:xpc10" //res2: Thread=xpc10 state=X3:"3:xpc10" //*-----+-----+---------+------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------* //| 3 | - | R0 CTRL | | //| 3 | 903 | R0 DATA | | //| 3+E | 903 | W0 DATA | | //*-----+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X4:"4:xpc10" 904 : major_start_pcl=4 edge_private_start/end=-1/-1 exec=4 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X4:"4:xpc10" //res2: Thread=xpc10 state=X4:"4:xpc10" //*-----+-----+---------+------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------* //| 4 | - | R0 CTRL | | //| 4 | 904 | R0 DATA | | //| 4+E | 904 | W0 DATA | | //*-----+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X5:"5:xpc10" 905 : major_start_pcl=5 edge_private_start/end=-1/-1 exec=5 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X5:"5:xpc10" //res2: Thread=xpc10 state=X5:"5:xpc10" //*-----+-----+---------+------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------* //| 5 | - | R0 CTRL | | //| 5 | 905 | R0 DATA | | //| 5+E | 905 | W0 DATA | | //*-----+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X6:"6:xpc10" 906 : major_start_pcl=6 edge_private_start/end=-1/-1 exec=6 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X6:"6:xpc10" //res2: Thread=xpc10 state=X6:"6:xpc10" //*-----+-----+---------+------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------* //| 6 | - | R0 CTRL | | //| 6 | 906 | R0 DATA | | //| 6+E | 906 | W0 DATA | | //*-----+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X7:"7:xpc10" 907 : major_start_pcl=7 edge_private_start/end=-1/-1 exec=7 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X7:"7:xpc10" //res2: Thread=xpc10 state=X7:"7:xpc10" //*-----+-----+---------+------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------* //| 7 | - | R0 CTRL | | //| 7 | 907 | R0 DATA | | //| 7+E | 907 | W0 DATA | | //*-----+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8:"8:xpc10" 908 : major_start_pcl=8 edge_private_start/end=-1/-1 exec=8 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X8:"8:xpc10" //res2: Thread=xpc10 state=X8:"8:xpc10" //*-----+-----+---------+------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------* //| 8 | - | R0 CTRL | | //| 8 | 908 | R0 DATA | | //| 8+E | 908 | W0 DATA | | //*-----+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X9:"9:xpc10" 909 : major_start_pcl=9 edge_private_start/end=-1/-1 exec=9 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X9:"9:xpc10" //res2: Thread=xpc10 state=X9:"9:xpc10" //*-----+-----+---------+------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------* //| 9 | - | R0 CTRL | | //| 9 | 909 | R0 DATA | | //| 9+E | 909 | W0 DATA | | //*-----+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X10:"10:xpc10" 910 : major_start_pcl=10 edge_private_start/end=-1/-1 exec=10 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X10:"10:xpc10" //res2: Thread=xpc10 state=X10:"10:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 10 | - | R0 CTRL | | //| 10 | 910 | R0 DATA | | //| 10+E | 910 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X11:"11:xpc10" 911 : major_start_pcl=11 edge_private_start/end=-1/-1 exec=11 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X11:"11:xpc10" //res2: Thread=xpc10 state=X11:"11:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 11 | - | R0 CTRL | | //| 11 | 911 | R0 DATA | | //| 11+E | 911 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X12:"12:xpc10" 912 : major_start_pcl=12 edge_private_start/end=-1/-1 exec=12 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X12:"12:xpc10" //res2: Thread=xpc10 state=X12:"12:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 12 | - | R0 CTRL | | //| 12 | 912 | R0 DATA | | //| 12+E | 912 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X13:"13:xpc10" 913 : major_start_pcl=13 edge_private_start/end=-1/-1 exec=13 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X13:"13:xpc10" //res2: Thread=xpc10 state=X13:"13:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 13 | - | R0 CTRL | | //| 13 | 913 | R0 DATA | | //| 13+E | 913 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X14:"14:xpc10" 914 : major_start_pcl=14 edge_private_start/end=-1/-1 exec=14 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X14:"14:xpc10" //res2: Thread=xpc10 state=X14:"14:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 14 | - | R0 CTRL | | //| 14 | 914 | R0 DATA | | //| 14+E | 914 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X15:"15:xpc10" 915 : major_start_pcl=15 edge_private_start/end=-1/-1 exec=15 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X15:"15:xpc10" //res2: Thread=xpc10 state=X15:"15:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 15 | - | R0 CTRL | | //| 15 | 915 | R0 DATA | | //| 15+E | 915 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X16:"16:xpc10" 916 : major_start_pcl=16 edge_private_start/end=-1/-1 exec=16 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X16:"16:xpc10" //res2: Thread=xpc10 state=X16:"16:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 16 | - | R0 CTRL | | //| 16 | 916 | R0 DATA | | //| 16+E | 916 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X17:"17:xpc10" 917 : major_start_pcl=17 edge_private_start/end=-1/-1 exec=17 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X17:"17:xpc10" //res2: Thread=xpc10 state=X17:"17:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 17 | - | R0 CTRL | | //| 17 | 917 | R0 DATA | | //| 17+E | 917 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X18:"18:xpc10" 918 : major_start_pcl=18 edge_private_start/end=-1/-1 exec=18 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X18:"18:xpc10" //res2: Thread=xpc10 state=X18:"18:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 18 | - | R0 CTRL | | //| 18 | 918 | R0 DATA | | //| 18+E | 918 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X19:"19:xpc10" 919 : major_start_pcl=19 edge_private_start/end=-1/-1 exec=19 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X19:"19:xpc10" //res2: Thread=xpc10 state=X19:"19:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 19 | - | R0 CTRL | | //| 19 | 919 | R0 DATA | | //| 19+E | 919 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X20:"20:xpc10" 920 : major_start_pcl=20 edge_private_start/end=-1/-1 exec=20 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X20:"20:xpc10" //res2: Thread=xpc10 state=X20:"20:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 20 | - | R0 CTRL | | //| 20 | 920 | R0 DATA | | //| 20+E | 920 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X21:"21:xpc10" 921 : major_start_pcl=21 edge_private_start/end=-1/-1 exec=21 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X21:"21:xpc10" //res2: Thread=xpc10 state=X21:"21:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 21 | - | R0 CTRL | | //| 21 | 921 | R0 DATA | | //| 21+E | 921 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X22:"22:xpc10" 922 : major_start_pcl=22 edge_private_start/end=-1/-1 exec=22 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X22:"22:xpc10" //res2: Thread=xpc10 state=X22:"22:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 22 | - | R0 CTRL | | //| 22 | 922 | R0 DATA | | //| 22+E | 922 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X23:"23:xpc10" 923 : major_start_pcl=23 edge_private_start/end=-1/-1 exec=23 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X23:"23:xpc10" //res2: Thread=xpc10 state=X23:"23:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 23 | - | R0 CTRL | | //| 23 | 923 | R0 DATA | | //| 23+E | 923 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X24:"24:xpc10" 924 : major_start_pcl=24 edge_private_start/end=-1/-1 exec=24 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X24:"24:xpc10" //res2: Thread=xpc10 state=X24:"24:xpc10" //*------+-----+---------+------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+------------------------------* //| 24 | - | R0 CTRL | | //| 24 | 924 | R0 DATA | | //| 24+E | 924 | W0 DATA | PLI:Kiwi Demo - L/U deco... | //*------+-----+---------+------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X25:"25:xpc10" 925 : major_start_pcl=25 edge_private_start/end=-1/-1 exec=25 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X25:"25:xpc10" //res2: Thread=xpc10 state=X25:"25:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 25 | - | R0 CTRL | | //| 25 | 925 | R0 DATA | | //| 25+E | 925 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X26:"26:xpc10" 926 : major_start_pcl=26 edge_private_start/end=-1/-1 exec=26 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X26:"26:xpc10" //res2: Thread=xpc10 state=X26:"26:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 26 | - | R0 CTRL | | //| 26 | 926 | R0 DATA | | //| 26+E | 926 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X27:"27:xpc10" 927 : major_start_pcl=27 edge_private_start/end=-1/-1 exec=27 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X27:"27:xpc10" //res2: Thread=xpc10 state=X27:"27:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 27 | - | R0 CTRL | | //| 27 | 927 | R0 DATA | | //| 27+E | 927 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X28:"28:xpc10" 928 : major_start_pcl=28 edge_private_start/end=-1/-1 exec=28 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X28:"28:xpc10" //res2: Thread=xpc10 state=X28:"28:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 28 | - | R0 CTRL | | //| 28 | 928 | R0 DATA | | //| 28+E | 928 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X29:"29:xpc10" 929 : major_start_pcl=29 edge_private_start/end=-1/-1 exec=29 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X29:"29:xpc10" //res2: Thread=xpc10 state=X29:"29:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 29 | - | R0 CTRL | | //| 29 | 929 | R0 DATA | | //| 29+E | 929 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X30:"30:xpc10" 930 : major_start_pcl=30 edge_private_start/end=-1/-1 exec=30 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X30:"30:xpc10" //res2: Thread=xpc10 state=X30:"30:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 30 | - | R0 CTRL | | //| 30 | 930 | R0 DATA | | //| 30+E | 930 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X31:"31:xpc10" 931 : major_start_pcl=31 edge_private_start/end=-1/-1 exec=31 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X31:"31:xpc10" //res2: Thread=xpc10 state=X31:"31:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 31 | - | R0 CTRL | | //| 31 | 931 | R0 DATA | | //| 31+E | 931 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X32:"32:xpc10" 932 : major_start_pcl=32 edge_private_start/end=-1/-1 exec=32 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X32:"32:xpc10" //res2: Thread=xpc10 state=X32:"32:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 32 | - | R0 CTRL | | //| 32 | 932 | R0 DATA | | //| 32+E | 932 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X33:"33:xpc10" 933 : major_start_pcl=33 edge_private_start/end=-1/-1 exec=33 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X33:"33:xpc10" //res2: Thread=xpc10 state=X33:"33:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 33 | - | R0 CTRL | | //| 33 | 933 | R0 DATA | | //| 33+E | 933 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X34:"34:xpc10" 934 : major_start_pcl=34 edge_private_start/end=-1/-1 exec=34 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X34:"34:xpc10" //res2: Thread=xpc10 state=X34:"34:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 34 | - | R0 CTRL | | //| 34 | 934 | R0 DATA | | //| 34+E | 934 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X35:"35:xpc10" 935 : major_start_pcl=35 edge_private_start/end=-1/-1 exec=35 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X35:"35:xpc10" //res2: Thread=xpc10 state=X35:"35:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 35 | - | R0 CTRL | | //| 35 | 935 | R0 DATA | | //| 35+E | 935 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X36:"36:xpc10" 936 : major_start_pcl=36 edge_private_start/end=-1/-1 exec=36 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X36:"36:xpc10" //res2: Thread=xpc10 state=X36:"36:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 36 | - | R0 CTRL | | //| 36 | 936 | R0 DATA | | //| 36+E | 936 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X37:"37:xpc10" 937 : major_start_pcl=37 edge_private_start/end=-1/-1 exec=37 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X37:"37:xpc10" //res2: Thread=xpc10 state=X37:"37:xpc10" //*------+-----+---------+---------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------------------* //| 37 | - | R0 CTRL | | //| 37 | 937 | R0 DATA | | //| 37+E | 937 | W0 DATA | TMm1.V_1_GP te=te:37 scalarw(10) W/P:Start | //*------+-----+---------+---------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X38:"38:xpc10" 938 : major_start_pcl=38 edge_private_start/end=-1/-1 exec=38 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X38:"38:xpc10" //res2: Thread=xpc10 state=X38:"38:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 38 | - | R0 CTRL | | //| 38 | 938 | R0 DATA | | //| 38+E | 938 | W0 DATA | TMm1.V_2_GP te=te:38 scalarw(0) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X39:"39:xpc10" 939 : major_start_pcl=39 edge_private_start/end=-1/-1 exec=39 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X39:"39:xpc10" //res2: Thread=xpc10 state=X39:"39:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 39 | - | R0 CTRL | | //| 39 | 939 | R0 DATA | | //| 39+E | 939 | W0 DATA | TMp1.V_0_GP te=te:39 scalarw(0) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X40:"40:xpc10" 940 : major_start_pcl=40 edge_private_start/end=41/41 exec=40 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X40:"40:xpc10" //res2: Thread=xpc10 state=X40:"40:xpc10" //*------+-----+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+----------------------------------------------* //| 40 | - | R0 CTRL | | //| 40 | 940 | R0 DATA | | //| 40+E | 940 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:40 write(0, 10) | //| 41 | 940 | W1 DATA | | //*------+-----+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X41:"41:xpc10" 941 : major_start_pcl=42 edge_private_start/end=-1/-1 exec=42 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X41:"41:xpc10" //res2: Thread=xpc10 state=X41:"41:xpc10" //*------+-----+---------+------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+------------------------------------* //| 42 | - | R0 CTRL | | //| 42 | 941 | R0 DATA | | //| 42+E | 941 | W0 DATA | TMm1.V_1_GP te=te:42 scalarw(11.0) | //*------+-----+---------+------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X42:"42:xpc10" 942 : major_start_pcl=43 edge_private_start/end=-1/-1 exec=43 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X42:"42:xpc10" //res2: Thread=xpc10 state=X42:"42:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 43 | - | R0 CTRL | | //| 43 | 942 | R0 DATA | | //| 43+E | 942 | W0 DATA | TMp1.V_0_GP te=te:43 scalarw(1) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X43:"43:xpc10" 943 : major_start_pcl=44 edge_private_start/end=45/45 exec=44 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X43:"43:xpc10" //res2: Thread=xpc10 state=X43:"43:xpc10" //*------+-----+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+------------------------------------------------* //| 44 | - | R0 CTRL | | //| 44 | 943 | R0 DATA | | //| 44+E | 943 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:44 write(1, 11.0) | //| 45 | 943 | W1 DATA | | //*------+-----+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X44:"44:xpc10" 944 : major_start_pcl=46 edge_private_start/end=-1/-1 exec=46 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X44:"44:xpc10" //res2: Thread=xpc10 state=X44:"44:xpc10" //*------+-----+---------+------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+------------------------------------* //| 46 | - | R0 CTRL | | //| 46 | 944 | R0 DATA | | //| 46+E | 944 | W0 DATA | TMm1.V_1_GP te=te:46 scalarw(12.1) | //*------+-----+---------+------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X45:"45:xpc10" 945 : major_start_pcl=47 edge_private_start/end=-1/-1 exec=47 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X45:"45:xpc10" //res2: Thread=xpc10 state=X45:"45:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 47 | - | R0 CTRL | | //| 47 | 945 | R0 DATA | | //| 47+E | 945 | W0 DATA | TMp1.V_0_GP te=te:47 scalarw(2) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X46:"46:xpc10" 946 : major_start_pcl=48 edge_private_start/end=49/49 exec=48 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X46:"46:xpc10" //res2: Thread=xpc10 state=X46:"46:xpc10" //*------+-----+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+------------------------------------------------* //| 48 | - | R0 CTRL | | //| 48 | 946 | R0 DATA | | //| 48+E | 946 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:48 write(2, 12.1) | //| 49 | 946 | W1 DATA | | //*------+-----+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X47:"47:xpc10" 947 : major_start_pcl=50 edge_private_start/end=-1/-1 exec=50 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X47:"47:xpc10" //res2: Thread=xpc10 state=X47:"47:xpc10" //*------+-----+---------+-------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------* //| 50 | - | R0 CTRL | | //| 50 | 947 | R0 DATA | | //| 50+E | 947 | W0 DATA | TMm1.V_1_GP te=te:50 scalarw(13.31) | //*------+-----+---------+-------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X48:"48:xpc10" 948 : major_start_pcl=51 edge_private_start/end=-1/-1 exec=51 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X48:"48:xpc10" //res2: Thread=xpc10 state=X48:"48:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 51 | - | R0 CTRL | | //| 51 | 948 | R0 DATA | | //| 51+E | 948 | W0 DATA | TMp1.V_0_GP te=te:51 scalarw(3) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X49:"49:xpc10" 949 : major_start_pcl=52 edge_private_start/end=53/53 exec=52 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X49:"49:xpc10" //res2: Thread=xpc10 state=X49:"49:xpc10" //*------+-----+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------------* //| 52 | - | R0 CTRL | | //| 52 | 949 | R0 DATA | | //| 52+E | 949 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:52 write(3, 13.31) | //| 53 | 949 | W1 DATA | | //*------+-----+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X50:"50:xpc10" 950 : major_start_pcl=54 edge_private_start/end=-1/-1 exec=54 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X50:"50:xpc10" //res2: Thread=xpc10 state=X50:"50:xpc10" //*------+-----+---------+--------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+--------------------------------------* //| 54 | - | R0 CTRL | | //| 54 | 950 | R0 DATA | | //| 54+E | 950 | W0 DATA | TMm1.V_1_GP te=te:54 scalarw(14.641) | //*------+-----+---------+--------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X51:"51:xpc10" 951 : major_start_pcl=55 edge_private_start/end=-1/-1 exec=55 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X51:"51:xpc10" //res2: Thread=xpc10 state=X51:"51:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 55 | - | R0 CTRL | | //| 55 | 951 | R0 DATA | | //| 55+E | 951 | W0 DATA | TMp1.V_0_GP te=te:55 scalarw(4) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X52:"52:xpc10" 952 : major_start_pcl=56 edge_private_start/end=57/57 exec=56 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X52:"52:xpc10" //res2: Thread=xpc10 state=X52:"52:xpc10" //*------+-----+---------+--------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+--------------------------------------------------* //| 56 | - | R0 CTRL | | //| 56 | 952 | R0 DATA | | //| 56+E | 952 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:56 write(4, 14.641) | //| 57 | 952 | W1 DATA | | //*------+-----+---------+--------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X53:"53:xpc10" 953 : major_start_pcl=58 edge_private_start/end=-1/-1 exec=58 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X53:"53:xpc10" //res2: Thread=xpc10 state=X53:"53:xpc10" //*------+-----+---------+---------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------------* //| 58 | - | R0 CTRL | | //| 58 | 953 | R0 DATA | | //| 58+E | 953 | W0 DATA | TMm1.V_1_GP te=te:58 scalarw(16.1051) | //*------+-----+---------+---------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X54:"54:xpc10" 954 : major_start_pcl=59 edge_private_start/end=-1/-1 exec=59 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X54:"54:xpc10" //res2: Thread=xpc10 state=X54:"54:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 59 | - | R0 CTRL | | //| 59 | 954 | R0 DATA | | //| 59+E | 954 | W0 DATA | TMp1.V_0_GP te=te:59 scalarw(5) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X55:"55:xpc10" 955 : major_start_pcl=60 edge_private_start/end=61/61 exec=60 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X55:"55:xpc10" //res2: Thread=xpc10 state=X55:"55:xpc10" //*------+-----+---------+---------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------------------------* //| 60 | - | R0 CTRL | | //| 60 | 955 | R0 DATA | | //| 60+E | 955 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:60 write(5, 16.1051) | //| 61 | 955 | W1 DATA | | //*------+-----+---------+---------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X56:"56:xpc10" 956 : major_start_pcl=62 edge_private_start/end=-1/-1 exec=62 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X56:"56:xpc10" //res2: Thread=xpc10 state=X56:"56:xpc10" //*------+-----+---------+----------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+----------------------------------------* //| 62 | - | R0 CTRL | | //| 62 | 956 | R0 DATA | | //| 62+E | 956 | W0 DATA | TMm1.V_1_GP te=te:62 scalarw(17.71561) | //*------+-----+---------+----------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X57:"57:xpc10" 957 : major_start_pcl=63 edge_private_start/end=-1/-1 exec=63 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X57:"57:xpc10" //res2: Thread=xpc10 state=X57:"57:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 63 | - | R0 CTRL | | //| 63 | 957 | R0 DATA | | //| 63+E | 957 | W0 DATA | TMp1.V_0_GP te=te:63 scalarw(6) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X58:"58:xpc10" 958 : major_start_pcl=64 edge_private_start/end=65/65 exec=64 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X58:"58:xpc10" //res2: Thread=xpc10 state=X58:"58:xpc10" //*------+-----+---------+----------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+----------------------------------------------------* //| 64 | - | R0 CTRL | | //| 64 | 958 | R0 DATA | | //| 64+E | 958 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:64 write(6, 17.71561) | //| 65 | 958 | W1 DATA | | //*------+-----+---------+----------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X59:"59:xpc10" 959 : major_start_pcl=66 edge_private_start/end=-1/-1 exec=66 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X59:"59:xpc10" //res2: Thread=xpc10 state=X59:"59:xpc10" //*------+-----+---------+-----------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-----------------------------------------* //| 66 | - | R0 CTRL | | //| 66 | 959 | R0 DATA | | //| 66+E | 959 | W0 DATA | TMm1.V_1_GP te=te:66 scalarw(19.487171) | //*------+-----+---------+-----------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X60:"60:xpc10" 960 : major_start_pcl=67 edge_private_start/end=-1/-1 exec=67 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X60:"60:xpc10" //res2: Thread=xpc10 state=X60:"60:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 67 | - | R0 CTRL | | //| 67 | 960 | R0 DATA | | //| 67+E | 960 | W0 DATA | TMp1.V_0_GP te=te:67 scalarw(7) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X61:"61:xpc10" 961 : major_start_pcl=68 edge_private_start/end=69/69 exec=68 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X61:"61:xpc10" //res2: Thread=xpc10 state=X61:"61:xpc10" //*------+-----+---------+-----------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-----------------------------------------------------* //| 68 | - | R0 CTRL | | //| 68 | 961 | R0 DATA | | //| 68+E | 961 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:68 write(7, 19.487171) | //| 69 | 961 | W1 DATA | | //*------+-----+---------+-----------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X62:"62:xpc10" 962 : major_start_pcl=70 edge_private_start/end=-1/-1 exec=70 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X62:"62:xpc10" //res2: Thread=xpc10 state=X62:"62:xpc10" //*------+-----+---------+------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+------------------------------------------* //| 70 | - | R0 CTRL | | //| 70 | 962 | R0 DATA | | //| 70+E | 962 | W0 DATA | TMm1.V_1_GP te=te:70 scalarw(21.4358881) | //*------+-----+---------+------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X63:"63:xpc10" 963 : major_start_pcl=71 edge_private_start/end=-1/-1 exec=71 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X63:"63:xpc10" //res2: Thread=xpc10 state=X63:"63:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 71 | - | R0 CTRL | | //| 71 | 963 | R0 DATA | | //| 71+E | 963 | W0 DATA | TMp1.V_0_GP te=te:71 scalarw(8) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X64:"64:xpc10" 964 : major_start_pcl=72 edge_private_start/end=-1/-1 exec=72 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X64:"64:xpc10" //res2: Thread=xpc10 state=X64:"64:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 72 | - | R0 CTRL | | //| 72 | 964 | R0 DATA | | //| 72+E | 964 | W0 DATA | TMm1.V_2_GP te=te:72 scalarw(1) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X65:"65:xpc10" 965 : major_start_pcl=73 edge_private_start/end=-1/-1 exec=73 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X65:"65:xpc10" //res2: Thread=xpc10 state=X65:"65:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 73 | - | R0 CTRL | | //| 73 | 965 | R0 DATA | | //| 73+E | 965 | W0 DATA | TMp1.V_0_GP te=te:73 scalarw(0) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X66:"66:xpc10" 966 : major_start_pcl=74 edge_private_start/end=75/75 exec=74 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X66:"66:xpc10" //res2: Thread=xpc10 state=X66:"66:xpc10" //*------+-----+---------+------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+------------------------------------------------------* //| 74 | - | R0 CTRL | | //| 74 | 966 | R0 DATA | | //| 74+E | 966 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:74 write(8, 21.4358881) | //| 75 | 966 | W1 DATA | | //*------+-----+---------+------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X67:"67:xpc10" 967 : major_start_pcl=76 edge_private_start/end=-1/-1 exec=76 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X67:"67:xpc10" //res2: Thread=xpc10 state=X67:"67:xpc10" //*------+-----+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------* //| 76 | - | R0 CTRL | | //| 76 | 967 | R0 DATA | | //| 76+E | 967 | W0 DATA | TMm1.V_1_GP te=te:76 scalarw(23.57947691) | //*------+-----+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X68:"68:xpc10" 968 : major_start_pcl=77 edge_private_start/end=-1/-1 exec=77 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X68:"68:xpc10" //res2: Thread=xpc10 state=X68:"68:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 77 | - | R0 CTRL | | //| 77 | 968 | R0 DATA | | //| 77+E | 968 | W0 DATA | TMp1.V_0_GP te=te:77 scalarw(1) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X69:"69:xpc10" 969 : major_start_pcl=78 edge_private_start/end=79/79 exec=78 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X69:"69:xpc10" //res2: Thread=xpc10 state=X69:"69:xpc10" //*------+-----+---------+-------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------------------* //| 78 | - | R0 CTRL | | //| 78 | 969 | R0 DATA | | //| 78+E | 969 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:78 write(9, 23.57947691) | //| 79 | 969 | W1 DATA | | //*------+-----+---------+-------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X70:"70:xpc10" 970 : major_start_pcl=80 edge_private_start/end=-1/-1 exec=80 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X70:"70:xpc10" //res2: Thread=xpc10 state=X70:"70:xpc10" //*------+-----+---------+------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+------------------------------------------* //| 80 | - | R0 CTRL | | //| 80 | 970 | R0 DATA | | //| 80+E | 970 | W0 DATA | TMm1.V_1_GP te=te:80 scalarw(25.9374246) | //*------+-----+---------+------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X71:"71:xpc10" 971 : major_start_pcl=81 edge_private_start/end=-1/-1 exec=81 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X71:"71:xpc10" //res2: Thread=xpc10 state=X71:"71:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 81 | - | R0 CTRL | | //| 81 | 971 | R0 DATA | | //| 81+E | 971 | W0 DATA | TMp1.V_0_GP te=te:81 scalarw(2) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X72:"72:xpc10" 972 : major_start_pcl=82 edge_private_start/end=83/83 exec=82 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X72:"72:xpc10" //res2: Thread=xpc10 state=X72:"72:xpc10" //*------+-----+---------+-------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------------------* //| 82 | - | R0 CTRL | | //| 82 | 972 | R0 DATA | | //| 82+E | 972 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:82 write(10, 25.9374246) | //| 83 | 972 | W1 DATA | | //*------+-----+---------+-------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X73:"73:xpc10" 973 : major_start_pcl=84 edge_private_start/end=-1/-1 exec=84 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X73:"73:xpc10" //res2: Thread=xpc10 state=X73:"73:xpc10" //*------+-----+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------* //| 84 | - | R0 CTRL | | //| 84 | 973 | R0 DATA | | //| 84+E | 973 | W0 DATA | TMm1.V_1_GP te=te:84 scalarw(28.53116706) | //*------+-----+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X74:"74:xpc10" 974 : major_start_pcl=85 edge_private_start/end=-1/-1 exec=85 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X74:"74:xpc10" //res2: Thread=xpc10 state=X74:"74:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 85 | - | R0 CTRL | | //| 85 | 974 | R0 DATA | | //| 85+E | 974 | W0 DATA | TMp1.V_0_GP te=te:85 scalarw(3) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X75:"75:xpc10" 975 : major_start_pcl=86 edge_private_start/end=87/87 exec=86 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X75:"75:xpc10" //res2: Thread=xpc10 state=X75:"75:xpc10" //*------+-----+---------+--------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+--------------------------------------------------------* //| 86 | - | R0 CTRL | | //| 86 | 975 | R0 DATA | | //| 86+E | 975 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:86 write(11, 28.53116706) | //| 87 | 975 | W1 DATA | | //*------+-----+---------+--------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X76:"76:xpc10" 976 : major_start_pcl=88 edge_private_start/end=-1/-1 exec=88 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X76:"76:xpc10" //res2: Thread=xpc10 state=X76:"76:xpc10" //*------+-----+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------* //| 88 | - | R0 CTRL | | //| 88 | 976 | R0 DATA | | //| 88+E | 976 | W0 DATA | TMm1.V_1_GP te=te:88 scalarw(31.38428377) | //*------+-----+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X77:"77:xpc10" 977 : major_start_pcl=89 edge_private_start/end=-1/-1 exec=89 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X77:"77:xpc10" //res2: Thread=xpc10 state=X77:"77:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 89 | - | R0 CTRL | | //| 89 | 977 | R0 DATA | | //| 89+E | 977 | W0 DATA | TMp1.V_0_GP te=te:89 scalarw(4) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X78:"78:xpc10" 978 : major_start_pcl=90 edge_private_start/end=91/91 exec=90 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X78:"78:xpc10" //res2: Thread=xpc10 state=X78:"78:xpc10" //*------+-----+---------+--------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+--------------------------------------------------------* //| 90 | - | R0 CTRL | | //| 90 | 978 | R0 DATA | | //| 90+E | 978 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:90 write(12, 31.38428377) | //| 91 | 978 | W1 DATA | | //*------+-----+---------+--------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X79:"79:xpc10" 979 : major_start_pcl=92 edge_private_start/end=-1/-1 exec=92 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X79:"79:xpc10" //res2: Thread=xpc10 state=X79:"79:xpc10" //*------+-----+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------* //| 92 | - | R0 CTRL | | //| 92 | 979 | R0 DATA | | //| 92+E | 979 | W0 DATA | TMm1.V_1_GP te=te:92 scalarw(34.52271214) | //*------+-----+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X80:"80:xpc10" 980 : major_start_pcl=93 edge_private_start/end=-1/-1 exec=93 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X80:"80:xpc10" //res2: Thread=xpc10 state=X80:"80:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 93 | - | R0 CTRL | | //| 93 | 980 | R0 DATA | | //| 93+E | 980 | W0 DATA | TMp1.V_0_GP te=te:93 scalarw(5) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X81:"81:xpc10" 981 : major_start_pcl=94 edge_private_start/end=95/95 exec=94 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X81:"81:xpc10" //res2: Thread=xpc10 state=X81:"81:xpc10" //*------+-----+---------+--------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+--------------------------------------------------------* //| 94 | - | R0 CTRL | | //| 94 | 981 | R0 DATA | | //| 94+E | 981 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:94 write(13, 34.52271214) | //| 95 | 981 | W1 DATA | | //*------+-----+---------+--------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X82:"82:xpc10" 982 : major_start_pcl=96 edge_private_start/end=-1/-1 exec=96 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X82:"82:xpc10" //res2: Thread=xpc10 state=X82:"82:xpc10" //*------+-----+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------* //| 96 | - | R0 CTRL | | //| 96 | 982 | R0 DATA | | //| 96+E | 982 | W0 DATA | TMm1.V_1_GP te=te:96 scalarw(37.97498336) | //*------+-----+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X83:"83:xpc10" 983 : major_start_pcl=97 edge_private_start/end=-1/-1 exec=97 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X83:"83:xpc10" //res2: Thread=xpc10 state=X83:"83:xpc10" //*------+-----+---------+---------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------* //| 97 | - | R0 CTRL | | //| 97 | 983 | R0 DATA | | //| 97+E | 983 | W0 DATA | TMp1.V_0_GP te=te:97 scalarw(6) | //*------+-----+---------+---------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X84:"84:xpc10" 984 : major_start_pcl=98 edge_private_start/end=99/99 exec=98 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X84:"84:xpc10" //res2: Thread=xpc10 state=X84:"84:xpc10" //*------+-----+---------+--------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+--------------------------------------------------------* //| 98 | - | R0 CTRL | | //| 98 | 984 | R0 DATA | | //| 98+E | 984 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:98 write(14, 37.97498336) | //| 99 | 984 | W1 DATA | | //*------+-----+---------+--------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X85:"85:xpc10" 985 : major_start_pcl=100 edge_private_start/end=-1/-1 exec=100 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X85:"85:xpc10" //res2: Thread=xpc10 state=X85:"85:xpc10" //*-------+-----+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+-----+---------+--------------------------------------------* //| 100 | - | R0 CTRL | | //| 100 | 985 | R0 DATA | | //| 100+E | 985 | W0 DATA | TMm1.V_1_GP te=te:100 scalarw(41.77248169) | //*-------+-----+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X86:"86:xpc10" 986 : major_start_pcl=101 edge_private_start/end=-1/-1 exec=101 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X86:"86:xpc10" //res2: Thread=xpc10 state=X86:"86:xpc10" //*-------+-----+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+-----+---------+----------------------------------* //| 101 | - | R0 CTRL | | //| 101 | 986 | R0 DATA | | //| 101+E | 986 | W0 DATA | TMp1.V_0_GP te=te:101 scalarw(7) | //*-------+-----+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X87:"87:xpc10" 987 : major_start_pcl=102 edge_private_start/end=103/103 exec=102 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X87:"87:xpc10" //res2: Thread=xpc10 state=X87:"87:xpc10" //*-------+-----+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+-----+---------+---------------------------------------------------------* //| 102 | - | R0 CTRL | | //| 102 | 987 | R0 DATA | | //| 102+E | 987 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:102 write(15, 41.77248169) | //| 103 | 987 | W1 DATA | | //*-------+-----+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X88:"88:xpc10" 988 : major_start_pcl=104 edge_private_start/end=-1/-1 exec=104 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X88:"88:xpc10" //res2: Thread=xpc10 state=X88:"88:xpc10" //*-------+-----+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+-----+---------+--------------------------------------------* //| 104 | - | R0 CTRL | | //| 104 | 988 | R0 DATA | | //| 104+E | 988 | W0 DATA | TMm1.V_1_GP te=te:104 scalarw(45.94972986) | //*-------+-----+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X89:"89:xpc10" 989 : major_start_pcl=105 edge_private_start/end=-1/-1 exec=105 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X89:"89:xpc10" //res2: Thread=xpc10 state=X89:"89:xpc10" //*-------+-----+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+-----+---------+----------------------------------* //| 105 | - | R0 CTRL | | //| 105 | 989 | R0 DATA | | //| 105+E | 989 | W0 DATA | TMp1.V_0_GP te=te:105 scalarw(8) | //*-------+-----+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X90:"90:xpc10" 990 : major_start_pcl=106 edge_private_start/end=-1/-1 exec=106 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X90:"90:xpc10" //res2: Thread=xpc10 state=X90:"90:xpc10" //*-------+-----+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+-----+---------+----------------------------------* //| 106 | - | R0 CTRL | | //| 106 | 990 | R0 DATA | | //| 106+E | 990 | W0 DATA | TMm1.V_2_GP te=te:106 scalarw(2) | //*-------+-----+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X91:"91:xpc10" 991 : major_start_pcl=107 edge_private_start/end=-1/-1 exec=107 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X91:"91:xpc10" //res2: Thread=xpc10 state=X91:"91:xpc10" //*-------+-----+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+-----+---------+----------------------------------* //| 107 | - | R0 CTRL | | //| 107 | 991 | R0 DATA | | //| 107+E | 991 | W0 DATA | TMp1.V_0_GP te=te:107 scalarw(0) | //*-------+-----+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X92:"92:xpc10" 992 : major_start_pcl=108 edge_private_start/end=109/109 exec=108 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X92:"92:xpc10" //res2: Thread=xpc10 state=X92:"92:xpc10" //*-------+-----+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+-----+---------+---------------------------------------------------------* //| 108 | - | R0 CTRL | | //| 108 | 992 | R0 DATA | | //| 108+E | 992 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:108 write(16, 45.94972986) | //| 109 | 992 | W1 DATA | | //*-------+-----+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X93:"93:xpc10" 993 : major_start_pcl=110 edge_private_start/end=-1/-1 exec=110 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X93:"93:xpc10" //res2: Thread=xpc10 state=X93:"93:xpc10" //*-------+-----+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+-----+---------+--------------------------------------------* //| 110 | - | R0 CTRL | | //| 110 | 993 | R0 DATA | | //| 110+E | 993 | W0 DATA | TMm1.V_1_GP te=te:110 scalarw(50.54470285) | //*-------+-----+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X94:"94:xpc10" 994 : major_start_pcl=111 edge_private_start/end=-1/-1 exec=111 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X94:"94:xpc10" //res2: Thread=xpc10 state=X94:"94:xpc10" //*-------+-----+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+-----+---------+----------------------------------* //| 111 | - | R0 CTRL | | //| 111 | 994 | R0 DATA | | //| 111+E | 994 | W0 DATA | TMp1.V_0_GP te=te:111 scalarw(1) | //*-------+-----+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X95:"95:xpc10" 995 : major_start_pcl=112 edge_private_start/end=113/113 exec=112 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X95:"95:xpc10" //res2: Thread=xpc10 state=X95:"95:xpc10" //*-------+-----+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+-----+---------+---------------------------------------------------------* //| 112 | - | R0 CTRL | | //| 112 | 995 | R0 DATA | | //| 112+E | 995 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:112 write(17, 50.54470285) | //| 113 | 995 | W1 DATA | | //*-------+-----+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X96:"96:xpc10" 996 : major_start_pcl=114 edge_private_start/end=-1/-1 exec=114 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X96:"96:xpc10" //res2: Thread=xpc10 state=X96:"96:xpc10" //*-------+-----+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+-----+---------+--------------------------------------------* //| 114 | - | R0 CTRL | | //| 114 | 996 | R0 DATA | | //| 114+E | 996 | W0 DATA | TMm1.V_1_GP te=te:114 scalarw(55.59917313) | //*-------+-----+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X97:"97:xpc10" 997 : major_start_pcl=115 edge_private_start/end=-1/-1 exec=115 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X97:"97:xpc10" //res2: Thread=xpc10 state=X97:"97:xpc10" //*-------+-----+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+-----+---------+----------------------------------* //| 115 | - | R0 CTRL | | //| 115 | 997 | R0 DATA | | //| 115+E | 997 | W0 DATA | TMp1.V_0_GP te=te:115 scalarw(2) | //*-------+-----+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X98:"98:xpc10" 998 : major_start_pcl=116 edge_private_start/end=117/117 exec=116 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X98:"98:xpc10" //res2: Thread=xpc10 state=X98:"98:xpc10" //*-------+-----+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+-----+---------+---------------------------------------------------------* //| 116 | - | R0 CTRL | | //| 116 | 998 | R0 DATA | | //| 116+E | 998 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:116 write(18, 55.59917313) | //| 117 | 998 | W1 DATA | | //*-------+-----+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X99:"99:xpc10" 999 : major_start_pcl=118 edge_private_start/end=-1/-1 exec=118 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X99:"99:xpc10" //res2: Thread=xpc10 state=X99:"99:xpc10" //*-------+-----+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+-----+---------+--------------------------------------------* //| 118 | - | R0 CTRL | | //| 118 | 999 | R0 DATA | | //| 118+E | 999 | W0 DATA | TMm1.V_1_GP te=te:118 scalarw(61.15909045) | //*-------+-----+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X100:"100:xpc10" 1000 : major_start_pcl=119 edge_private_start/end=-1/-1 exec=119 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X100:"100:xpc10" //res2: Thread=xpc10 state=X100:"100:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 119 | - | R0 CTRL | | //| 119 | 1000 | R0 DATA | | //| 119+E | 1000 | W0 DATA | TMp1.V_0_GP te=te:119 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X101:"101:xpc10" 1001 : major_start_pcl=120 edge_private_start/end=121/121 exec=120 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X101:"101:xpc10" //res2: Thread=xpc10 state=X101:"101:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 120 | - | R0 CTRL | | //| 120 | 1001 | R0 DATA | | //| 120+E | 1001 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:120 write(19, 61.15909045) | //| 121 | 1001 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X102:"102:xpc10" 1002 : major_start_pcl=122 edge_private_start/end=-1/-1 exec=122 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X102:"102:xpc10" //res2: Thread=xpc10 state=X102:"102:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 122 | - | R0 CTRL | | //| 122 | 1002 | R0 DATA | | //| 122+E | 1002 | W0 DATA | TMm1.V_1_GP te=te:122 scalarw(67.27499949) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X103:"103:xpc10" 1003 : major_start_pcl=123 edge_private_start/end=-1/-1 exec=123 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X103:"103:xpc10" //res2: Thread=xpc10 state=X103:"103:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 123 | - | R0 CTRL | | //| 123 | 1003 | R0 DATA | | //| 123+E | 1003 | W0 DATA | TMp1.V_0_GP te=te:123 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X104:"104:xpc10" 1004 : major_start_pcl=124 edge_private_start/end=125/125 exec=124 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X104:"104:xpc10" //res2: Thread=xpc10 state=X104:"104:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 124 | - | R0 CTRL | | //| 124 | 1004 | R0 DATA | | //| 124+E | 1004 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:124 write(20, 67.27499949) | //| 125 | 1004 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X105:"105:xpc10" 1005 : major_start_pcl=126 edge_private_start/end=-1/-1 exec=126 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X105:"105:xpc10" //res2: Thread=xpc10 state=X105:"105:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 126 | - | R0 CTRL | | //| 126 | 1005 | R0 DATA | | //| 126+E | 1005 | W0 DATA | TMm1.V_1_GP te=te:126 scalarw(74.00249944) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X106:"106:xpc10" 1006 : major_start_pcl=127 edge_private_start/end=-1/-1 exec=127 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X106:"106:xpc10" //res2: Thread=xpc10 state=X106:"106:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 127 | - | R0 CTRL | | //| 127 | 1006 | R0 DATA | | //| 127+E | 1006 | W0 DATA | TMp1.V_0_GP te=te:127 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X107:"107:xpc10" 1007 : major_start_pcl=128 edge_private_start/end=129/129 exec=128 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X107:"107:xpc10" //res2: Thread=xpc10 state=X107:"107:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 128 | - | R0 CTRL | | //| 128 | 1007 | R0 DATA | | //| 128+E | 1007 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:128 write(21, 74.00249944) | //| 129 | 1007 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X108:"108:xpc10" 1008 : major_start_pcl=130 edge_private_start/end=-1/-1 exec=130 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X108:"108:xpc10" //res2: Thread=xpc10 state=X108:"108:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 130 | - | R0 CTRL | | //| 130 | 1008 | R0 DATA | | //| 130+E | 1008 | W0 DATA | TMm1.V_1_GP te=te:130 scalarw(81.40274939) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X109:"109:xpc10" 1009 : major_start_pcl=131 edge_private_start/end=-1/-1 exec=131 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X109:"109:xpc10" //res2: Thread=xpc10 state=X109:"109:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 131 | - | R0 CTRL | | //| 131 | 1009 | R0 DATA | | //| 131+E | 1009 | W0 DATA | TMp1.V_0_GP te=te:131 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X110:"110:xpc10" 1010 : major_start_pcl=132 edge_private_start/end=133/133 exec=132 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X110:"110:xpc10" //res2: Thread=xpc10 state=X110:"110:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 132 | - | R0 CTRL | | //| 132 | 1010 | R0 DATA | | //| 132+E | 1010 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:132 write(22, 81.40274939) | //| 133 | 1010 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X111:"111:xpc10" 1011 : major_start_pcl=134 edge_private_start/end=-1/-1 exec=134 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X111:"111:xpc10" //res2: Thread=xpc10 state=X111:"111:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 134 | - | R0 CTRL | | //| 134 | 1011 | R0 DATA | | //| 134+E | 1011 | W0 DATA | TMm1.V_1_GP te=te:134 scalarw(89.54302433) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X112:"112:xpc10" 1012 : major_start_pcl=135 edge_private_start/end=-1/-1 exec=135 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X112:"112:xpc10" //res2: Thread=xpc10 state=X112:"112:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 135 | - | R0 CTRL | | //| 135 | 1012 | R0 DATA | | //| 135+E | 1012 | W0 DATA | TMp1.V_0_GP te=te:135 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X113:"113:xpc10" 1013 : major_start_pcl=136 edge_private_start/end=137/137 exec=136 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X113:"113:xpc10" //res2: Thread=xpc10 state=X113:"113:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 136 | - | R0 CTRL | | //| 136 | 1013 | R0 DATA | | //| 136+E | 1013 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:136 write(23, 89.54302433) | //| 137 | 1013 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X114:"114:xpc10" 1014 : major_start_pcl=138 edge_private_start/end=-1/-1 exec=138 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X114:"114:xpc10" //res2: Thread=xpc10 state=X114:"114:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 138 | - | R0 CTRL | | //| 138 | 1014 | R0 DATA | | //| 138+E | 1014 | W0 DATA | TMm1.V_1_GP te=te:138 scalarw(98.49732676) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X115:"115:xpc10" 1015 : major_start_pcl=139 edge_private_start/end=-1/-1 exec=139 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X115:"115:xpc10" //res2: Thread=xpc10 state=X115:"115:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 139 | - | R0 CTRL | | //| 139 | 1015 | R0 DATA | | //| 139+E | 1015 | W0 DATA | TMp1.V_0_GP te=te:139 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X116:"116:xpc10" 1016 : major_start_pcl=140 edge_private_start/end=-1/-1 exec=140 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X116:"116:xpc10" //res2: Thread=xpc10 state=X116:"116:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 140 | - | R0 CTRL | | //| 140 | 1016 | R0 DATA | | //| 140+E | 1016 | W0 DATA | TMm1.V_2_GP te=te:140 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X117:"117:xpc10" 1017 : major_start_pcl=141 edge_private_start/end=-1/-1 exec=141 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X117:"117:xpc10" //res2: Thread=xpc10 state=X117:"117:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 141 | - | R0 CTRL | | //| 141 | 1017 | R0 DATA | | //| 141+E | 1017 | W0 DATA | TMp1.V_0_GP te=te:141 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X118:"118:xpc10" 1018 : major_start_pcl=142 edge_private_start/end=143/143 exec=142 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X118:"118:xpc10" //res2: Thread=xpc10 state=X118:"118:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 142 | - | R0 CTRL | | //| 142 | 1018 | R0 DATA | | //| 142+E | 1018 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:142 write(24, 98.49732676) | //| 143 | 1018 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X119:"119:xpc10" 1019 : major_start_pcl=144 edge_private_start/end=-1/-1 exec=144 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X119:"119:xpc10" //res2: Thread=xpc10 state=X119:"119:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 144 | - | R0 CTRL | | //| 144 | 1019 | R0 DATA | | //| 144+E | 1019 | W0 DATA | TMm1.V_1_GP te=te:144 scalarw(108.3470594) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X120:"120:xpc10" 1020 : major_start_pcl=145 edge_private_start/end=-1/-1 exec=145 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X120:"120:xpc10" //res2: Thread=xpc10 state=X120:"120:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 145 | - | R0 CTRL | | //| 145 | 1020 | R0 DATA | | //| 145+E | 1020 | W0 DATA | TMp1.V_0_GP te=te:145 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X121:"121:xpc10" 1021 : major_start_pcl=146 edge_private_start/end=147/147 exec=146 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X121:"121:xpc10" //res2: Thread=xpc10 state=X121:"121:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 146 | - | R0 CTRL | | //| 146 | 1021 | R0 DATA | | //| 146+E | 1021 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:146 write(25, 108.3470594) | //| 147 | 1021 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X122:"122:xpc10" 1022 : major_start_pcl=148 edge_private_start/end=-1/-1 exec=148 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X122:"122:xpc10" //res2: Thread=xpc10 state=X122:"122:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 148 | - | R0 CTRL | | //| 148 | 1022 | R0 DATA | | //| 148+E | 1022 | W0 DATA | TMm1.V_1_GP te=te:148 scalarw(119.1817654) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X123:"123:xpc10" 1023 : major_start_pcl=149 edge_private_start/end=-1/-1 exec=149 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X123:"123:xpc10" //res2: Thread=xpc10 state=X123:"123:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 149 | - | R0 CTRL | | //| 149 | 1023 | R0 DATA | | //| 149+E | 1023 | W0 DATA | TMp1.V_0_GP te=te:149 scalarw(2) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X124:"124:xpc10" 1024 : major_start_pcl=150 edge_private_start/end=151/151 exec=150 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X124:"124:xpc10" //res2: Thread=xpc10 state=X124:"124:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 150 | - | R0 CTRL | | //| 150 | 1024 | R0 DATA | | //| 150+E | 1024 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:150 write(26, 119.1817654) | //| 151 | 1024 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X125:"125:xpc10" 1025 : major_start_pcl=152 edge_private_start/end=-1/-1 exec=152 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X125:"125:xpc10" //res2: Thread=xpc10 state=X125:"125:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 152 | - | R0 CTRL | | //| 152 | 1025 | R0 DATA | | //| 152+E | 1025 | W0 DATA | TMm1.V_1_GP te=te:152 scalarw(131.0999419) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X126:"126:xpc10" 1026 : major_start_pcl=153 edge_private_start/end=-1/-1 exec=153 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X126:"126:xpc10" //res2: Thread=xpc10 state=X126:"126:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 153 | - | R0 CTRL | | //| 153 | 1026 | R0 DATA | | //| 153+E | 1026 | W0 DATA | TMp1.V_0_GP te=te:153 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X127:"127:xpc10" 1027 : major_start_pcl=154 edge_private_start/end=155/155 exec=154 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X127:"127:xpc10" //res2: Thread=xpc10 state=X127:"127:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 154 | - | R0 CTRL | | //| 154 | 1027 | R0 DATA | | //| 154+E | 1027 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:154 write(27, 131.0999419) | //| 155 | 1027 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X128:"128:xpc10" 1028 : major_start_pcl=156 edge_private_start/end=-1/-1 exec=156 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X128:"128:xpc10" //res2: Thread=xpc10 state=X128:"128:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 156 | - | R0 CTRL | | //| 156 | 1028 | R0 DATA | | //| 156+E | 1028 | W0 DATA | TMm1.V_1_GP te=te:156 scalarw(144.2099361) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X129:"129:xpc10" 1029 : major_start_pcl=157 edge_private_start/end=-1/-1 exec=157 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X129:"129:xpc10" //res2: Thread=xpc10 state=X129:"129:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 157 | - | R0 CTRL | | //| 157 | 1029 | R0 DATA | | //| 157+E | 1029 | W0 DATA | TMp1.V_0_GP te=te:157 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X130:"130:xpc10" 1030 : major_start_pcl=158 edge_private_start/end=159/159 exec=158 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X130:"130:xpc10" //res2: Thread=xpc10 state=X130:"130:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 158 | - | R0 CTRL | | //| 158 | 1030 | R0 DATA | | //| 158+E | 1030 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:158 write(28, 144.2099361) | //| 159 | 1030 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X131:"131:xpc10" 1031 : major_start_pcl=160 edge_private_start/end=-1/-1 exec=160 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X131:"131:xpc10" //res2: Thread=xpc10 state=X131:"131:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 160 | - | R0 CTRL | | //| 160 | 1031 | R0 DATA | | //| 160+E | 1031 | W0 DATA | TMm1.V_1_GP te=te:160 scalarw(158.6309297) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X132:"132:xpc10" 1032 : major_start_pcl=161 edge_private_start/end=-1/-1 exec=161 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X132:"132:xpc10" //res2: Thread=xpc10 state=X132:"132:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 161 | - | R0 CTRL | | //| 161 | 1032 | R0 DATA | | //| 161+E | 1032 | W0 DATA | TMp1.V_0_GP te=te:161 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X133:"133:xpc10" 1033 : major_start_pcl=162 edge_private_start/end=163/163 exec=162 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X133:"133:xpc10" //res2: Thread=xpc10 state=X133:"133:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 162 | - | R0 CTRL | | //| 162 | 1033 | R0 DATA | | //| 162+E | 1033 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:162 write(29, 158.6309297) | //| 163 | 1033 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X134:"134:xpc10" 1034 : major_start_pcl=164 edge_private_start/end=-1/-1 exec=164 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X134:"134:xpc10" //res2: Thread=xpc10 state=X134:"134:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 164 | - | R0 CTRL | | //| 164 | 1034 | R0 DATA | | //| 164+E | 1034 | W0 DATA | TMm1.V_1_GP te=te:164 scalarw(174.4940227) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X135:"135:xpc10" 1035 : major_start_pcl=165 edge_private_start/end=-1/-1 exec=165 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X135:"135:xpc10" //res2: Thread=xpc10 state=X135:"135:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 165 | - | R0 CTRL | | //| 165 | 1035 | R0 DATA | | //| 165+E | 1035 | W0 DATA | TMp1.V_0_GP te=te:165 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X136:"136:xpc10" 1036 : major_start_pcl=166 edge_private_start/end=167/167 exec=166 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X136:"136:xpc10" //res2: Thread=xpc10 state=X136:"136:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 166 | - | R0 CTRL | | //| 166 | 1036 | R0 DATA | | //| 166+E | 1036 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:166 write(30, 174.4940227) | //| 167 | 1036 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X137:"137:xpc10" 1037 : major_start_pcl=168 edge_private_start/end=-1/-1 exec=168 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X137:"137:xpc10" //res2: Thread=xpc10 state=X137:"137:xpc10" //*-------+------+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------* //| 168 | - | R0 CTRL | | //| 168 | 1037 | R0 DATA | | //| 168+E | 1037 | W0 DATA | TMm1.V_1_GP te=te:168 scalarw(191.943425) | //*-------+------+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X138:"138:xpc10" 1038 : major_start_pcl=169 edge_private_start/end=-1/-1 exec=169 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X138:"138:xpc10" //res2: Thread=xpc10 state=X138:"138:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 169 | - | R0 CTRL | | //| 169 | 1038 | R0 DATA | | //| 169+E | 1038 | W0 DATA | TMp1.V_0_GP te=te:169 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X139:"139:xpc10" 1039 : major_start_pcl=170 edge_private_start/end=171/171 exec=170 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X139:"139:xpc10" //res2: Thread=xpc10 state=X139:"139:xpc10" //*-------+------+---------+--------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------------------* //| 170 | - | R0 CTRL | | //| 170 | 1039 | R0 DATA | | //| 170+E | 1039 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:170 write(31, 191.943425) | //| 171 | 1039 | W1 DATA | | //*-------+------+---------+--------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X140:"140:xpc10" 1040 : major_start_pcl=172 edge_private_start/end=-1/-1 exec=172 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X140:"140:xpc10" //res2: Thread=xpc10 state=X140:"140:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 172 | - | R0 CTRL | | //| 172 | 1040 | R0 DATA | | //| 172+E | 1040 | W0 DATA | TMm1.V_1_GP te=te:172 scalarw(211.1377675) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X141:"141:xpc10" 1041 : major_start_pcl=173 edge_private_start/end=-1/-1 exec=173 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X141:"141:xpc10" //res2: Thread=xpc10 state=X141:"141:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 173 | - | R0 CTRL | | //| 173 | 1041 | R0 DATA | | //| 173+E | 1041 | W0 DATA | TMp1.V_0_GP te=te:173 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X142:"142:xpc10" 1042 : major_start_pcl=174 edge_private_start/end=-1/-1 exec=174 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X142:"142:xpc10" //res2: Thread=xpc10 state=X142:"142:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 174 | - | R0 CTRL | | //| 174 | 1042 | R0 DATA | | //| 174+E | 1042 | W0 DATA | TMm1.V_2_GP te=te:174 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X143:"143:xpc10" 1043 : major_start_pcl=175 edge_private_start/end=-1/-1 exec=175 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X143:"143:xpc10" //res2: Thread=xpc10 state=X143:"143:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 175 | - | R0 CTRL | | //| 175 | 1043 | R0 DATA | | //| 175+E | 1043 | W0 DATA | TMp1.V_0_GP te=te:175 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X144:"144:xpc10" 1044 : major_start_pcl=176 edge_private_start/end=177/177 exec=176 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X144:"144:xpc10" //res2: Thread=xpc10 state=X144:"144:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 176 | - | R0 CTRL | | //| 176 | 1044 | R0 DATA | | //| 176+E | 1044 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:176 write(32, 211.1377675) | //| 177 | 1044 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X145:"145:xpc10" 1045 : major_start_pcl=178 edge_private_start/end=-1/-1 exec=178 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X145:"145:xpc10" //res2: Thread=xpc10 state=X145:"145:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 178 | - | R0 CTRL | | //| 178 | 1045 | R0 DATA | | //| 178+E | 1045 | W0 DATA | TMm1.V_1_GP te=te:178 scalarw(232.2515442) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X146:"146:xpc10" 1046 : major_start_pcl=179 edge_private_start/end=-1/-1 exec=179 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X146:"146:xpc10" //res2: Thread=xpc10 state=X146:"146:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 179 | - | R0 CTRL | | //| 179 | 1046 | R0 DATA | | //| 179+E | 1046 | W0 DATA | TMp1.V_0_GP te=te:179 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X147:"147:xpc10" 1047 : major_start_pcl=180 edge_private_start/end=181/181 exec=180 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X147:"147:xpc10" //res2: Thread=xpc10 state=X147:"147:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 180 | - | R0 CTRL | | //| 180 | 1047 | R0 DATA | | //| 180+E | 1047 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:180 write(33, 232.2515442) | //| 181 | 1047 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X148:"148:xpc10" 1048 : major_start_pcl=182 edge_private_start/end=-1/-1 exec=182 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X148:"148:xpc10" //res2: Thread=xpc10 state=X148:"148:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 182 | - | R0 CTRL | | //| 182 | 1048 | R0 DATA | | //| 182+E | 1048 | W0 DATA | TMm1.V_1_GP te=te:182 scalarw(255.4766986) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X149:"149:xpc10" 1049 : major_start_pcl=183 edge_private_start/end=-1/-1 exec=183 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X149:"149:xpc10" //res2: Thread=xpc10 state=X149:"149:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 183 | - | R0 CTRL | | //| 183 | 1049 | R0 DATA | | //| 183+E | 1049 | W0 DATA | TMp1.V_0_GP te=te:183 scalarw(2) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X150:"150:xpc10" 1050 : major_start_pcl=184 edge_private_start/end=185/185 exec=184 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X150:"150:xpc10" //res2: Thread=xpc10 state=X150:"150:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 184 | - | R0 CTRL | | //| 184 | 1050 | R0 DATA | | //| 184+E | 1050 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:184 write(34, 255.4766986) | //| 185 | 1050 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X151:"151:xpc10" 1051 : major_start_pcl=186 edge_private_start/end=-1/-1 exec=186 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X151:"151:xpc10" //res2: Thread=xpc10 state=X151:"151:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 186 | - | R0 CTRL | | //| 186 | 1051 | R0 DATA | | //| 186+E | 1051 | W0 DATA | TMm1.V_1_GP te=te:186 scalarw(281.0243685) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X152:"152:xpc10" 1052 : major_start_pcl=187 edge_private_start/end=-1/-1 exec=187 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X152:"152:xpc10" //res2: Thread=xpc10 state=X152:"152:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 187 | - | R0 CTRL | | //| 187 | 1052 | R0 DATA | | //| 187+E | 1052 | W0 DATA | TMp1.V_0_GP te=te:187 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X153:"153:xpc10" 1053 : major_start_pcl=188 edge_private_start/end=189/189 exec=188 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X153:"153:xpc10" //res2: Thread=xpc10 state=X153:"153:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 188 | - | R0 CTRL | | //| 188 | 1053 | R0 DATA | | //| 188+E | 1053 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:188 write(35, 281.0243685) | //| 189 | 1053 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X154:"154:xpc10" 1054 : major_start_pcl=190 edge_private_start/end=-1/-1 exec=190 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X154:"154:xpc10" //res2: Thread=xpc10 state=X154:"154:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 190 | - | R0 CTRL | | //| 190 | 1054 | R0 DATA | | //| 190+E | 1054 | W0 DATA | TMm1.V_1_GP te=te:190 scalarw(309.1268053) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X155:"155:xpc10" 1055 : major_start_pcl=191 edge_private_start/end=-1/-1 exec=191 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X155:"155:xpc10" //res2: Thread=xpc10 state=X155:"155:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 191 | - | R0 CTRL | | //| 191 | 1055 | R0 DATA | | //| 191+E | 1055 | W0 DATA | TMp1.V_0_GP te=te:191 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X156:"156:xpc10" 1056 : major_start_pcl=192 edge_private_start/end=193/193 exec=192 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X156:"156:xpc10" //res2: Thread=xpc10 state=X156:"156:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 192 | - | R0 CTRL | | //| 192 | 1056 | R0 DATA | | //| 192+E | 1056 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:192 write(36, 309.1268053) | //| 193 | 1056 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X157:"157:xpc10" 1057 : major_start_pcl=194 edge_private_start/end=-1/-1 exec=194 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X157:"157:xpc10" //res2: Thread=xpc10 state=X157:"157:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 194 | - | R0 CTRL | | //| 194 | 1057 | R0 DATA | | //| 194+E | 1057 | W0 DATA | TMm1.V_1_GP te=te:194 scalarw(340.0394859) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X158:"158:xpc10" 1058 : major_start_pcl=195 edge_private_start/end=-1/-1 exec=195 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X158:"158:xpc10" //res2: Thread=xpc10 state=X158:"158:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 195 | - | R0 CTRL | | //| 195 | 1058 | R0 DATA | | //| 195+E | 1058 | W0 DATA | TMp1.V_0_GP te=te:195 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X159:"159:xpc10" 1059 : major_start_pcl=196 edge_private_start/end=197/197 exec=196 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X159:"159:xpc10" //res2: Thread=xpc10 state=X159:"159:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 196 | - | R0 CTRL | | //| 196 | 1059 | R0 DATA | | //| 196+E | 1059 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:196 write(37, 340.0394859) | //| 197 | 1059 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X160:"160:xpc10" 1060 : major_start_pcl=198 edge_private_start/end=-1/-1 exec=198 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X160:"160:xpc10" //res2: Thread=xpc10 state=X160:"160:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 198 | - | R0 CTRL | | //| 198 | 1060 | R0 DATA | | //| 198+E | 1060 | W0 DATA | TMm1.V_1_GP te=te:198 scalarw(374.0434344) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X161:"161:xpc10" 1061 : major_start_pcl=199 edge_private_start/end=-1/-1 exec=199 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X161:"161:xpc10" //res2: Thread=xpc10 state=X161:"161:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 199 | - | R0 CTRL | | //| 199 | 1061 | R0 DATA | | //| 199+E | 1061 | W0 DATA | TMp1.V_0_GP te=te:199 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X162:"162:xpc10" 1062 : major_start_pcl=200 edge_private_start/end=201/201 exec=200 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X162:"162:xpc10" //res2: Thread=xpc10 state=X162:"162:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 200 | - | R0 CTRL | | //| 200 | 1062 | R0 DATA | | //| 200+E | 1062 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:200 write(38, 374.0434344) | //| 201 | 1062 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X163:"163:xpc10" 1063 : major_start_pcl=202 edge_private_start/end=-1/-1 exec=202 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X163:"163:xpc10" //res2: Thread=xpc10 state=X163:"163:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 202 | - | R0 CTRL | | //| 202 | 1063 | R0 DATA | | //| 202+E | 1063 | W0 DATA | TMm1.V_1_GP te=te:202 scalarw(411.4477779) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X164:"164:xpc10" 1064 : major_start_pcl=203 edge_private_start/end=-1/-1 exec=203 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X164:"164:xpc10" //res2: Thread=xpc10 state=X164:"164:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 203 | - | R0 CTRL | | //| 203 | 1064 | R0 DATA | | //| 203+E | 1064 | W0 DATA | TMp1.V_0_GP te=te:203 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X165:"165:xpc10" 1065 : major_start_pcl=204 edge_private_start/end=205/205 exec=204 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X165:"165:xpc10" //res2: Thread=xpc10 state=X165:"165:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 204 | - | R0 CTRL | | //| 204 | 1065 | R0 DATA | | //| 204+E | 1065 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:204 write(39, 411.4477779) | //| 205 | 1065 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X166:"166:xpc10" 1066 : major_start_pcl=206 edge_private_start/end=-1/-1 exec=206 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X166:"166:xpc10" //res2: Thread=xpc10 state=X166:"166:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 206 | - | R0 CTRL | | //| 206 | 1066 | R0 DATA | | //| 206+E | 1066 | W0 DATA | TMm1.V_1_GP te=te:206 scalarw(452.5925557) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X167:"167:xpc10" 1067 : major_start_pcl=207 edge_private_start/end=-1/-1 exec=207 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X167:"167:xpc10" //res2: Thread=xpc10 state=X167:"167:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 207 | - | R0 CTRL | | //| 207 | 1067 | R0 DATA | | //| 207+E | 1067 | W0 DATA | TMp1.V_0_GP te=te:207 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X168:"168:xpc10" 1068 : major_start_pcl=208 edge_private_start/end=-1/-1 exec=208 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X168:"168:xpc10" //res2: Thread=xpc10 state=X168:"168:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 208 | - | R0 CTRL | | //| 208 | 1068 | R0 DATA | | //| 208+E | 1068 | W0 DATA | TMm1.V_2_GP te=te:208 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X169:"169:xpc10" 1069 : major_start_pcl=209 edge_private_start/end=-1/-1 exec=209 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X169:"169:xpc10" //res2: Thread=xpc10 state=X169:"169:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 209 | - | R0 CTRL | | //| 209 | 1069 | R0 DATA | | //| 209+E | 1069 | W0 DATA | TMp1.V_0_GP te=te:209 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X170:"170:xpc10" 1070 : major_start_pcl=210 edge_private_start/end=211/211 exec=210 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X170:"170:xpc10" //res2: Thread=xpc10 state=X170:"170:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 210 | - | R0 CTRL | | //| 210 | 1070 | R0 DATA | | //| 210+E | 1070 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:210 write(40, 452.5925557) | //| 211 | 1070 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X171:"171:xpc10" 1071 : major_start_pcl=212 edge_private_start/end=-1/-1 exec=212 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X171:"171:xpc10" //res2: Thread=xpc10 state=X171:"171:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 212 | - | R0 CTRL | | //| 212 | 1071 | R0 DATA | | //| 212+E | 1071 | W0 DATA | TMm1.V_1_GP te=te:212 scalarw(497.8518112) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X172:"172:xpc10" 1072 : major_start_pcl=213 edge_private_start/end=-1/-1 exec=213 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X172:"172:xpc10" //res2: Thread=xpc10 state=X172:"172:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 213 | - | R0 CTRL | | //| 213 | 1072 | R0 DATA | | //| 213+E | 1072 | W0 DATA | TMp1.V_0_GP te=te:213 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X173:"173:xpc10" 1073 : major_start_pcl=214 edge_private_start/end=215/215 exec=214 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X173:"173:xpc10" //res2: Thread=xpc10 state=X173:"173:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 214 | - | R0 CTRL | | //| 214 | 1073 | R0 DATA | | //| 214+E | 1073 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:214 write(41, 497.8518112) | //| 215 | 1073 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X174:"174:xpc10" 1074 : major_start_pcl=216 edge_private_start/end=-1/-1 exec=216 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X174:"174:xpc10" //res2: Thread=xpc10 state=X174:"174:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 216 | - | R0 CTRL | | //| 216 | 1074 | R0 DATA | | //| 216+E | 1074 | W0 DATA | TMm1.V_1_GP te=te:216 scalarw(547.6369924) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X175:"175:xpc10" 1075 : major_start_pcl=217 edge_private_start/end=-1/-1 exec=217 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X175:"175:xpc10" //res2: Thread=xpc10 state=X175:"175:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 217 | - | R0 CTRL | | //| 217 | 1075 | R0 DATA | | //| 217+E | 1075 | W0 DATA | TMp1.V_0_GP te=te:217 scalarw(2) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X176:"176:xpc10" 1076 : major_start_pcl=218 edge_private_start/end=219/219 exec=218 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X176:"176:xpc10" //res2: Thread=xpc10 state=X176:"176:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 218 | - | R0 CTRL | | //| 218 | 1076 | R0 DATA | | //| 218+E | 1076 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:218 write(42, 547.6369924) | //| 219 | 1076 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X177:"177:xpc10" 1077 : major_start_pcl=220 edge_private_start/end=-1/-1 exec=220 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X177:"177:xpc10" //res2: Thread=xpc10 state=X177:"177:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 220 | - | R0 CTRL | | //| 220 | 1077 | R0 DATA | | //| 220+E | 1077 | W0 DATA | TMm1.V_1_GP te=te:220 scalarw(602.4006916) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X178:"178:xpc10" 1078 : major_start_pcl=221 edge_private_start/end=-1/-1 exec=221 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X178:"178:xpc10" //res2: Thread=xpc10 state=X178:"178:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 221 | - | R0 CTRL | | //| 221 | 1078 | R0 DATA | | //| 221+E | 1078 | W0 DATA | TMp1.V_0_GP te=te:221 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X179:"179:xpc10" 1079 : major_start_pcl=222 edge_private_start/end=223/223 exec=222 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X179:"179:xpc10" //res2: Thread=xpc10 state=X179:"179:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 222 | - | R0 CTRL | | //| 222 | 1079 | R0 DATA | | //| 222+E | 1079 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:222 write(43, 602.4006916) | //| 223 | 1079 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X180:"180:xpc10" 1080 : major_start_pcl=224 edge_private_start/end=-1/-1 exec=224 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X180:"180:xpc10" //res2: Thread=xpc10 state=X180:"180:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 224 | - | R0 CTRL | | //| 224 | 1080 | R0 DATA | | //| 224+E | 1080 | W0 DATA | TMm1.V_1_GP te=te:224 scalarw(662.6407608) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X181:"181:xpc10" 1081 : major_start_pcl=225 edge_private_start/end=-1/-1 exec=225 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X181:"181:xpc10" //res2: Thread=xpc10 state=X181:"181:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 225 | - | R0 CTRL | | //| 225 | 1081 | R0 DATA | | //| 225+E | 1081 | W0 DATA | TMp1.V_0_GP te=te:225 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X182:"182:xpc10" 1082 : major_start_pcl=226 edge_private_start/end=227/227 exec=226 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X182:"182:xpc10" //res2: Thread=xpc10 state=X182:"182:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 226 | - | R0 CTRL | | //| 226 | 1082 | R0 DATA | | //| 226+E | 1082 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:226 write(44, 662.6407608) | //| 227 | 1082 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X183:"183:xpc10" 1083 : major_start_pcl=228 edge_private_start/end=-1/-1 exec=228 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X183:"183:xpc10" //res2: Thread=xpc10 state=X183:"183:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 228 | - | R0 CTRL | | //| 228 | 1083 | R0 DATA | | //| 228+E | 1083 | W0 DATA | TMm1.V_1_GP te=te:228 scalarw(728.9048369) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X184:"184:xpc10" 1084 : major_start_pcl=229 edge_private_start/end=-1/-1 exec=229 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X184:"184:xpc10" //res2: Thread=xpc10 state=X184:"184:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 229 | - | R0 CTRL | | //| 229 | 1084 | R0 DATA | | //| 229+E | 1084 | W0 DATA | TMp1.V_0_GP te=te:229 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X185:"185:xpc10" 1085 : major_start_pcl=230 edge_private_start/end=231/231 exec=230 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X185:"185:xpc10" //res2: Thread=xpc10 state=X185:"185:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 230 | - | R0 CTRL | | //| 230 | 1085 | R0 DATA | | //| 230+E | 1085 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:230 write(45, 728.9048369) | //| 231 | 1085 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X186:"186:xpc10" 1086 : major_start_pcl=232 edge_private_start/end=-1/-1 exec=232 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X186:"186:xpc10" //res2: Thread=xpc10 state=X186:"186:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 232 | - | R0 CTRL | | //| 232 | 1086 | R0 DATA | | //| 232+E | 1086 | W0 DATA | TMm1.V_1_GP te=te:232 scalarw(801.7953205) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X187:"187:xpc10" 1087 : major_start_pcl=233 edge_private_start/end=-1/-1 exec=233 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X187:"187:xpc10" //res2: Thread=xpc10 state=X187:"187:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 233 | - | R0 CTRL | | //| 233 | 1087 | R0 DATA | | //| 233+E | 1087 | W0 DATA | TMp1.V_0_GP te=te:233 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X188:"188:xpc10" 1088 : major_start_pcl=234 edge_private_start/end=235/235 exec=234 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X188:"188:xpc10" //res2: Thread=xpc10 state=X188:"188:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 234 | - | R0 CTRL | | //| 234 | 1088 | R0 DATA | | //| 234+E | 1088 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:234 write(46, 801.7953205) | //| 235 | 1088 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X189:"189:xpc10" 1089 : major_start_pcl=236 edge_private_start/end=-1/-1 exec=236 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X189:"189:xpc10" //res2: Thread=xpc10 state=X189:"189:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 236 | - | R0 CTRL | | //| 236 | 1089 | R0 DATA | | //| 236+E | 1089 | W0 DATA | TMm1.V_1_GP te=te:236 scalarw(881.9748526) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X190:"190:xpc10" 1090 : major_start_pcl=237 edge_private_start/end=-1/-1 exec=237 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X190:"190:xpc10" //res2: Thread=xpc10 state=X190:"190:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 237 | - | R0 CTRL | | //| 237 | 1090 | R0 DATA | | //| 237+E | 1090 | W0 DATA | TMp1.V_0_GP te=te:237 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X191:"191:xpc10" 1091 : major_start_pcl=238 edge_private_start/end=239/239 exec=238 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X191:"191:xpc10" //res2: Thread=xpc10 state=X191:"191:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 238 | - | R0 CTRL | | //| 238 | 1091 | R0 DATA | | //| 238+E | 1091 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:238 write(47, 881.9748526) | //| 239 | 1091 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X192:"192:xpc10" 1092 : major_start_pcl=240 edge_private_start/end=-1/-1 exec=240 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X192:"192:xpc10" //res2: Thread=xpc10 state=X192:"192:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 240 | - | R0 CTRL | | //| 240 | 1092 | R0 DATA | | //| 240+E | 1092 | W0 DATA | TMm1.V_1_GP te=te:240 scalarw(970.1723378) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X193:"193:xpc10" 1093 : major_start_pcl=241 edge_private_start/end=-1/-1 exec=241 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X193:"193:xpc10" //res2: Thread=xpc10 state=X193:"193:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 241 | - | R0 CTRL | | //| 241 | 1093 | R0 DATA | | //| 241+E | 1093 | W0 DATA | TMp1.V_0_GP te=te:241 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X194:"194:xpc10" 1094 : major_start_pcl=242 edge_private_start/end=-1/-1 exec=242 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X194:"194:xpc10" //res2: Thread=xpc10 state=X194:"194:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 242 | - | R0 CTRL | | //| 242 | 1094 | R0 DATA | | //| 242+E | 1094 | W0 DATA | TMm1.V_2_GP te=te:242 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X195:"195:xpc10" 1095 : major_start_pcl=243 edge_private_start/end=-1/-1 exec=243 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X195:"195:xpc10" //res2: Thread=xpc10 state=X195:"195:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 243 | - | R0 CTRL | | //| 243 | 1095 | R0 DATA | | //| 243+E | 1095 | W0 DATA | TMp1.V_0_GP te=te:243 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X196:"196:xpc10" 1096 : major_start_pcl=244 edge_private_start/end=245/245 exec=244 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X196:"196:xpc10" //res2: Thread=xpc10 state=X196:"196:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 244 | - | R0 CTRL | | //| 244 | 1096 | R0 DATA | | //| 244+E | 1096 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:244 write(48, 970.1723378) | //| 245 | 1096 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X197:"197:xpc10" 1097 : major_start_pcl=246 edge_private_start/end=-1/-1 exec=246 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X197:"197:xpc10" //res2: Thread=xpc10 state=X197:"197:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 246 | - | R0 CTRL | | //| 246 | 1097 | R0 DATA | | //| 246+E | 1097 | W0 DATA | TMm1.V_1_GP te=te:246 scalarw(1067.189572) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X198:"198:xpc10" 1098 : major_start_pcl=247 edge_private_start/end=-1/-1 exec=247 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X198:"198:xpc10" //res2: Thread=xpc10 state=X198:"198:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 247 | - | R0 CTRL | | //| 247 | 1098 | R0 DATA | | //| 247+E | 1098 | W0 DATA | TMp1.V_0_GP te=te:247 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X199:"199:xpc10" 1099 : major_start_pcl=248 edge_private_start/end=249/249 exec=248 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X199:"199:xpc10" //res2: Thread=xpc10 state=X199:"199:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 248 | - | R0 CTRL | | //| 248 | 1099 | R0 DATA | | //| 248+E | 1099 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:248 write(49, 1067.189572) | //| 249 | 1099 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X200:"200:xpc10" 1100 : major_start_pcl=250 edge_private_start/end=-1/-1 exec=250 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X200:"200:xpc10" //res2: Thread=xpc10 state=X200:"200:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 250 | - | R0 CTRL | | //| 250 | 1100 | R0 DATA | | //| 250+E | 1100 | W0 DATA | TMm1.V_1_GP te=te:250 scalarw(1173.908529) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X201:"201:xpc10" 1101 : major_start_pcl=251 edge_private_start/end=-1/-1 exec=251 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X201:"201:xpc10" //res2: Thread=xpc10 state=X201:"201:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 251 | - | R0 CTRL | | //| 251 | 1101 | R0 DATA | | //| 251+E | 1101 | W0 DATA | TMp1.V_0_GP te=te:251 scalarw(2) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X202:"202:xpc10" 1102 : major_start_pcl=252 edge_private_start/end=253/253 exec=252 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X202:"202:xpc10" //res2: Thread=xpc10 state=X202:"202:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 252 | - | R0 CTRL | | //| 252 | 1102 | R0 DATA | | //| 252+E | 1102 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:252 write(50, 1173.908529) | //| 253 | 1102 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X203:"203:xpc10" 1103 : major_start_pcl=254 edge_private_start/end=-1/-1 exec=254 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X203:"203:xpc10" //res2: Thread=xpc10 state=X203:"203:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 254 | - | R0 CTRL | | //| 254 | 1103 | R0 DATA | | //| 254+E | 1103 | W0 DATA | TMm1.V_1_GP te=te:254 scalarw(1291.299382) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X204:"204:xpc10" 1104 : major_start_pcl=255 edge_private_start/end=-1/-1 exec=255 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X204:"204:xpc10" //res2: Thread=xpc10 state=X204:"204:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 255 | - | R0 CTRL | | //| 255 | 1104 | R0 DATA | | //| 255+E | 1104 | W0 DATA | TMp1.V_0_GP te=te:255 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X205:"205:xpc10" 1105 : major_start_pcl=256 edge_private_start/end=257/257 exec=256 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X205:"205:xpc10" //res2: Thread=xpc10 state=X205:"205:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 256 | - | R0 CTRL | | //| 256 | 1105 | R0 DATA | | //| 256+E | 1105 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:256 write(51, 1291.299382) | //| 257 | 1105 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X206:"206:xpc10" 1106 : major_start_pcl=258 edge_private_start/end=-1/-1 exec=258 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X206:"206:xpc10" //res2: Thread=xpc10 state=X206:"206:xpc10" //*-------+------+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------* //| 258 | - | R0 CTRL | | //| 258 | 1106 | R0 DATA | | //| 258+E | 1106 | W0 DATA | TMm1.V_1_GP te=te:258 scalarw(1420.42932) | //*-------+------+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X207:"207:xpc10" 1107 : major_start_pcl=259 edge_private_start/end=-1/-1 exec=259 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X207:"207:xpc10" //res2: Thread=xpc10 state=X207:"207:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 259 | - | R0 CTRL | | //| 259 | 1107 | R0 DATA | | //| 259+E | 1107 | W0 DATA | TMp1.V_0_GP te=te:259 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X208:"208:xpc10" 1108 : major_start_pcl=260 edge_private_start/end=261/261 exec=260 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X208:"208:xpc10" //res2: Thread=xpc10 state=X208:"208:xpc10" //*-------+------+---------+--------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------------------* //| 260 | - | R0 CTRL | | //| 260 | 1108 | R0 DATA | | //| 260+E | 1108 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:260 write(52, 1420.42932) | //| 261 | 1108 | W1 DATA | | //*-------+------+---------+--------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X209:"209:xpc10" 1109 : major_start_pcl=262 edge_private_start/end=-1/-1 exec=262 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X209:"209:xpc10" //res2: Thread=xpc10 state=X209:"209:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 262 | - | R0 CTRL | | //| 262 | 1109 | R0 DATA | | //| 262+E | 1109 | W0 DATA | TMm1.V_1_GP te=te:262 scalarw(1562.472252) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X210:"210:xpc10" 1110 : major_start_pcl=263 edge_private_start/end=-1/-1 exec=263 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X210:"210:xpc10" //res2: Thread=xpc10 state=X210:"210:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 263 | - | R0 CTRL | | //| 263 | 1110 | R0 DATA | | //| 263+E | 1110 | W0 DATA | TMp1.V_0_GP te=te:263 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X211:"211:xpc10" 1111 : major_start_pcl=264 edge_private_start/end=265/265 exec=264 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X211:"211:xpc10" //res2: Thread=xpc10 state=X211:"211:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 264 | - | R0 CTRL | | //| 264 | 1111 | R0 DATA | | //| 264+E | 1111 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:264 write(53, 1562.472252) | //| 265 | 1111 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X212:"212:xpc10" 1112 : major_start_pcl=266 edge_private_start/end=-1/-1 exec=266 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X212:"212:xpc10" //res2: Thread=xpc10 state=X212:"212:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 266 | - | R0 CTRL | | //| 266 | 1112 | R0 DATA | | //| 266+E | 1112 | W0 DATA | TMm1.V_1_GP te=te:266 scalarw(1718.719477) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X213:"213:xpc10" 1113 : major_start_pcl=267 edge_private_start/end=-1/-1 exec=267 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X213:"213:xpc10" //res2: Thread=xpc10 state=X213:"213:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 267 | - | R0 CTRL | | //| 267 | 1113 | R0 DATA | | //| 267+E | 1113 | W0 DATA | TMp1.V_0_GP te=te:267 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X214:"214:xpc10" 1114 : major_start_pcl=268 edge_private_start/end=269/269 exec=268 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X214:"214:xpc10" //res2: Thread=xpc10 state=X214:"214:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 268 | - | R0 CTRL | | //| 268 | 1114 | R0 DATA | | //| 268+E | 1114 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:268 write(54, 1718.719477) | //| 269 | 1114 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X215:"215:xpc10" 1115 : major_start_pcl=270 edge_private_start/end=-1/-1 exec=270 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X215:"215:xpc10" //res2: Thread=xpc10 state=X215:"215:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 270 | - | R0 CTRL | | //| 270 | 1115 | R0 DATA | | //| 270+E | 1115 | W0 DATA | TMm1.V_1_GP te=te:270 scalarw(1890.591425) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X216:"216:xpc10" 1116 : major_start_pcl=271 edge_private_start/end=-1/-1 exec=271 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X216:"216:xpc10" //res2: Thread=xpc10 state=X216:"216:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 271 | - | R0 CTRL | | //| 271 | 1116 | R0 DATA | | //| 271+E | 1116 | W0 DATA | TMp1.V_0_GP te=te:271 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X217:"217:xpc10" 1117 : major_start_pcl=272 edge_private_start/end=273/273 exec=272 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X217:"217:xpc10" //res2: Thread=xpc10 state=X217:"217:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 272 | - | R0 CTRL | | //| 272 | 1117 | R0 DATA | | //| 272+E | 1117 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:272 write(55, 1890.591425) | //| 273 | 1117 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X218:"218:xpc10" 1118 : major_start_pcl=274 edge_private_start/end=-1/-1 exec=274 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X218:"218:xpc10" //res2: Thread=xpc10 state=X218:"218:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 274 | - | R0 CTRL | | //| 274 | 1118 | R0 DATA | | //| 274+E | 1118 | W0 DATA | TMm1.V_1_GP te=te:274 scalarw(2079.650567) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X219:"219:xpc10" 1119 : major_start_pcl=275 edge_private_start/end=-1/-1 exec=275 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X219:"219:xpc10" //res2: Thread=xpc10 state=X219:"219:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 275 | - | R0 CTRL | | //| 275 | 1119 | R0 DATA | | //| 275+E | 1119 | W0 DATA | TMp1.V_0_GP te=te:275 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X220:"220:xpc10" 1120 : major_start_pcl=276 edge_private_start/end=-1/-1 exec=276 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X220:"220:xpc10" //res2: Thread=xpc10 state=X220:"220:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 276 | - | R0 CTRL | | //| 276 | 1120 | R0 DATA | | //| 276+E | 1120 | W0 DATA | TMm1.V_2_GP te=te:276 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X221:"221:xpc10" 1121 : major_start_pcl=277 edge_private_start/end=-1/-1 exec=277 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X221:"221:xpc10" //res2: Thread=xpc10 state=X221:"221:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 277 | - | R0 CTRL | | //| 277 | 1121 | R0 DATA | | //| 277+E | 1121 | W0 DATA | TMp1.V_0_GP te=te:277 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X222:"222:xpc10" 1122 : major_start_pcl=278 edge_private_start/end=279/279 exec=278 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X222:"222:xpc10" //res2: Thread=xpc10 state=X222:"222:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 278 | - | R0 CTRL | | //| 278 | 1122 | R0 DATA | | //| 278+E | 1122 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:278 write(56, 2079.650567) | //| 279 | 1122 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X223:"223:xpc10" 1123 : major_start_pcl=280 edge_private_start/end=-1/-1 exec=280 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X223:"223:xpc10" //res2: Thread=xpc10 state=X223:"223:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 280 | - | R0 CTRL | | //| 280 | 1123 | R0 DATA | | //| 280+E | 1123 | W0 DATA | TMm1.V_1_GP te=te:280 scalarw(2287.615624) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X224:"224:xpc10" 1124 : major_start_pcl=281 edge_private_start/end=-1/-1 exec=281 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X224:"224:xpc10" //res2: Thread=xpc10 state=X224:"224:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 281 | - | R0 CTRL | | //| 281 | 1124 | R0 DATA | | //| 281+E | 1124 | W0 DATA | TMp1.V_0_GP te=te:281 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X225:"225:xpc10" 1125 : major_start_pcl=282 edge_private_start/end=283/283 exec=282 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X225:"225:xpc10" //res2: Thread=xpc10 state=X225:"225:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 282 | - | R0 CTRL | | //| 282 | 1125 | R0 DATA | | //| 282+E | 1125 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:282 write(57, 2287.615624) | //| 283 | 1125 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X226:"226:xpc10" 1126 : major_start_pcl=284 edge_private_start/end=-1/-1 exec=284 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X226:"226:xpc10" //res2: Thread=xpc10 state=X226:"226:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 284 | - | R0 CTRL | | //| 284 | 1126 | R0 DATA | | //| 284+E | 1126 | W0 DATA | TMm1.V_1_GP te=te:284 scalarw(2516.377186) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X227:"227:xpc10" 1127 : major_start_pcl=285 edge_private_start/end=-1/-1 exec=285 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X227:"227:xpc10" //res2: Thread=xpc10 state=X227:"227:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 285 | - | R0 CTRL | | //| 285 | 1127 | R0 DATA | | //| 285+E | 1127 | W0 DATA | TMp1.V_0_GP te=te:285 scalarw(2) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X228:"228:xpc10" 1128 : major_start_pcl=286 edge_private_start/end=287/287 exec=286 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X228:"228:xpc10" //res2: Thread=xpc10 state=X228:"228:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 286 | - | R0 CTRL | | //| 286 | 1128 | R0 DATA | | //| 286+E | 1128 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:286 write(58, 2516.377186) | //| 287 | 1128 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X229:"229:xpc10" 1129 : major_start_pcl=288 edge_private_start/end=-1/-1 exec=288 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X229:"229:xpc10" //res2: Thread=xpc10 state=X229:"229:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 288 | - | R0 CTRL | | //| 288 | 1129 | R0 DATA | | //| 288+E | 1129 | W0 DATA | TMm1.V_1_GP te=te:288 scalarw(2768.014905) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X230:"230:xpc10" 1130 : major_start_pcl=289 edge_private_start/end=-1/-1 exec=289 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X230:"230:xpc10" //res2: Thread=xpc10 state=X230:"230:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 289 | - | R0 CTRL | | //| 289 | 1130 | R0 DATA | | //| 289+E | 1130 | W0 DATA | TMp1.V_0_GP te=te:289 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X231:"231:xpc10" 1131 : major_start_pcl=290 edge_private_start/end=291/291 exec=290 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X231:"231:xpc10" //res2: Thread=xpc10 state=X231:"231:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 290 | - | R0 CTRL | | //| 290 | 1131 | R0 DATA | | //| 290+E | 1131 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:290 write(59, 2768.014905) | //| 291 | 1131 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X232:"232:xpc10" 1132 : major_start_pcl=292 edge_private_start/end=-1/-1 exec=292 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X232:"232:xpc10" //res2: Thread=xpc10 state=X232:"232:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 292 | - | R0 CTRL | | //| 292 | 1132 | R0 DATA | | //| 292+E | 1132 | W0 DATA | TMm1.V_1_GP te=te:292 scalarw(3044.816395) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X233:"233:xpc10" 1133 : major_start_pcl=293 edge_private_start/end=-1/-1 exec=293 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X233:"233:xpc10" //res2: Thread=xpc10 state=X233:"233:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 293 | - | R0 CTRL | | //| 293 | 1133 | R0 DATA | | //| 293+E | 1133 | W0 DATA | TMp1.V_0_GP te=te:293 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X234:"234:xpc10" 1134 : major_start_pcl=294 edge_private_start/end=295/295 exec=294 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X234:"234:xpc10" //res2: Thread=xpc10 state=X234:"234:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 294 | - | R0 CTRL | | //| 294 | 1134 | R0 DATA | | //| 294+E | 1134 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:294 write(60, 3044.816395) | //| 295 | 1134 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X235:"235:xpc10" 1135 : major_start_pcl=296 edge_private_start/end=-1/-1 exec=296 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X235:"235:xpc10" //res2: Thread=xpc10 state=X235:"235:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 296 | - | R0 CTRL | | //| 296 | 1135 | R0 DATA | | //| 296+E | 1135 | W0 DATA | TMm1.V_1_GP te=te:296 scalarw(3349.298035) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X236:"236:xpc10" 1136 : major_start_pcl=297 edge_private_start/end=-1/-1 exec=297 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X236:"236:xpc10" //res2: Thread=xpc10 state=X236:"236:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 297 | - | R0 CTRL | | //| 297 | 1136 | R0 DATA | | //| 297+E | 1136 | W0 DATA | TMp1.V_0_GP te=te:297 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X237:"237:xpc10" 1137 : major_start_pcl=298 edge_private_start/end=299/299 exec=298 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X237:"237:xpc10" //res2: Thread=xpc10 state=X237:"237:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 298 | - | R0 CTRL | | //| 298 | 1137 | R0 DATA | | //| 298+E | 1137 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:298 write(61, 3349.298035) | //| 299 | 1137 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X238:"238:xpc10" 1138 : major_start_pcl=300 edge_private_start/end=-1/-1 exec=300 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X238:"238:xpc10" //res2: Thread=xpc10 state=X238:"238:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 300 | - | R0 CTRL | | //| 300 | 1138 | R0 DATA | | //| 300+E | 1138 | W0 DATA | TMm1.V_1_GP te=te:300 scalarw(3684.227838) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X239:"239:xpc10" 1139 : major_start_pcl=301 edge_private_start/end=-1/-1 exec=301 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X239:"239:xpc10" //res2: Thread=xpc10 state=X239:"239:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 301 | - | R0 CTRL | | //| 301 | 1139 | R0 DATA | | //| 301+E | 1139 | W0 DATA | TMp1.V_0_GP te=te:301 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X240:"240:xpc10" 1140 : major_start_pcl=302 edge_private_start/end=303/303 exec=302 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X240:"240:xpc10" //res2: Thread=xpc10 state=X240:"240:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 302 | - | R0 CTRL | | //| 302 | 1140 | R0 DATA | | //| 302+E | 1140 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:302 write(62, 3684.227838) | //| 303 | 1140 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X241:"241:xpc10" 1141 : major_start_pcl=304 edge_private_start/end=-1/-1 exec=304 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X241:"241:xpc10" //res2: Thread=xpc10 state=X241:"241:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 304 | - | R0 CTRL | | //| 304 | 1141 | R0 DATA | | //| 304+E | 1141 | W0 DATA | TMm1.V_1_GP te=te:304 scalarw(4052.650622) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X242:"242:xpc10" 1142 : major_start_pcl=305 edge_private_start/end=-1/-1 exec=305 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X242:"242:xpc10" //res2: Thread=xpc10 state=X242:"242:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 305 | - | R0 CTRL | | //| 305 | 1142 | R0 DATA | | //| 305+E | 1142 | W0 DATA | TMp1.V_0_GP te=te:305 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X243:"243:xpc10" 1143 : major_start_pcl=306 edge_private_start/end=307/307 exec=306 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X243:"243:xpc10" //res2: Thread=xpc10 state=X243:"243:xpc10" //*-------+------+---------+---------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------* //| 306 | - | R0 CTRL | | //| 306 | 1143 | R0 DATA | | //| 306+E | 1143 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:306 write(63, 4052.650622) | //| 307 | 1143 | W1 DATA | | //*-------+------+---------+---------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X244:"244:xpc10" 1144 : major_start_pcl=308 edge_private_start/end=-1/-1 exec=308 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X244:"244:xpc10" //res2: Thread=xpc10 state=X244:"244:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 308 | - | R0 CTRL | | //| 308 | 1144 | R0 DATA | | //| 308+E | 1144 | W0 DATA | TMm1.V_1_GP te=te:308 scalarw(4457.915685) | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X245:"245:xpc10" 1145 : major_start_pcl=309 edge_private_start/end=-1/-1 exec=309 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X245:"245:xpc10" //res2: Thread=xpc10 state=X245:"245:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 309 | - | R0 CTRL | | //| 309 | 1145 | R0 DATA | | //| 309+E | 1145 | W0 DATA | TMp1.V_0_GP te=te:309 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X246:"246:xpc10" 1146 : major_start_pcl=310 edge_private_start/end=-1/-1 exec=310 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X246:"246:xpc10" //res2: Thread=xpc10 state=X246:"246:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 310 | - | R0 CTRL | | //| 310 | 1146 | R0 DATA | | //| 310+E | 1146 | W0 DATA | TMm1.V_2_GP te=te:310 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X247:"247:xpc10" 1147 : major_start_pcl=311 edge_private_start/end=-1/-1 exec=311 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X247:"247:xpc10" //res2: Thread=xpc10 state=X247:"247:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 311 | - | R0 CTRL | | //| 311 | 1147 | R0 DATA | | //| 311+E | 1147 | W0 DATA | TMp1.V_0_GP te=te:311 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X248:"248:xpc10" 1148 : major_start_pcl=312 edge_private_start/end=313/313 exec=313 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X248:"248:xpc10" //res2: Thread=xpc10 state=X248:"248:xpc10" //*-------+------+---------+------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------* //| 312 | - | R0 CTRL | | //| 312 | 1148 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:312 read(0) | //| 313 | 1148 | R1 DATA | | //| 313+E | 1148 | W0 DATA | Tlge0.9_V_4 te=te:313 scalarw(E1) | //*-------+------+---------+------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X249:"249:xpc10" 1149 : major_start_pcl=314 edge_private_start/end=315/319 exec=318 (dend=5) //Simple greedy schedule for res2: Thread=xpc10 state=X249:"249:xpc10" //res2: Thread=xpc10 state=X249:"249:xpc10" //*-------+------+---------+-----------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------------------------------* //| 314 | - | R0 CTRL | | //| 314 | 1149 | R0 DATA | CVFPADDER10 te=te:314 *fixed-func-ALU*(10, Tlge0.9_V_4) | //| 315 | 1149 | R1 DATA | | //| 316 | 1149 | R2 DATA | | //| 317 | 1149 | R3 DATA | | //| 318 | 1149 | R4 DATA | | //| 318+E | 1149 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:318 write(0, 10+Tlge0.9_V_4) | //| 319 | 1149 | W1 DATA | | //*-------+------+---------+-----------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X250:"250:xpc10" 1150 : major_start_pcl=320 edge_private_start/end=-1/-1 exec=320 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X250:"250:xpc10" //res2: Thread=xpc10 state=X250:"250:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 320 | - | R0 CTRL | | //| 320 | 1150 | R0 DATA | | //| 320+E | 1150 | W0 DATA | TMp1.V_0_GP te=te:320 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X251:"251:xpc10" 1151 : major_start_pcl=321 edge_private_start/end=322/322 exec=322 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X251:"251:xpc10" //res2: Thread=xpc10 state=X251:"251:xpc10" //*-------+------+---------+------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------* //| 321 | - | R0 CTRL | | //| 321 | 1151 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:321 read(9) | //| 322 | 1151 | R1 DATA | | //| 322+E | 1151 | W0 DATA | Tlge0.9_V_4 te=te:322 scalarw(E2) | //*-------+------+---------+------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X252:"252:xpc10" 1152 : major_start_pcl=323 edge_private_start/end=324/328 exec=327 (dend=5) //Simple greedy schedule for res2: Thread=xpc10 state=X252:"252:xpc10" //res2: Thread=xpc10 state=X252:"252:xpc10" //*-------+------+---------+-----------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------------------------------* //| 323 | - | R0 CTRL | | //| 323 | 1152 | R0 DATA | CVFPADDER12 te=te:323 *fixed-func-ALU*(10, Tlge0.9_V_4) | //| 324 | 1152 | R1 DATA | | //| 325 | 1152 | R2 DATA | | //| 326 | 1152 | R3 DATA | | //| 327 | 1152 | R4 DATA | | //| 327+E | 1152 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:327 write(9, 10+Tlge0.9_V_4) | //| 328 | 1152 | W1 DATA | | //*-------+------+---------+-----------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X253:"253:xpc10" 1153 : major_start_pcl=329 edge_private_start/end=-1/-1 exec=329 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X253:"253:xpc10" //res2: Thread=xpc10 state=X253:"253:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 329 | - | R0 CTRL | | //| 329 | 1153 | R0 DATA | | //| 329+E | 1153 | W0 DATA | TMp1.V_0_GP te=te:329 scalarw(2) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X254:"254:xpc10" 1154 : major_start_pcl=330 edge_private_start/end=331/331 exec=331 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X254:"254:xpc10" //res2: Thread=xpc10 state=X254:"254:xpc10" //*-------+------+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------* //| 330 | - | R0 CTRL | | //| 330 | 1154 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:330 read(18) | //| 331 | 1154 | R1 DATA | | //| 331+E | 1154 | W0 DATA | Tlge0.9_V_4 te=te:331 scalarw(E3) | //*-------+------+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X255:"255:xpc10" 1155 : major_start_pcl=332 edge_private_start/end=333/337 exec=336 (dend=5) //Simple greedy schedule for res2: Thread=xpc10 state=X255:"255:xpc10" //res2: Thread=xpc10 state=X255:"255:xpc10" //*-------+------+---------+------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------------------* //| 332 | - | R0 CTRL | | //| 332 | 1155 | R0 DATA | CVFPADDER14 te=te:332 *fixed-func-ALU*(10, Tlge0.9_V_4) | //| 333 | 1155 | R1 DATA | | //| 334 | 1155 | R2 DATA | | //| 335 | 1155 | R3 DATA | | //| 336 | 1155 | R4 DATA | | //| 336+E | 1155 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:336 write(18, 10+Tlge0.9_V_4) | //| 337 | 1155 | W1 DATA | | //*-------+------+---------+------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X256:"256:xpc10" 1156 : major_start_pcl=338 edge_private_start/end=-1/-1 exec=338 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X256:"256:xpc10" //res2: Thread=xpc10 state=X256:"256:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 338 | - | R0 CTRL | | //| 338 | 1156 | R0 DATA | | //| 338+E | 1156 | W0 DATA | TMp1.V_0_GP te=te:338 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X257:"257:xpc10" 1157 : major_start_pcl=339 edge_private_start/end=340/340 exec=340 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X257:"257:xpc10" //res2: Thread=xpc10 state=X257:"257:xpc10" //*-------+------+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------* //| 339 | - | R0 CTRL | | //| 339 | 1157 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:339 read(27) | //| 340 | 1157 | R1 DATA | | //| 340+E | 1157 | W0 DATA | Tlge0.9_V_4 te=te:340 scalarw(E4) | //*-------+------+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X258:"258:xpc10" 1158 : major_start_pcl=341 edge_private_start/end=342/346 exec=345 (dend=5) //Simple greedy schedule for res2: Thread=xpc10 state=X258:"258:xpc10" //res2: Thread=xpc10 state=X258:"258:xpc10" //*-------+------+---------+------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------------------* //| 341 | - | R0 CTRL | | //| 341 | 1158 | R0 DATA | CVFPADDER16 te=te:341 *fixed-func-ALU*(10, Tlge0.9_V_4) | //| 342 | 1158 | R1 DATA | | //| 343 | 1158 | R2 DATA | | //| 344 | 1158 | R3 DATA | | //| 345 | 1158 | R4 DATA | | //| 345+E | 1158 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:345 write(27, 10+Tlge0.9_V_4) | //| 346 | 1158 | W1 DATA | | //*-------+------+---------+------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X259:"259:xpc10" 1159 : major_start_pcl=347 edge_private_start/end=-1/-1 exec=347 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X259:"259:xpc10" //res2: Thread=xpc10 state=X259:"259:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 347 | - | R0 CTRL | | //| 347 | 1159 | R0 DATA | | //| 347+E | 1159 | W0 DATA | TMp1.V_0_GP te=te:347 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X260:"260:xpc10" 1160 : major_start_pcl=348 edge_private_start/end=349/349 exec=349 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X260:"260:xpc10" //res2: Thread=xpc10 state=X260:"260:xpc10" //*-------+------+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------* //| 348 | - | R0 CTRL | | //| 348 | 1160 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:348 read(36) | //| 349 | 1160 | R1 DATA | | //| 349+E | 1160 | W0 DATA | Tlge0.9_V_4 te=te:349 scalarw(E5) | //*-------+------+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X261:"261:xpc10" 1161 : major_start_pcl=350 edge_private_start/end=351/355 exec=354 (dend=5) //Simple greedy schedule for res2: Thread=xpc10 state=X261:"261:xpc10" //res2: Thread=xpc10 state=X261:"261:xpc10" //*-------+------+---------+------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------------------* //| 350 | - | R0 CTRL | | //| 350 | 1161 | R0 DATA | CVFPADDER18 te=te:350 *fixed-func-ALU*(10, Tlge0.9_V_4) | //| 351 | 1161 | R1 DATA | | //| 352 | 1161 | R2 DATA | | //| 353 | 1161 | R3 DATA | | //| 354 | 1161 | R4 DATA | | //| 354+E | 1161 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:354 write(36, 10+Tlge0.9_V_4) | //| 355 | 1161 | W1 DATA | | //*-------+------+---------+------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X262:"262:xpc10" 1162 : major_start_pcl=356 edge_private_start/end=-1/-1 exec=356 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X262:"262:xpc10" //res2: Thread=xpc10 state=X262:"262:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 356 | - | R0 CTRL | | //| 356 | 1162 | R0 DATA | | //| 356+E | 1162 | W0 DATA | TMp1.V_0_GP te=te:356 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X263:"263:xpc10" 1163 : major_start_pcl=357 edge_private_start/end=358/358 exec=358 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X263:"263:xpc10" //res2: Thread=xpc10 state=X263:"263:xpc10" //*-------+------+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------* //| 357 | - | R0 CTRL | | //| 357 | 1163 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:357 read(45) | //| 358 | 1163 | R1 DATA | | //| 358+E | 1163 | W0 DATA | Tlge0.9_V_4 te=te:358 scalarw(E6) | //*-------+------+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X264:"264:xpc10" 1164 : major_start_pcl=359 edge_private_start/end=360/364 exec=363 (dend=5) //Simple greedy schedule for res2: Thread=xpc10 state=X264:"264:xpc10" //res2: Thread=xpc10 state=X264:"264:xpc10" //*-------+------+---------+------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------------------* //| 359 | - | R0 CTRL | | //| 359 | 1164 | R0 DATA | CVFPADDER20 te=te:359 *fixed-func-ALU*(10, Tlge0.9_V_4) | //| 360 | 1164 | R1 DATA | | //| 361 | 1164 | R2 DATA | | //| 362 | 1164 | R3 DATA | | //| 363 | 1164 | R4 DATA | | //| 363+E | 1164 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:363 write(45, 10+Tlge0.9_V_4) | //| 364 | 1164 | W1 DATA | | //*-------+------+---------+------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X265:"265:xpc10" 1165 : major_start_pcl=365 edge_private_start/end=-1/-1 exec=365 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X265:"265:xpc10" //res2: Thread=xpc10 state=X265:"265:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 365 | - | R0 CTRL | | //| 365 | 1165 | R0 DATA | | //| 365+E | 1165 | W0 DATA | TMp1.V_0_GP te=te:365 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X266:"266:xpc10" 1166 : major_start_pcl=366 edge_private_start/end=367/367 exec=367 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X266:"266:xpc10" //res2: Thread=xpc10 state=X266:"266:xpc10" //*-------+------+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------* //| 366 | - | R0 CTRL | | //| 366 | 1166 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:366 read(54) | //| 367 | 1166 | R1 DATA | | //| 367+E | 1166 | W0 DATA | Tlge0.9_V_4 te=te:367 scalarw(E7) | //*-------+------+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X267:"267:xpc10" 1167 : major_start_pcl=368 edge_private_start/end=369/373 exec=372 (dend=5) //Simple greedy schedule for res2: Thread=xpc10 state=X267:"267:xpc10" //res2: Thread=xpc10 state=X267:"267:xpc10" //*-------+------+---------+------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------------------* //| 368 | - | R0 CTRL | | //| 368 | 1167 | R0 DATA | CVFPADDER20 te=te:368 *fixed-func-ALU*(10, Tlge0.9_V_4) | //| 369 | 1167 | R1 DATA | | //| 370 | 1167 | R2 DATA | | //| 371 | 1167 | R3 DATA | | //| 372 | 1167 | R4 DATA | | //| 372+E | 1167 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:372 write(54, 10+Tlge0.9_V_4) | //| 373 | 1167 | W1 DATA | | //*-------+------+---------+------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X268:"268:xpc10" 1168 : major_start_pcl=374 edge_private_start/end=-1/-1 exec=374 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X268:"268:xpc10" //res2: Thread=xpc10 state=X268:"268:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 374 | - | R0 CTRL | | //| 374 | 1168 | R0 DATA | | //| 374+E | 1168 | W0 DATA | TMp1.V_0_GP te=te:374 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X269:"269:xpc10" 1169 : major_start_pcl=375 edge_private_start/end=376/376 exec=376 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X269:"269:xpc10" //res2: Thread=xpc10 state=X269:"269:xpc10" //*-------+------+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------* //| 375 | - | R0 CTRL | | //| 375 | 1169 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:375 read(63) | //| 376 | 1169 | R1 DATA | | //| 376+E | 1169 | W0 DATA | Tlge0.9_V_4 te=te:376 scalarw(E8) | //*-------+------+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X270:"270:xpc10" 1170 : major_start_pcl=377 edge_private_start/end=378/382 exec=381 (dend=5) //Simple greedy schedule for res2: Thread=xpc10 state=X270:"270:xpc10" //res2: Thread=xpc10 state=X270:"270:xpc10" //*-------+------+---------+------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------------------* //| 377 | - | R0 CTRL | | //| 377 | 1170 | R0 DATA | CVFPADDER20 te=te:377 *fixed-func-ALU*(10, Tlge0.9_V_4) | //| 378 | 1170 | R1 DATA | | //| 379 | 1170 | R2 DATA | | //| 380 | 1170 | R3 DATA | | //| 381 | 1170 | R4 DATA | | //| 381+E | 1170 | W0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:381 write(63, 10+Tlge0.9_V_4) | //| 382 | 1170 | W1 DATA | | //*-------+------+---------+------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X271:"271:xpc10" 1171 : major_start_pcl=383 edge_private_start/end=-1/-1 exec=383 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X271:"271:xpc10" //res2: Thread=xpc10 state=X271:"271:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 383 | - | R0 CTRL | | //| 383 | 1171 | R0 DATA | | //| 383+E | 1171 | W0 DATA | TMp1.V_0_GP te=te:383 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X272:"272:xpc10" 1172 : major_start_pcl=384 edge_private_start/end=-1/-1 exec=384 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X272:"272:xpc10" //res2: Thread=xpc10 state=X272:"272:xpc10" //*-------+------+---------+---------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------------* //| 384 | - | R0 CTRL | | //| 384 | 1172 | R0 DATA | | //| 384+E | 1172 | W0 DATA | TMp1.V_0_GP te=te:384 scalarw(0) PLI:Kiwi L/U demo - L/U ... | //*-------+------+---------+---------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X273:"273:xpc10" 1173 : major_start_pcl=385 edge_private_start/end=-1/-1 exec=385 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X273:"273:xpc10" //res2: Thread=xpc10 state=X273:"273:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 385 | - | R0 CTRL | | //| 385 | 1173 | R0 DATA | | //| 385+E | 1173 | W0 DATA | TMm1.V_2_GP te=te:385 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X274:"274:xpc10" 1174 : major_start_pcl=386 edge_private_start/end=387/388 exec=387 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X274:"274:xpc10" //res2: Thread=xpc10 state=X274:"274:xpc10" //*-------+------+---------+-----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------------------* //| 386 | - | R0 CTRL | | //| 386 | 1174 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:386 read(0) | //| 387 | 1174 | R1 DATA | | //| 387+E | 1174 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:387 write(0, E1) | //| 388 | 1174 | W1 DATA | | //*-------+------+---------+-----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X275:"275:xpc10" 1175 : major_start_pcl=389 edge_private_start/end=-1/-1 exec=389 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X275:"275:xpc10" //res2: Thread=xpc10 state=X275:"275:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 389 | - | R0 CTRL | | //| 389 | 1175 | R0 DATA | | //| 389+E | 1175 | W0 DATA | TMm1.V_2_GP te=te:389 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X276:"276:xpc10" 1176 : major_start_pcl=390 edge_private_start/end=391/392 exec=391 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X276:"276:xpc10" //res2: Thread=xpc10 state=X276:"276:xpc10" //*-------+------+---------+-----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------------------* //| 390 | - | R0 CTRL | | //| 390 | 1176 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:390 read(1) | //| 391 | 1176 | R1 DATA | | //| 391+E | 1176 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:391 write(1, E9) | //| 392 | 1176 | W1 DATA | | //*-------+------+---------+-----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X277:"277:xpc10" 1177 : major_start_pcl=393 edge_private_start/end=-1/-1 exec=393 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X277:"277:xpc10" //res2: Thread=xpc10 state=X277:"277:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 393 | - | R0 CTRL | | //| 393 | 1177 | R0 DATA | | //| 393+E | 1177 | W0 DATA | TMm1.V_2_GP te=te:393 scalarw(2) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X278:"278:xpc10" 1178 : major_start_pcl=394 edge_private_start/end=395/396 exec=395 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X278:"278:xpc10" //res2: Thread=xpc10 state=X278:"278:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 394 | - | R0 CTRL | | //| 394 | 1178 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:394 read(2) | //| 395 | 1178 | R1 DATA | | //| 395+E | 1178 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:395 write(2, E10) | //| 396 | 1178 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X279:"279:xpc10" 1179 : major_start_pcl=397 edge_private_start/end=-1/-1 exec=397 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X279:"279:xpc10" //res2: Thread=xpc10 state=X279:"279:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 397 | - | R0 CTRL | | //| 397 | 1179 | R0 DATA | | //| 397+E | 1179 | W0 DATA | TMm1.V_2_GP te=te:397 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X280:"280:xpc10" 1180 : major_start_pcl=398 edge_private_start/end=399/400 exec=399 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X280:"280:xpc10" //res2: Thread=xpc10 state=X280:"280:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 398 | - | R0 CTRL | | //| 398 | 1180 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:398 read(3) | //| 399 | 1180 | R1 DATA | | //| 399+E | 1180 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:399 write(3, E11) | //| 400 | 1180 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X281:"281:xpc10" 1181 : major_start_pcl=401 edge_private_start/end=-1/-1 exec=401 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X281:"281:xpc10" //res2: Thread=xpc10 state=X281:"281:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 401 | - | R0 CTRL | | //| 401 | 1181 | R0 DATA | | //| 401+E | 1181 | W0 DATA | TMm1.V_2_GP te=te:401 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X282:"282:xpc10" 1182 : major_start_pcl=402 edge_private_start/end=403/404 exec=403 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X282:"282:xpc10" //res2: Thread=xpc10 state=X282:"282:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 402 | - | R0 CTRL | | //| 402 | 1182 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:402 read(4) | //| 403 | 1182 | R1 DATA | | //| 403+E | 1182 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:403 write(4, E12) | //| 404 | 1182 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X283:"283:xpc10" 1183 : major_start_pcl=405 edge_private_start/end=-1/-1 exec=405 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X283:"283:xpc10" //res2: Thread=xpc10 state=X283:"283:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 405 | - | R0 CTRL | | //| 405 | 1183 | R0 DATA | | //| 405+E | 1183 | W0 DATA | TMm1.V_2_GP te=te:405 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X284:"284:xpc10" 1184 : major_start_pcl=406 edge_private_start/end=407/408 exec=407 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X284:"284:xpc10" //res2: Thread=xpc10 state=X284:"284:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 406 | - | R0 CTRL | | //| 406 | 1184 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:406 read(5) | //| 407 | 1184 | R1 DATA | | //| 407+E | 1184 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:407 write(5, E13) | //| 408 | 1184 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X285:"285:xpc10" 1185 : major_start_pcl=409 edge_private_start/end=-1/-1 exec=409 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X285:"285:xpc10" //res2: Thread=xpc10 state=X285:"285:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 409 | - | R0 CTRL | | //| 409 | 1185 | R0 DATA | | //| 409+E | 1185 | W0 DATA | TMm1.V_2_GP te=te:409 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X286:"286:xpc10" 1186 : major_start_pcl=410 edge_private_start/end=411/412 exec=411 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X286:"286:xpc10" //res2: Thread=xpc10 state=X286:"286:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 410 | - | R0 CTRL | | //| 410 | 1186 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:410 read(6) | //| 411 | 1186 | R1 DATA | | //| 411+E | 1186 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:411 write(6, E14) | //| 412 | 1186 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X287:"287:xpc10" 1187 : major_start_pcl=413 edge_private_start/end=-1/-1 exec=413 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X287:"287:xpc10" //res2: Thread=xpc10 state=X287:"287:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 413 | - | R0 CTRL | | //| 413 | 1187 | R0 DATA | | //| 413+E | 1187 | W0 DATA | TMm1.V_2_GP te=te:413 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X288:"288:xpc10" 1188 : major_start_pcl=414 edge_private_start/end=415/416 exec=415 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X288:"288:xpc10" //res2: Thread=xpc10 state=X288:"288:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 414 | - | R0 CTRL | | //| 414 | 1188 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:414 read(7) | //| 415 | 1188 | R1 DATA | | //| 415+E | 1188 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:415 write(7, E15) | //| 416 | 1188 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X289:"289:xpc10" 1189 : major_start_pcl=417 edge_private_start/end=-1/-1 exec=417 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X289:"289:xpc10" //res2: Thread=xpc10 state=X289:"289:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 417 | - | R0 CTRL | | //| 417 | 1189 | R0 DATA | | //| 417+E | 1189 | W0 DATA | TMm1.V_2_GP te=te:417 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X290:"290:xpc10" 1190 : major_start_pcl=418 edge_private_start/end=-1/-1 exec=418 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X290:"290:xpc10" //res2: Thread=xpc10 state=X290:"290:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 418 | - | R0 CTRL | | //| 418 | 1190 | R0 DATA | | //| 418+E | 1190 | W0 DATA | TMp1.V_0_GP te=te:418 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X291:"291:xpc10" 1191 : major_start_pcl=419 edge_private_start/end=-1/-1 exec=419 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X291:"291:xpc10" //res2: Thread=xpc10 state=X291:"291:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 419 | - | R0 CTRL | | //| 419 | 1191 | R0 DATA | | //| 419+E | 1191 | W0 DATA | TMm1.V_2_GP te=te:419 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X292:"292:xpc10" 1192 : major_start_pcl=420 edge_private_start/end=421/422 exec=421 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X292:"292:xpc10" //res2: Thread=xpc10 state=X292:"292:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 420 | - | R0 CTRL | | //| 420 | 1192 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:420 read(8) | //| 421 | 1192 | R1 DATA | | //| 421+E | 1192 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:421 write(8, E16) | //| 422 | 1192 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X293:"293:xpc10" 1193 : major_start_pcl=423 edge_private_start/end=-1/-1 exec=423 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X293:"293:xpc10" //res2: Thread=xpc10 state=X293:"293:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 423 | - | R0 CTRL | | //| 423 | 1193 | R0 DATA | | //| 423+E | 1193 | W0 DATA | TMm1.V_2_GP te=te:423 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X294:"294:xpc10" 1194 : major_start_pcl=424 edge_private_start/end=425/426 exec=425 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X294:"294:xpc10" //res2: Thread=xpc10 state=X294:"294:xpc10" //*-------+------+---------+-----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------------------* //| 424 | - | R0 CTRL | | //| 424 | 1194 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:424 read(9) | //| 425 | 1194 | R1 DATA | | //| 425+E | 1194 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:425 write(9, E2) | //| 426 | 1194 | W1 DATA | | //*-------+------+---------+-----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X295:"295:xpc10" 1195 : major_start_pcl=427 edge_private_start/end=-1/-1 exec=427 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X295:"295:xpc10" //res2: Thread=xpc10 state=X295:"295:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 427 | - | R0 CTRL | | //| 427 | 1195 | R0 DATA | | //| 427+E | 1195 | W0 DATA | TMm1.V_2_GP te=te:427 scalarw(2) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X296:"296:xpc10" 1196 : major_start_pcl=428 edge_private_start/end=429/430 exec=429 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X296:"296:xpc10" //res2: Thread=xpc10 state=X296:"296:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 428 | - | R0 CTRL | | //| 428 | 1196 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:428 read(10) | //| 429 | 1196 | R1 DATA | | //| 429+E | 1196 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:429 write(10, E17) | //| 430 | 1196 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X297:"297:xpc10" 1197 : major_start_pcl=431 edge_private_start/end=-1/-1 exec=431 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X297:"297:xpc10" //res2: Thread=xpc10 state=X297:"297:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 431 | - | R0 CTRL | | //| 431 | 1197 | R0 DATA | | //| 431+E | 1197 | W0 DATA | TMm1.V_2_GP te=te:431 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X298:"298:xpc10" 1198 : major_start_pcl=432 edge_private_start/end=433/434 exec=433 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X298:"298:xpc10" //res2: Thread=xpc10 state=X298:"298:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 432 | - | R0 CTRL | | //| 432 | 1198 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:432 read(11) | //| 433 | 1198 | R1 DATA | | //| 433+E | 1198 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:433 write(11, E18) | //| 434 | 1198 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X299:"299:xpc10" 1199 : major_start_pcl=435 edge_private_start/end=-1/-1 exec=435 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X299:"299:xpc10" //res2: Thread=xpc10 state=X299:"299:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 435 | - | R0 CTRL | | //| 435 | 1199 | R0 DATA | | //| 435+E | 1199 | W0 DATA | TMm1.V_2_GP te=te:435 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X300:"300:xpc10" 1200 : major_start_pcl=436 edge_private_start/end=437/438 exec=437 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X300:"300:xpc10" //res2: Thread=xpc10 state=X300:"300:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 436 | - | R0 CTRL | | //| 436 | 1200 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:436 read(12) | //| 437 | 1200 | R1 DATA | | //| 437+E | 1200 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:437 write(12, E19) | //| 438 | 1200 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X301:"301:xpc10" 1201 : major_start_pcl=439 edge_private_start/end=-1/-1 exec=439 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X301:"301:xpc10" //res2: Thread=xpc10 state=X301:"301:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 439 | - | R0 CTRL | | //| 439 | 1201 | R0 DATA | | //| 439+E | 1201 | W0 DATA | TMm1.V_2_GP te=te:439 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X302:"302:xpc10" 1202 : major_start_pcl=440 edge_private_start/end=441/442 exec=441 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X302:"302:xpc10" //res2: Thread=xpc10 state=X302:"302:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 440 | - | R0 CTRL | | //| 440 | 1202 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:440 read(13) | //| 441 | 1202 | R1 DATA | | //| 441+E | 1202 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:441 write(13, E20) | //| 442 | 1202 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X303:"303:xpc10" 1203 : major_start_pcl=443 edge_private_start/end=-1/-1 exec=443 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X303:"303:xpc10" //res2: Thread=xpc10 state=X303:"303:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 443 | - | R0 CTRL | | //| 443 | 1203 | R0 DATA | | //| 443+E | 1203 | W0 DATA | TMm1.V_2_GP te=te:443 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X304:"304:xpc10" 1204 : major_start_pcl=444 edge_private_start/end=445/446 exec=445 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X304:"304:xpc10" //res2: Thread=xpc10 state=X304:"304:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 444 | - | R0 CTRL | | //| 444 | 1204 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:444 read(14) | //| 445 | 1204 | R1 DATA | | //| 445+E | 1204 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:445 write(14, E21) | //| 446 | 1204 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X305:"305:xpc10" 1205 : major_start_pcl=447 edge_private_start/end=-1/-1 exec=447 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X305:"305:xpc10" //res2: Thread=xpc10 state=X305:"305:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 447 | - | R0 CTRL | | //| 447 | 1205 | R0 DATA | | //| 447+E | 1205 | W0 DATA | TMm1.V_2_GP te=te:447 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X306:"306:xpc10" 1206 : major_start_pcl=448 edge_private_start/end=449/450 exec=449 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X306:"306:xpc10" //res2: Thread=xpc10 state=X306:"306:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 448 | - | R0 CTRL | | //| 448 | 1206 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:448 read(15) | //| 449 | 1206 | R1 DATA | | //| 449+E | 1206 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:449 write(15, E22) | //| 450 | 1206 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X307:"307:xpc10" 1207 : major_start_pcl=451 edge_private_start/end=-1/-1 exec=451 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X307:"307:xpc10" //res2: Thread=xpc10 state=X307:"307:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 451 | - | R0 CTRL | | //| 451 | 1207 | R0 DATA | | //| 451+E | 1207 | W0 DATA | TMm1.V_2_GP te=te:451 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X308:"308:xpc10" 1208 : major_start_pcl=452 edge_private_start/end=-1/-1 exec=452 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X308:"308:xpc10" //res2: Thread=xpc10 state=X308:"308:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 452 | - | R0 CTRL | | //| 452 | 1208 | R0 DATA | | //| 452+E | 1208 | W0 DATA | TMp1.V_0_GP te=te:452 scalarw(2) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X309:"309:xpc10" 1209 : major_start_pcl=453 edge_private_start/end=-1/-1 exec=453 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X309:"309:xpc10" //res2: Thread=xpc10 state=X309:"309:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 453 | - | R0 CTRL | | //| 453 | 1209 | R0 DATA | | //| 453+E | 1209 | W0 DATA | TMm1.V_2_GP te=te:453 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X310:"310:xpc10" 1210 : major_start_pcl=454 edge_private_start/end=455/456 exec=455 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X310:"310:xpc10" //res2: Thread=xpc10 state=X310:"310:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 454 | - | R0 CTRL | | //| 454 | 1210 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:454 read(16) | //| 455 | 1210 | R1 DATA | | //| 455+E | 1210 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:455 write(16, E23) | //| 456 | 1210 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X311:"311:xpc10" 1211 : major_start_pcl=457 edge_private_start/end=-1/-1 exec=457 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X311:"311:xpc10" //res2: Thread=xpc10 state=X311:"311:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 457 | - | R0 CTRL | | //| 457 | 1211 | R0 DATA | | //| 457+E | 1211 | W0 DATA | TMm1.V_2_GP te=te:457 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X312:"312:xpc10" 1212 : major_start_pcl=458 edge_private_start/end=459/460 exec=459 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X312:"312:xpc10" //res2: Thread=xpc10 state=X312:"312:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 458 | - | R0 CTRL | | //| 458 | 1212 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:458 read(17) | //| 459 | 1212 | R1 DATA | | //| 459+E | 1212 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:459 write(17, E24) | //| 460 | 1212 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X313:"313:xpc10" 1213 : major_start_pcl=461 edge_private_start/end=-1/-1 exec=461 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X313:"313:xpc10" //res2: Thread=xpc10 state=X313:"313:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 461 | - | R0 CTRL | | //| 461 | 1213 | R0 DATA | | //| 461+E | 1213 | W0 DATA | TMm1.V_2_GP te=te:461 scalarw(2) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X314:"314:xpc10" 1214 : major_start_pcl=462 edge_private_start/end=463/464 exec=463 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X314:"314:xpc10" //res2: Thread=xpc10 state=X314:"314:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 462 | - | R0 CTRL | | //| 462 | 1214 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:462 read(18) | //| 463 | 1214 | R1 DATA | | //| 463+E | 1214 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:463 write(18, E3) | //| 464 | 1214 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X315:"315:xpc10" 1215 : major_start_pcl=465 edge_private_start/end=-1/-1 exec=465 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X315:"315:xpc10" //res2: Thread=xpc10 state=X315:"315:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 465 | - | R0 CTRL | | //| 465 | 1215 | R0 DATA | | //| 465+E | 1215 | W0 DATA | TMm1.V_2_GP te=te:465 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X316:"316:xpc10" 1216 : major_start_pcl=466 edge_private_start/end=467/468 exec=467 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X316:"316:xpc10" //res2: Thread=xpc10 state=X316:"316:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 466 | - | R0 CTRL | | //| 466 | 1216 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:466 read(19) | //| 467 | 1216 | R1 DATA | | //| 467+E | 1216 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:467 write(19, E25) | //| 468 | 1216 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X317:"317:xpc10" 1217 : major_start_pcl=469 edge_private_start/end=-1/-1 exec=469 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X317:"317:xpc10" //res2: Thread=xpc10 state=X317:"317:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 469 | - | R0 CTRL | | //| 469 | 1217 | R0 DATA | | //| 469+E | 1217 | W0 DATA | TMm1.V_2_GP te=te:469 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X318:"318:xpc10" 1218 : major_start_pcl=470 edge_private_start/end=471/472 exec=471 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X318:"318:xpc10" //res2: Thread=xpc10 state=X318:"318:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 470 | - | R0 CTRL | | //| 470 | 1218 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:470 read(20) | //| 471 | 1218 | R1 DATA | | //| 471+E | 1218 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:471 write(20, E26) | //| 472 | 1218 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X319:"319:xpc10" 1219 : major_start_pcl=473 edge_private_start/end=-1/-1 exec=473 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X319:"319:xpc10" //res2: Thread=xpc10 state=X319:"319:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 473 | - | R0 CTRL | | //| 473 | 1219 | R0 DATA | | //| 473+E | 1219 | W0 DATA | TMm1.V_2_GP te=te:473 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X320:"320:xpc10" 1220 : major_start_pcl=474 edge_private_start/end=475/476 exec=475 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X320:"320:xpc10" //res2: Thread=xpc10 state=X320:"320:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 474 | - | R0 CTRL | | //| 474 | 1220 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:474 read(21) | //| 475 | 1220 | R1 DATA | | //| 475+E | 1220 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:475 write(21, E27) | //| 476 | 1220 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X321:"321:xpc10" 1221 : major_start_pcl=477 edge_private_start/end=-1/-1 exec=477 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X321:"321:xpc10" //res2: Thread=xpc10 state=X321:"321:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 477 | - | R0 CTRL | | //| 477 | 1221 | R0 DATA | | //| 477+E | 1221 | W0 DATA | TMm1.V_2_GP te=te:477 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X322:"322:xpc10" 1222 : major_start_pcl=478 edge_private_start/end=479/480 exec=479 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X322:"322:xpc10" //res2: Thread=xpc10 state=X322:"322:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 478 | - | R0 CTRL | | //| 478 | 1222 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:478 read(22) | //| 479 | 1222 | R1 DATA | | //| 479+E | 1222 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:479 write(22, E28) | //| 480 | 1222 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X323:"323:xpc10" 1223 : major_start_pcl=481 edge_private_start/end=-1/-1 exec=481 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X323:"323:xpc10" //res2: Thread=xpc10 state=X323:"323:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 481 | - | R0 CTRL | | //| 481 | 1223 | R0 DATA | | //| 481+E | 1223 | W0 DATA | TMm1.V_2_GP te=te:481 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X324:"324:xpc10" 1224 : major_start_pcl=482 edge_private_start/end=483/484 exec=483 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X324:"324:xpc10" //res2: Thread=xpc10 state=X324:"324:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 482 | - | R0 CTRL | | //| 482 | 1224 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:482 read(23) | //| 483 | 1224 | R1 DATA | | //| 483+E | 1224 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:483 write(23, E29) | //| 484 | 1224 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X325:"325:xpc10" 1225 : major_start_pcl=485 edge_private_start/end=-1/-1 exec=485 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X325:"325:xpc10" //res2: Thread=xpc10 state=X325:"325:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 485 | - | R0 CTRL | | //| 485 | 1225 | R0 DATA | | //| 485+E | 1225 | W0 DATA | TMm1.V_2_GP te=te:485 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X326:"326:xpc10" 1226 : major_start_pcl=486 edge_private_start/end=-1/-1 exec=486 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X326:"326:xpc10" //res2: Thread=xpc10 state=X326:"326:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 486 | - | R0 CTRL | | //| 486 | 1226 | R0 DATA | | //| 486+E | 1226 | W0 DATA | TMp1.V_0_GP te=te:486 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X327:"327:xpc10" 1227 : major_start_pcl=487 edge_private_start/end=-1/-1 exec=487 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X327:"327:xpc10" //res2: Thread=xpc10 state=X327:"327:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 487 | - | R0 CTRL | | //| 487 | 1227 | R0 DATA | | //| 487+E | 1227 | W0 DATA | TMm1.V_2_GP te=te:487 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X328:"328:xpc10" 1228 : major_start_pcl=488 edge_private_start/end=489/490 exec=489 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X328:"328:xpc10" //res2: Thread=xpc10 state=X328:"328:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 488 | - | R0 CTRL | | //| 488 | 1228 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:488 read(24) | //| 489 | 1228 | R1 DATA | | //| 489+E | 1228 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:489 write(24, E30) | //| 490 | 1228 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X329:"329:xpc10" 1229 : major_start_pcl=491 edge_private_start/end=-1/-1 exec=491 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X329:"329:xpc10" //res2: Thread=xpc10 state=X329:"329:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 491 | - | R0 CTRL | | //| 491 | 1229 | R0 DATA | | //| 491+E | 1229 | W0 DATA | TMm1.V_2_GP te=te:491 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X330:"330:xpc10" 1230 : major_start_pcl=492 edge_private_start/end=493/494 exec=493 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X330:"330:xpc10" //res2: Thread=xpc10 state=X330:"330:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 492 | - | R0 CTRL | | //| 492 | 1230 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:492 read(25) | //| 493 | 1230 | R1 DATA | | //| 493+E | 1230 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:493 write(25, E31) | //| 494 | 1230 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X331:"331:xpc10" 1231 : major_start_pcl=495 edge_private_start/end=-1/-1 exec=495 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X331:"331:xpc10" //res2: Thread=xpc10 state=X331:"331:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 495 | - | R0 CTRL | | //| 495 | 1231 | R0 DATA | | //| 495+E | 1231 | W0 DATA | TMm1.V_2_GP te=te:495 scalarw(2) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X332:"332:xpc10" 1232 : major_start_pcl=496 edge_private_start/end=497/498 exec=497 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X332:"332:xpc10" //res2: Thread=xpc10 state=X332:"332:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 496 | - | R0 CTRL | | //| 496 | 1232 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:496 read(26) | //| 497 | 1232 | R1 DATA | | //| 497+E | 1232 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:497 write(26, E32) | //| 498 | 1232 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X333:"333:xpc10" 1233 : major_start_pcl=499 edge_private_start/end=-1/-1 exec=499 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X333:"333:xpc10" //res2: Thread=xpc10 state=X333:"333:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 499 | - | R0 CTRL | | //| 499 | 1233 | R0 DATA | | //| 499+E | 1233 | W0 DATA | TMm1.V_2_GP te=te:499 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X334:"334:xpc10" 1234 : major_start_pcl=500 edge_private_start/end=501/502 exec=501 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X334:"334:xpc10" //res2: Thread=xpc10 state=X334:"334:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 500 | - | R0 CTRL | | //| 500 | 1234 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:500 read(27) | //| 501 | 1234 | R1 DATA | | //| 501+E | 1234 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:501 write(27, E4) | //| 502 | 1234 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X335:"335:xpc10" 1235 : major_start_pcl=503 edge_private_start/end=-1/-1 exec=503 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X335:"335:xpc10" //res2: Thread=xpc10 state=X335:"335:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 503 | - | R0 CTRL | | //| 503 | 1235 | R0 DATA | | //| 503+E | 1235 | W0 DATA | TMm1.V_2_GP te=te:503 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X336:"336:xpc10" 1236 : major_start_pcl=504 edge_private_start/end=505/506 exec=505 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X336:"336:xpc10" //res2: Thread=xpc10 state=X336:"336:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 504 | - | R0 CTRL | | //| 504 | 1236 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:504 read(28) | //| 505 | 1236 | R1 DATA | | //| 505+E | 1236 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:505 write(28, E33) | //| 506 | 1236 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X337:"337:xpc10" 1237 : major_start_pcl=507 edge_private_start/end=-1/-1 exec=507 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X337:"337:xpc10" //res2: Thread=xpc10 state=X337:"337:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 507 | - | R0 CTRL | | //| 507 | 1237 | R0 DATA | | //| 507+E | 1237 | W0 DATA | TMm1.V_2_GP te=te:507 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X338:"338:xpc10" 1238 : major_start_pcl=508 edge_private_start/end=509/510 exec=509 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X338:"338:xpc10" //res2: Thread=xpc10 state=X338:"338:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 508 | - | R0 CTRL | | //| 508 | 1238 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:508 read(29) | //| 509 | 1238 | R1 DATA | | //| 509+E | 1238 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:509 write(29, E34) | //| 510 | 1238 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X339:"339:xpc10" 1239 : major_start_pcl=511 edge_private_start/end=-1/-1 exec=511 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X339:"339:xpc10" //res2: Thread=xpc10 state=X339:"339:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 511 | - | R0 CTRL | | //| 511 | 1239 | R0 DATA | | //| 511+E | 1239 | W0 DATA | TMm1.V_2_GP te=te:511 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X340:"340:xpc10" 1240 : major_start_pcl=512 edge_private_start/end=513/514 exec=513 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X340:"340:xpc10" //res2: Thread=xpc10 state=X340:"340:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 512 | - | R0 CTRL | | //| 512 | 1240 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:512 read(30) | //| 513 | 1240 | R1 DATA | | //| 513+E | 1240 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:513 write(30, E35) | //| 514 | 1240 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X341:"341:xpc10" 1241 : major_start_pcl=515 edge_private_start/end=-1/-1 exec=515 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X341:"341:xpc10" //res2: Thread=xpc10 state=X341:"341:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 515 | - | R0 CTRL | | //| 515 | 1241 | R0 DATA | | //| 515+E | 1241 | W0 DATA | TMm1.V_2_GP te=te:515 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X342:"342:xpc10" 1242 : major_start_pcl=516 edge_private_start/end=517/518 exec=517 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X342:"342:xpc10" //res2: Thread=xpc10 state=X342:"342:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 516 | - | R0 CTRL | | //| 516 | 1242 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:516 read(31) | //| 517 | 1242 | R1 DATA | | //| 517+E | 1242 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:517 write(31, E36) | //| 518 | 1242 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X343:"343:xpc10" 1243 : major_start_pcl=519 edge_private_start/end=-1/-1 exec=519 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X343:"343:xpc10" //res2: Thread=xpc10 state=X343:"343:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 519 | - | R0 CTRL | | //| 519 | 1243 | R0 DATA | | //| 519+E | 1243 | W0 DATA | TMm1.V_2_GP te=te:519 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X344:"344:xpc10" 1244 : major_start_pcl=520 edge_private_start/end=-1/-1 exec=520 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X344:"344:xpc10" //res2: Thread=xpc10 state=X344:"344:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 520 | - | R0 CTRL | | //| 520 | 1244 | R0 DATA | | //| 520+E | 1244 | W0 DATA | TMp1.V_0_GP te=te:520 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X345:"345:xpc10" 1245 : major_start_pcl=521 edge_private_start/end=-1/-1 exec=521 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X345:"345:xpc10" //res2: Thread=xpc10 state=X345:"345:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 521 | - | R0 CTRL | | //| 521 | 1245 | R0 DATA | | //| 521+E | 1245 | W0 DATA | TMm1.V_2_GP te=te:521 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X346:"346:xpc10" 1246 : major_start_pcl=522 edge_private_start/end=523/524 exec=523 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X346:"346:xpc10" //res2: Thread=xpc10 state=X346:"346:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 522 | - | R0 CTRL | | //| 522 | 1246 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:522 read(32) | //| 523 | 1246 | R1 DATA | | //| 523+E | 1246 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:523 write(32, E37) | //| 524 | 1246 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X347:"347:xpc10" 1247 : major_start_pcl=525 edge_private_start/end=-1/-1 exec=525 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X347:"347:xpc10" //res2: Thread=xpc10 state=X347:"347:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 525 | - | R0 CTRL | | //| 525 | 1247 | R0 DATA | | //| 525+E | 1247 | W0 DATA | TMm1.V_2_GP te=te:525 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X348:"348:xpc10" 1248 : major_start_pcl=526 edge_private_start/end=527/528 exec=527 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X348:"348:xpc10" //res2: Thread=xpc10 state=X348:"348:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 526 | - | R0 CTRL | | //| 526 | 1248 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:526 read(33) | //| 527 | 1248 | R1 DATA | | //| 527+E | 1248 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:527 write(33, E38) | //| 528 | 1248 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X349:"349:xpc10" 1249 : major_start_pcl=529 edge_private_start/end=-1/-1 exec=529 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X349:"349:xpc10" //res2: Thread=xpc10 state=X349:"349:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 529 | - | R0 CTRL | | //| 529 | 1249 | R0 DATA | | //| 529+E | 1249 | W0 DATA | TMm1.V_2_GP te=te:529 scalarw(2) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X350:"350:xpc10" 1250 : major_start_pcl=530 edge_private_start/end=531/532 exec=531 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X350:"350:xpc10" //res2: Thread=xpc10 state=X350:"350:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 530 | - | R0 CTRL | | //| 530 | 1250 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:530 read(34) | //| 531 | 1250 | R1 DATA | | //| 531+E | 1250 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:531 write(34, E39) | //| 532 | 1250 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X351:"351:xpc10" 1251 : major_start_pcl=533 edge_private_start/end=-1/-1 exec=533 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X351:"351:xpc10" //res2: Thread=xpc10 state=X351:"351:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 533 | - | R0 CTRL | | //| 533 | 1251 | R0 DATA | | //| 533+E | 1251 | W0 DATA | TMm1.V_2_GP te=te:533 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X352:"352:xpc10" 1252 : major_start_pcl=534 edge_private_start/end=535/536 exec=535 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X352:"352:xpc10" //res2: Thread=xpc10 state=X352:"352:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 534 | - | R0 CTRL | | //| 534 | 1252 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:534 read(35) | //| 535 | 1252 | R1 DATA | | //| 535+E | 1252 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:535 write(35, E40) | //| 536 | 1252 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X353:"353:xpc10" 1253 : major_start_pcl=537 edge_private_start/end=-1/-1 exec=537 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X353:"353:xpc10" //res2: Thread=xpc10 state=X353:"353:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 537 | - | R0 CTRL | | //| 537 | 1253 | R0 DATA | | //| 537+E | 1253 | W0 DATA | TMm1.V_2_GP te=te:537 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X354:"354:xpc10" 1254 : major_start_pcl=538 edge_private_start/end=539/540 exec=539 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X354:"354:xpc10" //res2: Thread=xpc10 state=X354:"354:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 538 | - | R0 CTRL | | //| 538 | 1254 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:538 read(36) | //| 539 | 1254 | R1 DATA | | //| 539+E | 1254 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:539 write(36, E5) | //| 540 | 1254 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X355:"355:xpc10" 1255 : major_start_pcl=541 edge_private_start/end=-1/-1 exec=541 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X355:"355:xpc10" //res2: Thread=xpc10 state=X355:"355:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 541 | - | R0 CTRL | | //| 541 | 1255 | R0 DATA | | //| 541+E | 1255 | W0 DATA | TMm1.V_2_GP te=te:541 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X356:"356:xpc10" 1256 : major_start_pcl=542 edge_private_start/end=543/544 exec=543 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X356:"356:xpc10" //res2: Thread=xpc10 state=X356:"356:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 542 | - | R0 CTRL | | //| 542 | 1256 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:542 read(37) | //| 543 | 1256 | R1 DATA | | //| 543+E | 1256 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:543 write(37, E41) | //| 544 | 1256 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X357:"357:xpc10" 1257 : major_start_pcl=545 edge_private_start/end=-1/-1 exec=545 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X357:"357:xpc10" //res2: Thread=xpc10 state=X357:"357:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 545 | - | R0 CTRL | | //| 545 | 1257 | R0 DATA | | //| 545+E | 1257 | W0 DATA | TMm1.V_2_GP te=te:545 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X358:"358:xpc10" 1258 : major_start_pcl=546 edge_private_start/end=547/548 exec=547 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X358:"358:xpc10" //res2: Thread=xpc10 state=X358:"358:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 546 | - | R0 CTRL | | //| 546 | 1258 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:546 read(38) | //| 547 | 1258 | R1 DATA | | //| 547+E | 1258 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:547 write(38, E42) | //| 548 | 1258 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X359:"359:xpc10" 1259 : major_start_pcl=549 edge_private_start/end=-1/-1 exec=549 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X359:"359:xpc10" //res2: Thread=xpc10 state=X359:"359:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 549 | - | R0 CTRL | | //| 549 | 1259 | R0 DATA | | //| 549+E | 1259 | W0 DATA | TMm1.V_2_GP te=te:549 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X360:"360:xpc10" 1260 : major_start_pcl=550 edge_private_start/end=551/552 exec=551 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X360:"360:xpc10" //res2: Thread=xpc10 state=X360:"360:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 550 | - | R0 CTRL | | //| 550 | 1260 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:550 read(39) | //| 551 | 1260 | R1 DATA | | //| 551+E | 1260 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:551 write(39, E43) | //| 552 | 1260 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X361:"361:xpc10" 1261 : major_start_pcl=553 edge_private_start/end=-1/-1 exec=553 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X361:"361:xpc10" //res2: Thread=xpc10 state=X361:"361:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 553 | - | R0 CTRL | | //| 553 | 1261 | R0 DATA | | //| 553+E | 1261 | W0 DATA | TMm1.V_2_GP te=te:553 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X362:"362:xpc10" 1262 : major_start_pcl=554 edge_private_start/end=-1/-1 exec=554 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X362:"362:xpc10" //res2: Thread=xpc10 state=X362:"362:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 554 | - | R0 CTRL | | //| 554 | 1262 | R0 DATA | | //| 554+E | 1262 | W0 DATA | TMp1.V_0_GP te=te:554 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X363:"363:xpc10" 1263 : major_start_pcl=555 edge_private_start/end=-1/-1 exec=555 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X363:"363:xpc10" //res2: Thread=xpc10 state=X363:"363:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 555 | - | R0 CTRL | | //| 555 | 1263 | R0 DATA | | //| 555+E | 1263 | W0 DATA | TMm1.V_2_GP te=te:555 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X364:"364:xpc10" 1264 : major_start_pcl=556 edge_private_start/end=557/558 exec=557 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X364:"364:xpc10" //res2: Thread=xpc10 state=X364:"364:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 556 | - | R0 CTRL | | //| 556 | 1264 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:556 read(40) | //| 557 | 1264 | R1 DATA | | //| 557+E | 1264 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:557 write(40, E44) | //| 558 | 1264 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X365:"365:xpc10" 1265 : major_start_pcl=559 edge_private_start/end=-1/-1 exec=559 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X365:"365:xpc10" //res2: Thread=xpc10 state=X365:"365:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 559 | - | R0 CTRL | | //| 559 | 1265 | R0 DATA | | //| 559+E | 1265 | W0 DATA | TMm1.V_2_GP te=te:559 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X366:"366:xpc10" 1266 : major_start_pcl=560 edge_private_start/end=561/562 exec=561 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X366:"366:xpc10" //res2: Thread=xpc10 state=X366:"366:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 560 | - | R0 CTRL | | //| 560 | 1266 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:560 read(41) | //| 561 | 1266 | R1 DATA | | //| 561+E | 1266 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:561 write(41, E45) | //| 562 | 1266 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X367:"367:xpc10" 1267 : major_start_pcl=563 edge_private_start/end=-1/-1 exec=563 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X367:"367:xpc10" //res2: Thread=xpc10 state=X367:"367:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 563 | - | R0 CTRL | | //| 563 | 1267 | R0 DATA | | //| 563+E | 1267 | W0 DATA | TMm1.V_2_GP te=te:563 scalarw(2) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X368:"368:xpc10" 1268 : major_start_pcl=564 edge_private_start/end=565/566 exec=565 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X368:"368:xpc10" //res2: Thread=xpc10 state=X368:"368:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 564 | - | R0 CTRL | | //| 564 | 1268 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:564 read(42) | //| 565 | 1268 | R1 DATA | | //| 565+E | 1268 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:565 write(42, E46) | //| 566 | 1268 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X369:"369:xpc10" 1269 : major_start_pcl=567 edge_private_start/end=-1/-1 exec=567 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X369:"369:xpc10" //res2: Thread=xpc10 state=X369:"369:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 567 | - | R0 CTRL | | //| 567 | 1269 | R0 DATA | | //| 567+E | 1269 | W0 DATA | TMm1.V_2_GP te=te:567 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X370:"370:xpc10" 1270 : major_start_pcl=568 edge_private_start/end=569/570 exec=569 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X370:"370:xpc10" //res2: Thread=xpc10 state=X370:"370:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 568 | - | R0 CTRL | | //| 568 | 1270 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:568 read(43) | //| 569 | 1270 | R1 DATA | | //| 569+E | 1270 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:569 write(43, E47) | //| 570 | 1270 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X371:"371:xpc10" 1271 : major_start_pcl=571 edge_private_start/end=-1/-1 exec=571 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X371:"371:xpc10" //res2: Thread=xpc10 state=X371:"371:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 571 | - | R0 CTRL | | //| 571 | 1271 | R0 DATA | | //| 571+E | 1271 | W0 DATA | TMm1.V_2_GP te=te:571 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X372:"372:xpc10" 1272 : major_start_pcl=572 edge_private_start/end=573/574 exec=573 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X372:"372:xpc10" //res2: Thread=xpc10 state=X372:"372:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 572 | - | R0 CTRL | | //| 572 | 1272 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:572 read(44) | //| 573 | 1272 | R1 DATA | | //| 573+E | 1272 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:573 write(44, E48) | //| 574 | 1272 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X373:"373:xpc10" 1273 : major_start_pcl=575 edge_private_start/end=-1/-1 exec=575 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X373:"373:xpc10" //res2: Thread=xpc10 state=X373:"373:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 575 | - | R0 CTRL | | //| 575 | 1273 | R0 DATA | | //| 575+E | 1273 | W0 DATA | TMm1.V_2_GP te=te:575 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X374:"374:xpc10" 1274 : major_start_pcl=576 edge_private_start/end=577/578 exec=577 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X374:"374:xpc10" //res2: Thread=xpc10 state=X374:"374:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 576 | - | R0 CTRL | | //| 576 | 1274 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:576 read(45) | //| 577 | 1274 | R1 DATA | | //| 577+E | 1274 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:577 write(45, E6) | //| 578 | 1274 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X375:"375:xpc10" 1275 : major_start_pcl=579 edge_private_start/end=-1/-1 exec=579 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X375:"375:xpc10" //res2: Thread=xpc10 state=X375:"375:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 579 | - | R0 CTRL | | //| 579 | 1275 | R0 DATA | | //| 579+E | 1275 | W0 DATA | TMm1.V_2_GP te=te:579 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X376:"376:xpc10" 1276 : major_start_pcl=580 edge_private_start/end=581/582 exec=581 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X376:"376:xpc10" //res2: Thread=xpc10 state=X376:"376:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 580 | - | R0 CTRL | | //| 580 | 1276 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:580 read(46) | //| 581 | 1276 | R1 DATA | | //| 581+E | 1276 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:581 write(46, E49) | //| 582 | 1276 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X377:"377:xpc10" 1277 : major_start_pcl=583 edge_private_start/end=-1/-1 exec=583 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X377:"377:xpc10" //res2: Thread=xpc10 state=X377:"377:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 583 | - | R0 CTRL | | //| 583 | 1277 | R0 DATA | | //| 583+E | 1277 | W0 DATA | TMm1.V_2_GP te=te:583 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X378:"378:xpc10" 1278 : major_start_pcl=584 edge_private_start/end=585/586 exec=585 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X378:"378:xpc10" //res2: Thread=xpc10 state=X378:"378:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 584 | - | R0 CTRL | | //| 584 | 1278 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:584 read(47) | //| 585 | 1278 | R1 DATA | | //| 585+E | 1278 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:585 write(47, E50) | //| 586 | 1278 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X379:"379:xpc10" 1279 : major_start_pcl=587 edge_private_start/end=-1/-1 exec=587 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X379:"379:xpc10" //res2: Thread=xpc10 state=X379:"379:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 587 | - | R0 CTRL | | //| 587 | 1279 | R0 DATA | | //| 587+E | 1279 | W0 DATA | TMm1.V_2_GP te=te:587 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X380:"380:xpc10" 1280 : major_start_pcl=588 edge_private_start/end=-1/-1 exec=588 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X380:"380:xpc10" //res2: Thread=xpc10 state=X380:"380:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 588 | - | R0 CTRL | | //| 588 | 1280 | R0 DATA | | //| 588+E | 1280 | W0 DATA | TMp1.V_0_GP te=te:588 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X381:"381:xpc10" 1281 : major_start_pcl=589 edge_private_start/end=-1/-1 exec=589 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X381:"381:xpc10" //res2: Thread=xpc10 state=X381:"381:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 589 | - | R0 CTRL | | //| 589 | 1281 | R0 DATA | | //| 589+E | 1281 | W0 DATA | TMm1.V_2_GP te=te:589 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X382:"382:xpc10" 1282 : major_start_pcl=590 edge_private_start/end=591/592 exec=591 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X382:"382:xpc10" //res2: Thread=xpc10 state=X382:"382:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 590 | - | R0 CTRL | | //| 590 | 1282 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:590 read(48) | //| 591 | 1282 | R1 DATA | | //| 591+E | 1282 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:591 write(48, E51) | //| 592 | 1282 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X383:"383:xpc10" 1283 : major_start_pcl=593 edge_private_start/end=-1/-1 exec=593 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X383:"383:xpc10" //res2: Thread=xpc10 state=X383:"383:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 593 | - | R0 CTRL | | //| 593 | 1283 | R0 DATA | | //| 593+E | 1283 | W0 DATA | TMm1.V_2_GP te=te:593 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X384:"384:xpc10" 1284 : major_start_pcl=594 edge_private_start/end=595/596 exec=595 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X384:"384:xpc10" //res2: Thread=xpc10 state=X384:"384:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 594 | - | R0 CTRL | | //| 594 | 1284 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:594 read(49) | //| 595 | 1284 | R1 DATA | | //| 595+E | 1284 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:595 write(49, E52) | //| 596 | 1284 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X385:"385:xpc10" 1285 : major_start_pcl=597 edge_private_start/end=-1/-1 exec=597 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X385:"385:xpc10" //res2: Thread=xpc10 state=X385:"385:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 597 | - | R0 CTRL | | //| 597 | 1285 | R0 DATA | | //| 597+E | 1285 | W0 DATA | TMm1.V_2_GP te=te:597 scalarw(2) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X386:"386:xpc10" 1286 : major_start_pcl=598 edge_private_start/end=599/600 exec=599 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X386:"386:xpc10" //res2: Thread=xpc10 state=X386:"386:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 598 | - | R0 CTRL | | //| 598 | 1286 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:598 read(50) | //| 599 | 1286 | R1 DATA | | //| 599+E | 1286 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:599 write(50, E53) | //| 600 | 1286 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X387:"387:xpc10" 1287 : major_start_pcl=601 edge_private_start/end=-1/-1 exec=601 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X387:"387:xpc10" //res2: Thread=xpc10 state=X387:"387:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 601 | - | R0 CTRL | | //| 601 | 1287 | R0 DATA | | //| 601+E | 1287 | W0 DATA | TMm1.V_2_GP te=te:601 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X388:"388:xpc10" 1288 : major_start_pcl=602 edge_private_start/end=603/604 exec=603 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X388:"388:xpc10" //res2: Thread=xpc10 state=X388:"388:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 602 | - | R0 CTRL | | //| 602 | 1288 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:602 read(51) | //| 603 | 1288 | R1 DATA | | //| 603+E | 1288 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:603 write(51, E54) | //| 604 | 1288 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X389:"389:xpc10" 1289 : major_start_pcl=605 edge_private_start/end=-1/-1 exec=605 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X389:"389:xpc10" //res2: Thread=xpc10 state=X389:"389:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 605 | - | R0 CTRL | | //| 605 | 1289 | R0 DATA | | //| 605+E | 1289 | W0 DATA | TMm1.V_2_GP te=te:605 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X390:"390:xpc10" 1290 : major_start_pcl=606 edge_private_start/end=607/608 exec=607 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X390:"390:xpc10" //res2: Thread=xpc10 state=X390:"390:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 606 | - | R0 CTRL | | //| 606 | 1290 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:606 read(52) | //| 607 | 1290 | R1 DATA | | //| 607+E | 1290 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:607 write(52, E55) | //| 608 | 1290 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X391:"391:xpc10" 1291 : major_start_pcl=609 edge_private_start/end=-1/-1 exec=609 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X391:"391:xpc10" //res2: Thread=xpc10 state=X391:"391:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 609 | - | R0 CTRL | | //| 609 | 1291 | R0 DATA | | //| 609+E | 1291 | W0 DATA | TMm1.V_2_GP te=te:609 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X392:"392:xpc10" 1292 : major_start_pcl=610 edge_private_start/end=611/612 exec=611 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X392:"392:xpc10" //res2: Thread=xpc10 state=X392:"392:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 610 | - | R0 CTRL | | //| 610 | 1292 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:610 read(53) | //| 611 | 1292 | R1 DATA | | //| 611+E | 1292 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:611 write(53, E56) | //| 612 | 1292 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X393:"393:xpc10" 1293 : major_start_pcl=613 edge_private_start/end=-1/-1 exec=613 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X393:"393:xpc10" //res2: Thread=xpc10 state=X393:"393:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 613 | - | R0 CTRL | | //| 613 | 1293 | R0 DATA | | //| 613+E | 1293 | W0 DATA | TMm1.V_2_GP te=te:613 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X394:"394:xpc10" 1294 : major_start_pcl=614 edge_private_start/end=615/616 exec=615 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X394:"394:xpc10" //res2: Thread=xpc10 state=X394:"394:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 614 | - | R0 CTRL | | //| 614 | 1294 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:614 read(54) | //| 615 | 1294 | R1 DATA | | //| 615+E | 1294 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:615 write(54, E7) | //| 616 | 1294 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X395:"395:xpc10" 1295 : major_start_pcl=617 edge_private_start/end=-1/-1 exec=617 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X395:"395:xpc10" //res2: Thread=xpc10 state=X395:"395:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 617 | - | R0 CTRL | | //| 617 | 1295 | R0 DATA | | //| 617+E | 1295 | W0 DATA | TMm1.V_2_GP te=te:617 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X396:"396:xpc10" 1296 : major_start_pcl=618 edge_private_start/end=619/620 exec=619 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X396:"396:xpc10" //res2: Thread=xpc10 state=X396:"396:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 618 | - | R0 CTRL | | //| 618 | 1296 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:618 read(55) | //| 619 | 1296 | R1 DATA | | //| 619+E | 1296 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:619 write(55, E57) | //| 620 | 1296 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X397:"397:xpc10" 1297 : major_start_pcl=621 edge_private_start/end=-1/-1 exec=621 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X397:"397:xpc10" //res2: Thread=xpc10 state=X397:"397:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 621 | - | R0 CTRL | | //| 621 | 1297 | R0 DATA | | //| 621+E | 1297 | W0 DATA | TMm1.V_2_GP te=te:621 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X398:"398:xpc10" 1298 : major_start_pcl=622 edge_private_start/end=-1/-1 exec=622 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X398:"398:xpc10" //res2: Thread=xpc10 state=X398:"398:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 622 | - | R0 CTRL | | //| 622 | 1298 | R0 DATA | | //| 622+E | 1298 | W0 DATA | TMp1.V_0_GP te=te:622 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X399:"399:xpc10" 1299 : major_start_pcl=623 edge_private_start/end=-1/-1 exec=623 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X399:"399:xpc10" //res2: Thread=xpc10 state=X399:"399:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 623 | - | R0 CTRL | | //| 623 | 1299 | R0 DATA | | //| 623+E | 1299 | W0 DATA | TMm1.V_2_GP te=te:623 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X400:"400:xpc10" 1300 : major_start_pcl=624 edge_private_start/end=625/626 exec=625 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X400:"400:xpc10" //res2: Thread=xpc10 state=X400:"400:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 624 | - | R0 CTRL | | //| 624 | 1300 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:624 read(56) | //| 625 | 1300 | R1 DATA | | //| 625+E | 1300 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:625 write(56, E58) | //| 626 | 1300 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X401:"401:xpc10" 1301 : major_start_pcl=627 edge_private_start/end=-1/-1 exec=627 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X401:"401:xpc10" //res2: Thread=xpc10 state=X401:"401:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 627 | - | R0 CTRL | | //| 627 | 1301 | R0 DATA | | //| 627+E | 1301 | W0 DATA | TMm1.V_2_GP te=te:627 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X402:"402:xpc10" 1302 : major_start_pcl=628 edge_private_start/end=629/630 exec=629 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X402:"402:xpc10" //res2: Thread=xpc10 state=X402:"402:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 628 | - | R0 CTRL | | //| 628 | 1302 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:628 read(57) | //| 629 | 1302 | R1 DATA | | //| 629+E | 1302 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:629 write(57, E59) | //| 630 | 1302 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X403:"403:xpc10" 1303 : major_start_pcl=631 edge_private_start/end=-1/-1 exec=631 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X403:"403:xpc10" //res2: Thread=xpc10 state=X403:"403:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 631 | - | R0 CTRL | | //| 631 | 1303 | R0 DATA | | //| 631+E | 1303 | W0 DATA | TMm1.V_2_GP te=te:631 scalarw(2) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X404:"404:xpc10" 1304 : major_start_pcl=632 edge_private_start/end=633/634 exec=633 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X404:"404:xpc10" //res2: Thread=xpc10 state=X404:"404:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 632 | - | R0 CTRL | | //| 632 | 1304 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:632 read(58) | //| 633 | 1304 | R1 DATA | | //| 633+E | 1304 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:633 write(58, E60) | //| 634 | 1304 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X405:"405:xpc10" 1305 : major_start_pcl=635 edge_private_start/end=-1/-1 exec=635 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X405:"405:xpc10" //res2: Thread=xpc10 state=X405:"405:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 635 | - | R0 CTRL | | //| 635 | 1305 | R0 DATA | | //| 635+E | 1305 | W0 DATA | TMm1.V_2_GP te=te:635 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X406:"406:xpc10" 1306 : major_start_pcl=636 edge_private_start/end=637/638 exec=637 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X406:"406:xpc10" //res2: Thread=xpc10 state=X406:"406:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 636 | - | R0 CTRL | | //| 636 | 1306 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:636 read(59) | //| 637 | 1306 | R1 DATA | | //| 637+E | 1306 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:637 write(59, E61) | //| 638 | 1306 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X407:"407:xpc10" 1307 : major_start_pcl=639 edge_private_start/end=-1/-1 exec=639 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X407:"407:xpc10" //res2: Thread=xpc10 state=X407:"407:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 639 | - | R0 CTRL | | //| 639 | 1307 | R0 DATA | | //| 639+E | 1307 | W0 DATA | TMm1.V_2_GP te=te:639 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X408:"408:xpc10" 1308 : major_start_pcl=640 edge_private_start/end=641/642 exec=641 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X408:"408:xpc10" //res2: Thread=xpc10 state=X408:"408:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 640 | - | R0 CTRL | | //| 640 | 1308 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:640 read(60) | //| 641 | 1308 | R1 DATA | | //| 641+E | 1308 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:641 write(60, E62) | //| 642 | 1308 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X409:"409:xpc10" 1309 : major_start_pcl=643 edge_private_start/end=-1/-1 exec=643 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X409:"409:xpc10" //res2: Thread=xpc10 state=X409:"409:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 643 | - | R0 CTRL | | //| 643 | 1309 | R0 DATA | | //| 643+E | 1309 | W0 DATA | TMm1.V_2_GP te=te:643 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X410:"410:xpc10" 1310 : major_start_pcl=644 edge_private_start/end=645/646 exec=645 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X410:"410:xpc10" //res2: Thread=xpc10 state=X410:"410:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 644 | - | R0 CTRL | | //| 644 | 1310 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:644 read(61) | //| 645 | 1310 | R1 DATA | | //| 645+E | 1310 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:645 write(61, E63) | //| 646 | 1310 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X411:"411:xpc10" 1311 : major_start_pcl=647 edge_private_start/end=-1/-1 exec=647 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X411:"411:xpc10" //res2: Thread=xpc10 state=X411:"411:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 647 | - | R0 CTRL | | //| 647 | 1311 | R0 DATA | | //| 647+E | 1311 | W0 DATA | TMm1.V_2_GP te=te:647 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X412:"412:xpc10" 1312 : major_start_pcl=648 edge_private_start/end=649/650 exec=649 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X412:"412:xpc10" //res2: Thread=xpc10 state=X412:"412:xpc10" //*-------+------+---------+-------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------* //| 648 | - | R0 CTRL | | //| 648 | 1312 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:648 read(62) | //| 649 | 1312 | R1 DATA | | //| 649+E | 1312 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:649 write(62, E64) | //| 650 | 1312 | W1 DATA | | //*-------+------+---------+-------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X413:"413:xpc10" 1313 : major_start_pcl=651 edge_private_start/end=-1/-1 exec=651 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X413:"413:xpc10" //res2: Thread=xpc10 state=X413:"413:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 651 | - | R0 CTRL | | //| 651 | 1313 | R0 DATA | | //| 651+E | 1313 | W0 DATA | TMm1.V_2_GP te=te:651 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X414:"414:xpc10" 1314 : major_start_pcl=652 edge_private_start/end=653/654 exec=653 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X414:"414:xpc10" //res2: Thread=xpc10 state=X414:"414:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 652 | - | R0 CTRL | | //| 652 | 1314 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:652 read(63) | //| 653 | 1314 | R1 DATA | | //| 653+E | 1314 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:653 write(63, E8) | //| 654 | 1314 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X415:"415:xpc10" 1315 : major_start_pcl=655 edge_private_start/end=-1/-1 exec=655 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X415:"415:xpc10" //res2: Thread=xpc10 state=X415:"415:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 655 | - | R0 CTRL | | //| 655 | 1315 | R0 DATA | | //| 655+E | 1315 | W0 DATA | TMm1.V_2_GP te=te:655 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X416:"416:xpc10" 1316 : major_start_pcl=656 edge_private_start/end=-1/-1 exec=656 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X416:"416:xpc10" //res2: Thread=xpc10 state=X416:"416:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 656 | - | R0 CTRL | | //| 656 | 1316 | R0 DATA | | //| 656+E | 1316 | W0 DATA | TMp1.V_0_GP te=te:656 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X417:"417:xpc10" 1317 : major_start_pcl=657 edge_private_start/end=-1/-1 exec=657 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X417:"417:xpc10" //res2: Thread=xpc10 state=X417:"417:xpc10" //*-------+------+---------+-----------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------------------------------* //| 657 | - | R0 CTRL | | //| 657 | 1317 | R0 DATA | | //| 657+E | 1317 | W0 DATA | PLI:Initial Coefficient ... PLI:L/U Decomposition - ... | //*-------+------+---------+-----------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X418:"418:xpc10" 1318 : major_start_pcl=658 edge_private_start/end=-1/-1 exec=658 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X418:"418:xpc10" //res2: Thread=xpc10 state=X418:"418:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 658 | - | R0 CTRL | | //| 658 | 1318 | R0 DATA | | //| 658+E | 1318 | W0 DATA | TMp1.V_0_GP te=te:658 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X419:"419:xpc10" 1319 : major_start_pcl=659 edge_private_start/end=-1/-1 exec=659 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X419:"419:xpc10" //res2: Thread=xpc10 state=X419:"419:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 659 | - | R0 CTRL | | //| 659 | 1319 | R0 DATA | | //| 659+E | 1319 | W0 DATA | TMm1.V_2_GP te=te:659 scalarw(0) PLI: | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X420:"420:xpc10" 1320 : major_start_pcl=660 edge_private_start/end=661/661 exec=661 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X420:"420:xpc10" //res2: Thread=xpc10 state=X420:"420:xpc10" //*-------+------+---------+------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------* //| 660 | - | R0 CTRL | | //| 660 | 1320 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:660 read(0) | //| 661 | 1320 | R1 DATA | | //| 661+E | 1320 | W0 DATA | PLI: %F | //*-------+------+---------+------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X421:"421:xpc10" 1321 : major_start_pcl=662 edge_private_start/end=-1/-1 exec=662 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X421:"421:xpc10" //res2: Thread=xpc10 state=X421:"421:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 662 | - | R0 CTRL | | //| 662 | 1321 | R0 DATA | | //| 662+E | 1321 | W0 DATA | TMm1.V_2_GP te=te:662 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X422:"422:xpc10" 1322 : major_start_pcl=663 edge_private_start/end=664/664 exec=664 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X422:"422:xpc10" //res2: Thread=xpc10 state=X422:"422:xpc10" //*-------+------+---------+------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------* //| 663 | - | R0 CTRL | | //| 663 | 1322 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:663 read(1) | //| 664 | 1322 | R1 DATA | | //| 664+E | 1322 | W0 DATA | PLI: %F | //*-------+------+---------+------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X423:"423:xpc10" 1323 : major_start_pcl=665 edge_private_start/end=-1/-1 exec=665 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X423:"423:xpc10" //res2: Thread=xpc10 state=X423:"423:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 665 | - | R0 CTRL | | //| 665 | 1323 | R0 DATA | | //| 665+E | 1323 | W0 DATA | TMm1.V_2_GP te=te:665 scalarw(2) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X424:"424:xpc10" 1324 : major_start_pcl=666 edge_private_start/end=667/667 exec=667 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X424:"424:xpc10" //res2: Thread=xpc10 state=X424:"424:xpc10" //*-------+------+---------+------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------* //| 666 | - | R0 CTRL | | //| 666 | 1324 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:666 read(2) | //| 667 | 1324 | R1 DATA | | //| 667+E | 1324 | W0 DATA | PLI: %F | //*-------+------+---------+------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X425:"425:xpc10" 1325 : major_start_pcl=668 edge_private_start/end=-1/-1 exec=668 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X425:"425:xpc10" //res2: Thread=xpc10 state=X425:"425:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 668 | - | R0 CTRL | | //| 668 | 1325 | R0 DATA | | //| 668+E | 1325 | W0 DATA | TMm1.V_2_GP te=te:668 scalarw(3) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X426:"426:xpc10" 1326 : major_start_pcl=669 edge_private_start/end=670/670 exec=670 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X426:"426:xpc10" //res2: Thread=xpc10 state=X426:"426:xpc10" //*-------+------+---------+------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------* //| 669 | - | R0 CTRL | | //| 669 | 1326 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:669 read(3) | //| 670 | 1326 | R1 DATA | | //| 670+E | 1326 | W0 DATA | PLI: %F | //*-------+------+---------+------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X427:"427:xpc10" 1327 : major_start_pcl=671 edge_private_start/end=-1/-1 exec=671 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X427:"427:xpc10" //res2: Thread=xpc10 state=X427:"427:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 671 | - | R0 CTRL | | //| 671 | 1327 | R0 DATA | | //| 671+E | 1327 | W0 DATA | TMm1.V_2_GP te=te:671 scalarw(4) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X428:"428:xpc10" 1328 : major_start_pcl=672 edge_private_start/end=673/673 exec=673 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X428:"428:xpc10" //res2: Thread=xpc10 state=X428:"428:xpc10" //*-------+------+---------+------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------* //| 672 | - | R0 CTRL | | //| 672 | 1328 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:672 read(4) | //| 673 | 1328 | R1 DATA | | //| 673+E | 1328 | W0 DATA | PLI: %F | //*-------+------+---------+------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X429:"429:xpc10" 1329 : major_start_pcl=674 edge_private_start/end=-1/-1 exec=674 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X429:"429:xpc10" //res2: Thread=xpc10 state=X429:"429:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 674 | - | R0 CTRL | | //| 674 | 1329 | R0 DATA | | //| 674+E | 1329 | W0 DATA | TMm1.V_2_GP te=te:674 scalarw(5) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X430:"430:xpc10" 1330 : major_start_pcl=675 edge_private_start/end=676/676 exec=676 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X430:"430:xpc10" //res2: Thread=xpc10 state=X430:"430:xpc10" //*-------+------+---------+------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------* //| 675 | - | R0 CTRL | | //| 675 | 1330 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:675 read(5) | //| 676 | 1330 | R1 DATA | | //| 676+E | 1330 | W0 DATA | PLI: %F | //*-------+------+---------+------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X431:"431:xpc10" 1331 : major_start_pcl=677 edge_private_start/end=-1/-1 exec=677 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X431:"431:xpc10" //res2: Thread=xpc10 state=X431:"431:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 677 | - | R0 CTRL | | //| 677 | 1331 | R0 DATA | | //| 677+E | 1331 | W0 DATA | TMm1.V_2_GP te=te:677 scalarw(6) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X432:"432:xpc10" 1332 : major_start_pcl=678 edge_private_start/end=679/679 exec=679 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X432:"432:xpc10" //res2: Thread=xpc10 state=X432:"432:xpc10" //*-------+------+---------+------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------* //| 678 | - | R0 CTRL | | //| 678 | 1332 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:678 read(6) | //| 679 | 1332 | R1 DATA | | //| 679+E | 1332 | W0 DATA | PLI: %F | //*-------+------+---------+------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X433:"433:xpc10" 1333 : major_start_pcl=680 edge_private_start/end=-1/-1 exec=680 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X433:"433:xpc10" //res2: Thread=xpc10 state=X433:"433:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 680 | - | R0 CTRL | | //| 680 | 1333 | R0 DATA | | //| 680+E | 1333 | W0 DATA | TMm1.V_2_GP te=te:680 scalarw(7) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X434:"434:xpc10" 1334 : major_start_pcl=681 edge_private_start/end=682/682 exec=682 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X434:"434:xpc10" //res2: Thread=xpc10 state=X434:"434:xpc10" //*-------+------+---------+------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------* //| 681 | - | R0 CTRL | | //| 681 | 1334 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:681 read(7) | //| 682 | 1334 | R1 DATA | | //| 682+E | 1334 | W0 DATA | PLI: %F | //*-------+------+---------+------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X435:"435:xpc10" 1335 : major_start_pcl=683 edge_private_start/end=-1/-1 exec=683 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X435:"435:xpc10" //res2: Thread=xpc10 state=X435:"435:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 683 | - | R0 CTRL | | //| 683 | 1335 | R0 DATA | | //| 683+E | 1335 | W0 DATA | TMm1.V_2_GP te=te:683 scalarw(8) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X436:"436:xpc10" 1336 : major_start_pcl=684 edge_private_start/end=-1/-1 exec=684 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X436:"436:xpc10" //res2: Thread=xpc10 state=X436:"436:xpc10" //*-------+------+---------+-------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------* //| 684 | - | R0 CTRL | | //| 684 | 1336 | R0 DATA | | //| 684+E | 1336 | W0 DATA | PLI: | //*-------+------+---------+-------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X437:"437:xpc10" 1337 : major_start_pcl=685 edge_private_start/end=-1/-1 exec=685 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X437:"437:xpc10" //res2: Thread=xpc10 state=X437:"437:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 685 | - | R0 CTRL | | //| 685 | 1337 | R0 DATA | | //| 685+E | 1337 | W0 DATA | TMp1.V_0_GP te=te:685 scalarw(1+TMp1.V_0_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X438:"438:xpc10" 1339 : major_start_pcl=686 edge_private_start/end=-1/-1 exec=686 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X438:"438:xpc10" 1338 : major_start_pcl=686 edge_private_start/end=-1/-1 exec=686 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X438:"438:xpc10" //res2: Thread=xpc10 state=X438:"438:xpc10" //*-------+------+---------+-----------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------* //| 686 | - | R0 CTRL | | //| 686 | 1338 | R0 DATA | | //| 686+E | 1338 | W0 DATA | PLI: | //| 686 | 1339 | R0 DATA | | //| 686+E | 1339 | W0 DATA | PLI: | //*-------+------+---------+-----------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X439:"439:xpc10" 1340 : major_start_pcl=687 edge_private_start/end=-1/-1 exec=687 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X439:"439:xpc10" //res2: Thread=xpc10 state=X439:"439:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 687 | - | R0 CTRL | | //| 687 | 1340 | R0 DATA | | //| 687+E | 1340 | W0 DATA | TMp1.V_0_GP te=te:687 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X440:"440:xpc10" 1342 : major_start_pcl=688 edge_private_start/end=689/689 exec=688 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X440:"440:xpc10" 1341 : major_start_pcl=688 edge_private_start/end=-1/-1 exec=688 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X440:"440:xpc10" //res2: Thread=xpc10 state=X440:"440:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 688 | - | R0 CTRL | | //| 688 | 1341 | R0 DATA | | //| 688+E | 1341 | W0 DATA | TMp1.V_0_GP te=te:688 scalarw(0) | //| 688 | 1342 | R0 DATA | | //| 688+E | 1342 | W0 DATA | @_FPD/CC/SCALbx32_ARA0 te=te:688 write(E65, 1) | //| 689 | 1342 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X441:"441:xpc10" 1344 : major_start_pcl=690 edge_private_start/end=-1/-1 exec=690 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X441:"441:xpc10" 1343 : major_start_pcl=690 edge_private_start/end=-1/-1 exec=690 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X441:"441:xpc10" //res2: Thread=xpc10 state=X441:"441:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 690 | - | R0 CTRL | | //| 690 | 1343 | R0 DATA | | //| 690+E | 1343 | W0 DATA | PLI:UU= | //| 690 | 1344 | R0 DATA | | //| 690+E | 1344 | W0 DATA | TMm1.V_2_GP te=te:690 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X442:"442:xpc10" 1345 : major_start_pcl=691 edge_private_start/end=-1/-1 exec=691 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X442:"442:xpc10" //res2: Thread=xpc10 state=X442:"442:xpc10" //*-------+------+---------+-----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------* //| 691 | - | R0 CTRL | | //| 691 | 1345 | R0 DATA | | //| 691+E | 1345 | W0 DATA | lTMTMaV_1_GP te=te:691 scalarw(0) | //*-------+------+---------+-----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X443:"443:xpc10" 1347 : major_start_pcl=692 edge_private_start/end=-1/-1 exec=692 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X443:"443:xpc10" 1346 : major_start_pcl=692 edge_private_start/end=-1/-1 exec=692 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X443:"443:xpc10" //res2: Thread=xpc10 state=X443:"443:xpc10" //*-------+------+---------+-----------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------* //| 692 | - | R0 CTRL | | //| 692 | 1346 | R0 DATA | | //| 692+E | 1346 | W0 DATA | PLI: | //| 692 | 1347 | R0 DATA | | //| 692+E | 1347 | W0 DATA | PLI: | //*-------+------+---------+-----------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X444:"444:xpc10" 1348 : major_start_pcl=693 edge_private_start/end=-1/-1 exec=693 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X444:"444:xpc10" //res2: Thread=xpc10 state=X444:"444:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 693 | - | R0 CTRL | | //| 693 | 1348 | R0 DATA | | //| 693+E | 1348 | W0 DATA | lTMTMaV_1_GP te=te:693 scalarw(0) PLI:LL= | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X445:"445:xpc10" 1350 : major_start_pcl=694 edge_private_start/end=-1/-1 exec=694 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X445:"445:xpc10" 1349 : major_start_pcl=694 edge_private_start/end=-1/-1 exec=694 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X445:"445:xpc10" //res2: Thread=xpc10 state=X445:"445:xpc10" //*-------+------+---------+-----------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------* //| 694 | - | R0 CTRL | | //| 694 | 1349 | R0 DATA | | //| 694+E | 1349 | W0 DATA | PLI: | //| 694 | 1350 | R0 DATA | | //| 694+E | 1350 | W0 DATA | PLI: | //*-------+------+---------+-----------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X446:"446:xpc10" 1351 : major_start_pcl=695 edge_private_start/end=-1/-1 exec=695 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X446:"446:xpc10" //res2: Thread=xpc10 state=X446:"446:xpc10" //*-------+------+---------+----------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------------------------* //| 695 | - | R0 CTRL | | //| 695 | 1351 | R0 DATA | | //| 695+E | 1351 | W0 DATA | lTMTMaV_1_GP te=te:695 scalarw(0) PLI:Recombine LL and RR:... | //*-------+------+---------+----------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X447:"447:xpc10" 1353 : major_start_pcl=696 edge_private_start/end=-1/-1 exec=696 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X447:"447:xpc10" 1352 : major_start_pcl=696 edge_private_start/end=-1/-1 exec=696 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X447:"447:xpc10" //res2: Thread=xpc10 state=X447:"447:xpc10" //*-------+------+---------+-----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------* //| 696 | - | R0 CTRL | | //| 696 | 1352 | R0 DATA | | //| 696+E | 1352 | W0 DATA | lTMTMaV_1_GP te=te:696 scalarw(0) | //| 696 | 1353 | R0 DATA | | //| 696+E | 1353 | W0 DATA | TMp1.V_0_GP te=te:696 scalarw(0) | //*-------+------+---------+-----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X448:"448:xpc10" 1355 : major_start_pcl=697 edge_private_start/end=-1/-1 exec=697 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X448:"448:xpc10" 1354 : major_start_pcl=697 edge_private_start/end=-1/-1 exec=697 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X448:"448:xpc10" //res2: Thread=xpc10 state=X448:"448:xpc10" //*-------+------+---------+-----------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------* //| 697 | - | R0 CTRL | | //| 697 | 1354 | R0 DATA | | //| 697+E | 1354 | W0 DATA | PLI: | //| 697 | 1355 | R0 DATA | | //| 697+E | 1355 | W0 DATA | PLI: | //*-------+------+---------+-----------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X449:"449:xpc10" 1356 : major_start_pcl=698 edge_private_start/end=-1/-1 exec=698 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X449:"449:xpc10" //res2: Thread=xpc10 state=X449:"449:xpc10" //*-------+------+---------+--------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------------------* //| 698 | - | R0 CTRL | | //| 698 | 1356 | R0 DATA | | //| 698+E | 1356 | W0 DATA | W/P:Coefficients Created PLI:Kiwi L/U demo - coef... | //*-------+------+---------+--------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X450:"450:xpc10" 1357 : major_start_pcl=699 edge_private_start/end=-1/-1 exec=699 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X450:"450:xpc10" //res2: Thread=xpc10 state=X450:"450:xpc10" //*-------+------+---------+-----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------* //| 699 | - | R0 CTRL | | //| 699 | 1357 | R0 DATA | | //| 699+E | 1357 | W0 DATA | lTMTMaV_1_GP te=te:699 scalarw(0) | //*-------+------+---------+-----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X451:"451:xpc10" 1359 : major_start_pcl=700 edge_private_start/end=-1/-1 exec=700 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X451:"451:xpc10" 1358 : major_start_pcl=700 edge_private_start/end=-1/-1 exec=700 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X451:"451:xpc10" //res2: Thread=xpc10 state=X451:"451:xpc10" //*-------+------+---------+------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------------* //| 700 | - | R0 CTRL | | //| 700 | 1358 | R0 DATA | | //| 700+E | 1358 | W0 DATA | PLI:Kiwi L/U demo - L/U ... W/P:ThreeTestsFinished | //| 700 | 1359 | R0 DATA | | //| 700+E | 1359 | W0 DATA | PLI: //Kiwi L/U demo - L/U... | //*-------+------+---------+------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X452:"452:xpc10" 1360 : major_start_pcl=701 edge_private_start/end=-1/-1 exec=701 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X452:"452:xpc10" //res2: Thread=xpc10 state=X452:"452:xpc10" //*-------+------+---------+-----------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------* //| 701 | - | R0 CTRL | | //| 701 | 1360 | R0 DATA | | //| 701+E | 1360 | W0 DATA | PLI:GSAI:hpr_sysexit | //*-------+------+---------+-----------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X453:"453:xpc10" 1361 : major_start_pcl=702 edge_private_start/end=-1/-1 exec=702 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X453:"453:xpc10" //res2: Thread=xpc10 state=X453:"453:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 702 | - | R0 CTRL | | //| 702 | 1361 | R0 DATA | | //| 702+E | 1361 | W0 DATA | TMp1.V_0_GP te=te:702 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X454:"454:xpc10" 1363 : major_start_pcl=703 edge_private_start/end=705/718 exec=717 (dend=14) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X454:"454:xpc10" 1362 : major_start_pcl=703 edge_private_start/end=704/704 exec=703 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X454:"454:xpc10" //res2: Thread=xpc10 state=X454:"454:xpc10" //*-------+------+----------+---------------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+----------+---------------------------------------------------------------------------------------------------------------------------------------* //| 703 | - | R0 CTRL | | //| 703 | 1362 | R0 DATA | | //| 703+E | 1362 | W0 DATA | @_FPD/CC/SCALbx38_ARD0 te=te:703 write(7, 2.71) | //| 704 | 1362 | W1 DATA | | //| 703 | 1363 | R0 DATA | fpcvt10 te=te:703 cvt(TMp1.V_0_GP) fpcvt12 te=te:703 cvt(lTMTMaV_1_GP) | //| 705 | 1363 | R1 DATA | | //| 706 | 1363 | R2 DATA | CVFPMULTIPLIER12 te=te:706 *fixed-func-ALU*(10, C64f(lTMTMaV_1_GP)) CVFPMULTIPLIER10 te=te:706 *fixed-func-ALU*(2, C64f(TMp1.V_0_GP)) | //| 707 | 1363 | R3 DATA | | //| 708 | 1363 | R4 DATA | | //| 709 | 1363 | R5 DATA | CVFPADDER20 te=te:709 *fixed-func-ALU*(2*(C64f(TMp1.V_0_GP)), 10*(C64f(lTMTMaV_1_GP))) | //| 710 | 1363 | R6 DATA | | //| 711 | 1363 | R7 DATA | | //| 712 | 1363 | R8 DATA | | //| 713 | 1363 | R9 DATA | CVFPADDER18 te=te:713 *fixed-func-ALU*(1, E66) | //| 714 | 1363 | R10 DATA | | //| 715 | 1363 | R11 DATA | | //| 716 | 1363 | R12 DATA | | //| 717 | 1363 | R13 DATA | | //| 717+E | 1363 | W0 DATA | @_FPD/CC/SCALbx38_ARD0 te=te:717 write(TMp1.V_0_GP, E67) | //| 718 | 1363 | W1 DATA | | //*-------+------+----------+---------------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X455:"455:xpc10" 1364 : major_start_pcl=719 edge_private_start/end=-1/-1 exec=719 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X455:"455:xpc10" //res2: Thread=xpc10 state=X455:"455:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 719 | - | R0 CTRL | | //| 719 | 1364 | R0 DATA | | //| 719+E | 1364 | W0 DATA | TMp1.V_0_GP te=te:719 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X456:"456:xpc10" 1366 : major_start_pcl=720 edge_private_start/end=723/724 exec=724 (dend=2) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X456:"456:xpc10" 1365 : major_start_pcl=720 edge_private_start/end=721/722 exec=721 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X456:"456:xpc10" //res2: Thread=xpc10 state=X456:"456:xpc10" //*-------+------+---------+----------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------------* //| 720 | - | R0 CTRL | | //| 720 | 1365 | R0 DATA | @_FPD/CC/SCALbx38_ARD0 te=te:720 read(0) | //| 721 | 1365 | R1 DATA | | //| 721+E | 1365 | W0 DATA | @_FPD/CC/SCALbx40_ARE0 te=te:721 write(0, E68) | //| 722 | 1365 | W1 DATA | | //| 720 | 1366 | R0 DATA | | //| 723 | 1366 | R1 DATA | @_FPD/CC/SCALbx38_ARD0 te=te:723 read(TMp1.V_0_GP) | //| 724 | 1366 | R2 DATA | | //| 724+E | 1366 | W0 DATA | PLI: test=%u target_rh... | //*-------+------+---------+----------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X457:"457:xpc10" 1367 : major_start_pcl=725 edge_private_start/end=-1/-1 exec=725 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X457:"457:xpc10" //res2: Thread=xpc10 state=X457:"457:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 725 | - | R0 CTRL | | //| 725 | 1367 | R0 DATA | | //| 725+E | 1367 | W0 DATA | TMp1.V_0_GP te=te:725 scalarw(1) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X458:"458:xpc10" 1369 : major_start_pcl=726 edge_private_start/end=-1/-1 exec=726 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X458:"458:xpc10" 1368 : major_start_pcl=726 edge_private_start/end=-1/-1 exec=726 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X458:"458:xpc10" //res2: Thread=xpc10 state=X458:"458:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 726 | - | R0 CTRL | | //| 726 | 1368 | R0 DATA | | //| 726+E | 1368 | W0 DATA | | //| 726 | 1369 | R0 DATA | | //| 726+E | 1369 | W0 DATA | TMm1.V_1_GP te=te:726 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X459:"459:xpc10" 1370 : major_start_pcl=727 edge_private_start/end=-1/-1 exec=727 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X459:"459:xpc10" //res2: Thread=xpc10 state=X459:"459:xpc10" //*-------+------+---------+-------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------* //| 727 | - | R0 CTRL | | //| 727 | 1370 | R0 DATA | | //| 727+E | 1370 | W0 DATA | PLI:{ PLI:After fwds subst= | //*-------+------+---------+-------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X460:"460:xpc10" 1371 : major_start_pcl=728 edge_private_start/end=-1/-1 exec=728 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X460:"460:xpc10" //res2: Thread=xpc10 state=X460:"460:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 728 | - | R0 CTRL | | //| 728 | 1371 | R0 DATA | | //| 728+E | 1371 | W0 DATA | TMp1.V_0_GP te=te:728 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X461:"461:xpc10" 1373 : major_start_pcl=729 edge_private_start/end=730/730 exec=730 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X461:"461:xpc10" 1372 : major_start_pcl=729 edge_private_start/end=-1/-1 exec=729 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X461:"461:xpc10" //res2: Thread=xpc10 state=X461:"461:xpc10" //*-------+------+---------+----------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------------* //| 729 | - | R0 CTRL | | //| 729 | 1372 | R0 DATA | | //| 729+E | 1372 | W0 DATA | | //| 729 | 1373 | R0 DATA | @_FPD/CC/SCALbx40_ARE0 te=te:729 read(TMp1.V_0_GP) | //| 730 | 1373 | R1 DATA | | //| 730+E | 1373 | W0 DATA | PLI:%F | //*-------+------+---------+----------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X462:"462:xpc10" 1374 : major_start_pcl=731 edge_private_start/end=-1/-1 exec=731 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X462:"462:xpc10" //res2: Thread=xpc10 state=X462:"462:xpc10" //*-------+------+---------+-----------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------------* //| 731 | - | R0 CTRL | | //| 731 | 1374 | R0 DATA | | //| 731+E | 1374 | W0 DATA | TMp1.V_0_GP te=te:731 scalarw(7) PLI:} | //*-------+------+---------+-----------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X463:"463:xpc10" 1376 : major_start_pcl=732 edge_private_start/end=-1/-1 exec=732 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X463:"463:xpc10" 1375 : major_start_pcl=732 edge_private_start/end=-1/-1 exec=732 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X463:"463:xpc10" //res2: Thread=xpc10 state=X463:"463:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 732 | - | R0 CTRL | | //| 732 | 1375 | R0 DATA | | //| 732+E | 1375 | W0 DATA | | //| 732 | 1376 | R0 DATA | | //| 732+E | 1376 | W0 DATA | TMm1.V_1_GP te=te:732 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X464:"464:xpc10" 1377 : major_start_pcl=733 edge_private_start/end=-1/-1 exec=733 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X464:"464:xpc10" //res2: Thread=xpc10 state=X464:"464:xpc10" //*-------+------+---------+-------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------* //| 733 | - | R0 CTRL | | //| 733 | 1377 | R0 DATA | | //| 733+E | 1377 | W0 DATA | PLI:{ PLI:After back subst= | //*-------+------+---------+-------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X465:"465:xpc10" 1378 : major_start_pcl=734 edge_private_start/end=-1/-1 exec=734 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X465:"465:xpc10" //res2: Thread=xpc10 state=X465:"465:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 734 | - | R0 CTRL | | //| 734 | 1378 | R0 DATA | | //| 734+E | 1378 | W0 DATA | TMp1.V_0_GP te=te:734 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X466:"466:xpc10" 1380 : major_start_pcl=735 edge_private_start/end=736/736 exec=736 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X466:"466:xpc10" 1379 : major_start_pcl=735 edge_private_start/end=-1/-1 exec=735 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X466:"466:xpc10" //res2: Thread=xpc10 state=X466:"466:xpc10" //*-------+------+---------+----------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------------* //| 735 | - | R0 CTRL | | //| 735 | 1379 | R0 DATA | | //| 735+E | 1379 | W0 DATA | | //| 735 | 1380 | R0 DATA | @_FPD/CC/SCALbx42_ARF0 te=te:735 read(TMp1.V_0_GP) | //| 736 | 1380 | R1 DATA | | //| 736+E | 1380 | W0 DATA | PLI:%F | //*-------+------+---------+----------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X467:"467:xpc10" 1381 : major_start_pcl=737 edge_private_start/end=-1/-1 exec=737 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X467:"467:xpc10" //res2: Thread=xpc10 state=X467:"467:xpc10" //*-------+------+---------+--------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------* //| 737 | - | R0 CTRL | | //| 737 | 1381 | R0 DATA | | //| 737+E | 1381 | W0 DATA | PLI:} | //*-------+------+---------+--------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X468:"468:xpc10" 1382 : major_start_pcl=738 edge_private_start/end=-1/-1 exec=738 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X468:"468:xpc10" //res2: Thread=xpc10 state=X468:"468:xpc10" //*-------+------+---------+---------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------------* //| 738 | - | R0 CTRL | | //| 738 | 1382 | R0 DATA | | //| 738+E | 1382 | W0 DATA | TMp1.V_0_GP te=te:738 scalarw(0) PLI:Substitute back - rh... | //*-------+------+---------+---------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X469:"469:xpc10" 1384 : major_start_pcl=739 edge_private_start/end=-1/-1 exec=739 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X469:"469:xpc10" 1383 : major_start_pcl=739 edge_private_start/end=-1/-1 exec=739 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X469:"469:xpc10" //res2: Thread=xpc10 state=X469:"469:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 739 | - | R0 CTRL | | //| 739 | 1383 | R0 DATA | | //| 739+E | 1383 | W0 DATA | PLI:{ | //| 739 | 1384 | R0 DATA | | //| 739+E | 1384 | W0 DATA | TMm1.V_1_GP te=te:739 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X470:"470:xpc10" 1385 : major_start_pcl=740 edge_private_start/end=-1/-1 exec=740 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X470:"470:xpc10" //res2: Thread=xpc10 state=X470:"470:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 740 | - | R0 CTRL | | //| 740 | 1385 | R0 DATA | | //| 740+E | 1385 | W0 DATA | TMp1.V_0_GP te=te:740 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X471:"471:xpc10" 1387 : major_start_pcl=741 edge_private_start/end=742/742 exec=742 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X471:"471:xpc10" 1386 : major_start_pcl=741 edge_private_start/end=-1/-1 exec=741 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X471:"471:xpc10" //res2: Thread=xpc10 state=X471:"471:xpc10" //*-------+------+---------+----------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------------* //| 741 | - | R0 CTRL | | //| 741 | 1386 | R0 DATA | | //| 741+E | 1386 | W0 DATA | | //| 741 | 1387 | R0 DATA | @_FPD/CC/SCALbx46_ARH0 te=te:741 read(TMp1.V_0_GP) | //| 742 | 1387 | R1 DATA | | //| 742+E | 1387 | W0 DATA | PLI:%F | //*-------+------+---------+----------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X472:"472:xpc10" 1388 : major_start_pcl=743 edge_private_start/end=-1/-1 exec=743 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X472:"472:xpc10" //res2: Thread=xpc10 state=X472:"472:xpc10" //*-------+------+---------+-------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-------------------------------------------------------* //| 743 | - | R0 CTRL | | //| 743 | 1388 | R0 DATA | | //| 743+E | 1388 | W0 DATA | lTMTMaV_1_GP te=te:743 scalarw(1+lTMTMaV_1_GP) PLI:} | //*-------+------+---------+-------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X473:"473:xpc10" 1390 : major_start_pcl=744 edge_private_start/end=-1/-1 exec=744 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X473:"473:xpc10" 1389 : major_start_pcl=744 edge_private_start/end=-1/-1 exec=744 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X473:"473:xpc10" //res2: Thread=xpc10 state=X473:"473:xpc10" //*-------+------+---------+------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------------* //| 744 | - | R0 CTRL | | //| 744 | 1389 | R0 DATA | | //| 744+E | 1389 | W0 DATA | PLI:Kiwi L/U demo - L/U ... W/P:ThreeTestsFinished | //| 744 | 1390 | R0 DATA | | //| 744+E | 1390 | W0 DATA | PLI: //Kiwi L/U demo - L/U... | //*-------+------+---------+------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X474:"474:xpc10" 1391 : major_start_pcl=745 edge_private_start/end=-1/-1 exec=745 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X474:"474:xpc10" //res2: Thread=xpc10 state=X474:"474:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 745 | - | R0 CTRL | | //| 745 | 1391 | R0 DATA | | //| 745+E | 1391 | W0 DATA | TMp1.V_0_GP te=te:745 scalarw(1+TMp1.V_0_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X475:"475:xpc10" 1393 : major_start_pcl=746 edge_private_start/end=747/747 exec=747 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X475:"475:xpc10" 1392 : major_start_pcl=746 edge_private_start/end=-1/-1 exec=746 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X475:"475:xpc10" //res2: Thread=xpc10 state=X475:"475:xpc10" //*-------+------+---------+----------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------------* //| 746 | - | R0 CTRL | | //| 746 | 1392 | R0 DATA | | //| 746+E | 1392 | W0 DATA | | //| 746 | 1393 | R0 DATA | @_FPD/CC/SCALbx46_ARH0 te=te:746 read(TMp1.V_0_GP) | //| 747 | 1393 | R1 DATA | | //| 747+E | 1393 | W0 DATA | PLI:%F | //*-------+------+---------+----------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X476:"476:xpc10" 1394 : major_start_pcl=748 edge_private_start/end=-1/-1 exec=748 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X476:"476:xpc10" //res2: Thread=xpc10 state=X476:"476:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 748 | - | R0 CTRL | | //| 748 | 1394 | R0 DATA | | //| 748+E | 1394 | W0 DATA | TMm1.V_2_GP te=te:748 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X477:"477:xpc10" 1396 : major_start_pcl=749 edge_private_start/end=751/758 exec=758 (dend=8) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X477:"477:xpc10" 1395 : major_start_pcl=749 edge_private_start/end=750/750 exec=749 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X477:"477:xpc10" //res2: Thread=xpc10 state=X477:"477:xpc10" //*-------+------+---------+-----------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------------------------------------------------------------------* //| 749 | - | R0 CTRL | | //| 749 | 1395 | R0 DATA | | //| 749+E | 1395 | W0 DATA | @_FPD/CC/SCALbx46_ARH0 te=te:749 write(TMp1.V_0_GP, C64f(TMm1.V_1_GP)) | //| 750 | 1395 | W1 DATA | | //| 749 | 1396 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:749 read(E69) @_FPD/CC/SCALbx42_ARF0 te=te:749 read(TMm1.V_2_GP) | //| 751 | 1396 | R1 DATA | CVFPMULTIPLIER14 te=te:751 *fixed-func-ALU*(E70, E71) | //| 752 | 1396 | R2 DATA | | //| 753 | 1396 | R3 DATA | | //| 754 | 1396 | R4 DATA | CVFPADDER20 te=te:754 *fixed-func-ALU*(TMm1.V_1_GP, E72) | //| 755 | 1396 | R5 DATA | | //| 756 | 1396 | R6 DATA | | //| 757 | 1396 | R7 DATA | | //| 758 | 1396 | R8 DATA | | //| 758+E | 1396 | W0 DATA | TMm1.V_1_GP te=te:758 scalarw(E73) | //*-------+------+---------+-----------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X478:"478:xpc10" 1397 : major_start_pcl=759 edge_private_start/end=-1/-1 exec=759 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X478:"478:xpc10" //res2: Thread=xpc10 state=X478:"478:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 759 | - | R0 CTRL | | //| 759 | 1397 | R0 DATA | | //| 759+E | 1397 | W0 DATA | TMp1.V_0_GP te=te:759 scalarw(1+TMp1.V_0_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X479:"479:xpc10" 1399 : major_start_pcl=760 edge_private_start/end=-1/-1 exec=760 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X479:"479:xpc10" 1398 : major_start_pcl=760 edge_private_start/end=-1/-1 exec=760 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X479:"479:xpc10" //res2: Thread=xpc10 state=X479:"479:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 760 | - | R0 CTRL | | //| 760 | 1398 | R0 DATA | | //| 760+E | 1398 | W0 DATA | PLI:{ | //| 760 | 1399 | R0 DATA | | //| 760+E | 1399 | W0 DATA | TMm1.V_1_GP te=te:760 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X480:"480:xpc10" 1400 : major_start_pcl=761 edge_private_start/end=-1/-1 exec=761 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X480:"480:xpc10" //res2: Thread=xpc10 state=X480:"480:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 761 | - | R0 CTRL | | //| 761 | 1400 | R0 DATA | | //| 761+E | 1400 | W0 DATA | TMm1.V_2_GP te=te:761 scalarw(1+TMm1.V_2_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X481:"481:xpc10" 1402 : major_start_pcl=762 edge_private_start/end=764/771 exec=771 (dend=8) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X481:"481:xpc10" 1401 : major_start_pcl=762 edge_private_start/end=763/763 exec=762 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X481:"481:xpc10" //res2: Thread=xpc10 state=X481:"481:xpc10" //*-------+------+---------+-----------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------------------------------------------------------------------* //| 762 | - | R0 CTRL | | //| 762 | 1401 | R0 DATA | | //| 762+E | 1401 | W0 DATA | @_FPD/CC/SCALbx46_ARH0 te=te:762 write(TMp1.V_0_GP, C64f(TMm1.V_1_GP)) | //| 763 | 1401 | W1 DATA | | //| 762 | 1402 | R0 DATA | @_FPD/CC/SCALbx44_ARG0 te=te:762 read(E69) @_FPD/CC/SCALbx42_ARF0 te=te:762 read(TMm1.V_2_GP) | //| 764 | 1402 | R1 DATA | CVFPMULTIPLIER16 te=te:764 *fixed-func-ALU*(E70, E71) | //| 765 | 1402 | R2 DATA | | //| 766 | 1402 | R3 DATA | | //| 767 | 1402 | R4 DATA | CVFPADDER20 te=te:767 *fixed-func-ALU*(TMm1.V_1_GP, E72) | //| 768 | 1402 | R5 DATA | | //| 769 | 1402 | R6 DATA | | //| 770 | 1402 | R7 DATA | | //| 771 | 1402 | R8 DATA | | //| 771+E | 1402 | W0 DATA | TMm1.V_1_GP te=te:771 scalarw(E73) | //*-------+------+---------+-----------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X482:"482:xpc10" 1403 : major_start_pcl=772 edge_private_start/end=-1/-1 exec=772 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X482:"482:xpc10" //res2: Thread=xpc10 state=X482:"482:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 772 | - | R0 CTRL | | //| 772 | 1403 | R0 DATA | | //| 772+E | 1403 | W0 DATA | TMp1.V_0_GP te=te:772 scalarw(1+TMp1.V_0_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X483:"483:xpc10" 1405 : major_start_pcl=773 edge_private_start/end=774/774 exec=774 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X483:"483:xpc10" 1404 : major_start_pcl=773 edge_private_start/end=-1/-1 exec=773 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X483:"483:xpc10" //res2: Thread=xpc10 state=X483:"483:xpc10" //*-------+------+---------+----------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------------* //| 773 | - | R0 CTRL | | //| 773 | 1404 | R0 DATA | | //| 773+E | 1404 | W0 DATA | | //| 773 | 1405 | R0 DATA | @_FPD/CC/SCALbx42_ARF0 te=te:773 read(TMp1.V_0_GP) | //| 774 | 1405 | R1 DATA | | //| 774+E | 1405 | W0 DATA | PLI:%F | //*-------+------+---------+----------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X484:"484:xpc10" 1406 : major_start_pcl=775 edge_private_start/end=-1/-1 exec=775 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X484:"484:xpc10" //res2: Thread=xpc10 state=X484:"484:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 775 | - | R0 CTRL | | //| 775 | 1406 | R0 DATA | | //| 775+E | 1406 | W0 DATA | TMm1.V_2_GP te=te:775 scalarw(1+TMp1.V_0_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X485:"485:xpc10" 1408 : major_start_pcl=776 edge_private_start/end=788/796 exec=796 (dend=9) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X485:"485:xpc10" 1407 : major_start_pcl=776 edge_private_start/end=777/787 exec=786 (dend=11) //Simple greedy schedule for res2: Thread=xpc10 state=X485:"485:xpc10" //res2: Thread=xpc10 state=X485:"485:xpc10" //*-------+------+----------+-----------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+----------+-----------------------------------------------------------------------------------------------* //| 776 | - | R0 CTRL | | //| 776 | 1407 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:776 read(E65) @_FPD/CC/SCALbx40_ARE0 te=te:776 read(TMp1.V_0_GP) | //| 777 | 1407 | R1 DATA | CVFPADDER20 te=te:777 *fixed-func-ALU*(E74, -TMm1.V_1_GP) | //| 778 | 1407 | R2 DATA | | //| 779 | 1407 | R3 DATA | | //| 780 | 1407 | R4 DATA | | //| 781 | 1407 | R5 DATA | CVFPDIVIDER10 te=te:781 *fixed-func-ALU*(E75, E76) | //| 782 | 1407 | R6 DATA | | //| 783 | 1407 | R7 DATA | | //| 784 | 1407 | R8 DATA | | //| 785 | 1407 | R9 DATA | | //| 786 | 1407 | R10 DATA | | //| 786+E | 1407 | W0 DATA | @_FPD/CC/SCALbx42_ARF0 te=te:786 write(TMp1.V_0_GP, E77) | //| 787 | 1407 | W1 DATA | | //| 776 | 1408 | R0 DATA | @_FPD/CC/SCALbx42_ARF0 te=te:776 read(TMm1.V_2_GP) | //| 788 | 1408 | R1 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:788 read(E69) | //| 789 | 1408 | R2 DATA | CVFPMULTIPLIER18 te=te:789 *fixed-func-ALU*(E71, E78) | //| 790 | 1408 | R3 DATA | | //| 791 | 1408 | R4 DATA | | //| 792 | 1408 | R5 DATA | CVFPADDER18 te=te:792 *fixed-func-ALU*(TMm1.V_1_GP, E79) | //| 793 | 1408 | R6 DATA | | //| 794 | 1408 | R7 DATA | | //| 795 | 1408 | R8 DATA | | //| 796 | 1408 | R9 DATA | | //| 796+E | 1408 | W0 DATA | TMm1.V_1_GP te=te:796 scalarw(E80) | //*-------+------+----------+-----------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X486:"486:xpc10" 1409 : major_start_pcl=797 edge_private_start/end=-1/-1 exec=797 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X486:"486:xpc10" //res2: Thread=xpc10 state=X486:"486:xpc10" //*-------+------+---------+-----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------------------* //| 797 | - | R0 CTRL | | //| 797 | 1409 | R0 DATA | | //| 797+E | 1409 | W0 DATA | TMp1.V_0_GP te=te:797 scalarw(-1+TMp1.V_0_GP) | //*-------+------+---------+-----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X487:"487:xpc10" 1411 : major_start_pcl=798 edge_private_start/end=-1/-1 exec=798 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X487:"487:xpc10" 1410 : major_start_pcl=798 edge_private_start/end=-1/-1 exec=798 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X487:"487:xpc10" //res2: Thread=xpc10 state=X487:"487:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 798 | - | R0 CTRL | | //| 798 | 1410 | R0 DATA | | //| 798+E | 1410 | W0 DATA | | //| 798 | 1411 | R0 DATA | | //| 798+E | 1411 | W0 DATA | TMm1.V_1_GP te=te:798 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X488:"488:xpc10" 1412 : major_start_pcl=799 edge_private_start/end=-1/-1 exec=799 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X488:"488:xpc10" //res2: Thread=xpc10 state=X488:"488:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 799 | - | R0 CTRL | | //| 799 | 1412 | R0 DATA | | //| 799+E | 1412 | W0 DATA | TMm1.V_2_GP te=te:799 scalarw(1+TMm1.V_2_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X489:"489:xpc10" 1414 : major_start_pcl=800 edge_private_start/end=812/820 exec=820 (dend=9) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X489:"489:xpc10" 1413 : major_start_pcl=800 edge_private_start/end=801/811 exec=810 (dend=11) //Simple greedy schedule for res2: Thread=xpc10 state=X489:"489:xpc10" //res2: Thread=xpc10 state=X489:"489:xpc10" //*-------+------+----------+-----------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+----------+-----------------------------------------------------------------------------------------------* //| 800 | - | R0 CTRL | | //| 800 | 1413 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:800 read(E65) @_FPD/CC/SCALbx40_ARE0 te=te:800 read(TMp1.V_0_GP) | //| 801 | 1413 | R1 DATA | CVFPADDER20 te=te:801 *fixed-func-ALU*(E74, -TMm1.V_1_GP) | //| 802 | 1413 | R2 DATA | | //| 803 | 1413 | R3 DATA | | //| 804 | 1413 | R4 DATA | | //| 805 | 1413 | R5 DATA | CVFPDIVIDER12 te=te:805 *fixed-func-ALU*(E75, E76) | //| 806 | 1413 | R6 DATA | | //| 807 | 1413 | R7 DATA | | //| 808 | 1413 | R8 DATA | | //| 809 | 1413 | R9 DATA | | //| 810 | 1413 | R10 DATA | | //| 810+E | 1413 | W0 DATA | @_FPD/CC/SCALbx42_ARF0 te=te:810 write(TMp1.V_0_GP, E77) | //| 811 | 1413 | W1 DATA | | //| 800 | 1414 | R0 DATA | @_FPD/CC/SCALbx42_ARF0 te=te:800 read(TMm1.V_2_GP) | //| 812 | 1414 | R1 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:812 read(E69) | //| 813 | 1414 | R2 DATA | CVFPMULTIPLIER20 te=te:813 *fixed-func-ALU*(E71, E78) | //| 814 | 1414 | R3 DATA | | //| 815 | 1414 | R4 DATA | | //| 816 | 1414 | R5 DATA | CVFPADDER18 te=te:816 *fixed-func-ALU*(TMm1.V_1_GP, E79) | //| 817 | 1414 | R6 DATA | | //| 818 | 1414 | R7 DATA | | //| 819 | 1414 | R8 DATA | | //| 820 | 1414 | R9 DATA | | //| 820+E | 1414 | W0 DATA | TMm1.V_1_GP te=te:820 scalarw(E80) | //*-------+------+----------+-----------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X490:"490:xpc10" 1415 : major_start_pcl=821 edge_private_start/end=-1/-1 exec=821 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X490:"490:xpc10" //res2: Thread=xpc10 state=X490:"490:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 821 | - | R0 CTRL | | //| 821 | 1415 | R0 DATA | | //| 821+E | 1415 | W0 DATA | TMp1.V_0_GP te=te:821 scalarw(1+TMp1.V_0_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X491:"491:xpc10" 1417 : major_start_pcl=822 edge_private_start/end=823/823 exec=823 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X491:"491:xpc10" 1416 : major_start_pcl=822 edge_private_start/end=-1/-1 exec=822 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X491:"491:xpc10" //res2: Thread=xpc10 state=X491:"491:xpc10" //*-------+------+---------+----------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------------* //| 822 | - | R0 CTRL | | //| 822 | 1416 | R0 DATA | | //| 822+E | 1416 | W0 DATA | | //| 822 | 1417 | R0 DATA | @_FPD/CC/SCALbx40_ARE0 te=te:822 read(TMp1.V_0_GP) | //| 823 | 1417 | R1 DATA | | //| 823+E | 1417 | W0 DATA | PLI:%F | //*-------+------+---------+----------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X492:"492:xpc10" 1418 : major_start_pcl=824 edge_private_start/end=-1/-1 exec=824 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X492:"492:xpc10" //res2: Thread=xpc10 state=X492:"492:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 824 | - | R0 CTRL | | //| 824 | 1418 | R0 DATA | | //| 824+E | 1418 | W0 DATA | TMm1.V_2_GP te=te:824 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X493:"493:xpc10" 1420 : major_start_pcl=825 edge_private_start/end=832/839 exec=839 (dend=8) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X493:"493:xpc10" 1419 : major_start_pcl=825 edge_private_start/end=826/831 exec=830 (dend=6) //Simple greedy schedule for res2: Thread=xpc10 state=X493:"493:xpc10" //res2: Thread=xpc10 state=X493:"493:xpc10" //*-------+------+---------+-----------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------------------------------------------------------------------* //| 825 | - | R0 CTRL | | //| 825 | 1419 | R0 DATA | @_FPD/CC/SCALbx38_ARD0 te=te:825 read(TMp1.V_0_GP) | //| 826 | 1419 | R1 DATA | CVFPADDER20 te=te:826 *fixed-func-ALU*(E81, -TMm1.V_1_GP) | //| 827 | 1419 | R2 DATA | | //| 828 | 1419 | R3 DATA | | //| 829 | 1419 | R4 DATA | | //| 830 | 1419 | R5 DATA | | //| 830+E | 1419 | W0 DATA | @_FPD/CC/SCALbx40_ARE0 te=te:830 write(TMp1.V_0_GP, E82) | //| 831 | 1419 | W1 DATA | | //| 825 | 1420 | R0 DATA | @_FPD/CC/SCALbx32_ARA0 te=te:825 read(E69) @_FPD/CC/SCALbx40_ARE0 te=te:825 read(TMm1.V_2_GP) | //| 832 | 1420 | R1 DATA | CVFPMULTIPLIER22 te=te:832 *fixed-func-ALU*(E83, E84) | //| 833 | 1420 | R2 DATA | | //| 834 | 1420 | R3 DATA | | //| 835 | 1420 | R4 DATA | CVFPADDER18 te=te:835 *fixed-func-ALU*(TMm1.V_1_GP, E85) | //| 836 | 1420 | R5 DATA | | //| 837 | 1420 | R6 DATA | | //| 838 | 1420 | R7 DATA | | //| 839 | 1420 | R8 DATA | | //| 839+E | 1420 | W0 DATA | TMm1.V_1_GP te=te:839 scalarw(E86) | //*-------+------+---------+-----------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X494:"494:xpc10" 1421 : major_start_pcl=840 edge_private_start/end=-1/-1 exec=840 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X494:"494:xpc10" //res2: Thread=xpc10 state=X494:"494:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 840 | - | R0 CTRL | | //| 840 | 1421 | R0 DATA | | //| 840+E | 1421 | W0 DATA | TMp1.V_0_GP te=te:840 scalarw(1+TMp1.V_0_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X495:"495:xpc10" 1423 : major_start_pcl=841 edge_private_start/end=-1/-1 exec=841 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X495:"495:xpc10" 1422 : major_start_pcl=841 edge_private_start/end=-1/-1 exec=841 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X495:"495:xpc10" //res2: Thread=xpc10 state=X495:"495:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 841 | - | R0 CTRL | | //| 841 | 1422 | R0 DATA | | //| 841+E | 1422 | W0 DATA | | //| 841 | 1423 | R0 DATA | | //| 841+E | 1423 | W0 DATA | TMm1.V_1_GP te=te:841 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X496:"496:xpc10" 1424 : major_start_pcl=842 edge_private_start/end=-1/-1 exec=842 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X496:"496:xpc10" //res2: Thread=xpc10 state=X496:"496:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 842 | - | R0 CTRL | | //| 842 | 1424 | R0 DATA | | //| 842+E | 1424 | W0 DATA | TMm1.V_2_GP te=te:842 scalarw(1+TMm1.V_2_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X497:"497:xpc10" 1426 : major_start_pcl=843 edge_private_start/end=850/857 exec=857 (dend=8) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X497:"497:xpc10" 1425 : major_start_pcl=843 edge_private_start/end=844/849 exec=848 (dend=6) //Simple greedy schedule for res2: Thread=xpc10 state=X497:"497:xpc10" //res2: Thread=xpc10 state=X497:"497:xpc10" //*-------+------+---------+-----------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------------------------------------------------------------------* //| 843 | - | R0 CTRL | | //| 843 | 1425 | R0 DATA | @_FPD/CC/SCALbx38_ARD0 te=te:843 read(TMp1.V_0_GP) | //| 844 | 1425 | R1 DATA | CVFPADDER20 te=te:844 *fixed-func-ALU*(E81, -TMm1.V_1_GP) | //| 845 | 1425 | R2 DATA | | //| 846 | 1425 | R3 DATA | | //| 847 | 1425 | R4 DATA | | //| 848 | 1425 | R5 DATA | | //| 848+E | 1425 | W0 DATA | @_FPD/CC/SCALbx40_ARE0 te=te:848 write(TMp1.V_0_GP, E82) | //| 849 | 1425 | W1 DATA | | //| 843 | 1426 | R0 DATA | @_FPD/CC/SCALbx32_ARA0 te=te:843 read(E69) @_FPD/CC/SCALbx40_ARE0 te=te:843 read(TMm1.V_2_GP) | //| 850 | 1426 | R1 DATA | CVFPMULTIPLIER24 te=te:850 *fixed-func-ALU*(E83, E84) | //| 851 | 1426 | R2 DATA | | //| 852 | 1426 | R3 DATA | | //| 853 | 1426 | R4 DATA | CVFPADDER18 te=te:853 *fixed-func-ALU*(TMm1.V_1_GP, E85) | //| 854 | 1426 | R5 DATA | | //| 855 | 1426 | R6 DATA | | //| 856 | 1426 | R7 DATA | | //| 857 | 1426 | R8 DATA | | //| 857+E | 1426 | W0 DATA | TMm1.V_1_GP te=te:857 scalarw(E86) | //*-------+------+---------+-----------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X498:"498:xpc10" 1427 : major_start_pcl=858 edge_private_start/end=-1/-1 exec=858 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X498:"498:xpc10" //res2: Thread=xpc10 state=X498:"498:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 858 | - | R0 CTRL | | //| 858 | 1427 | R0 DATA | | //| 858+E | 1427 | W0 DATA | TMp1.V_0_GP te=te:858 scalarw(1+TMp1.V_0_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X499:"499:xpc10" 1429 : major_start_pcl=859 edge_private_start/end=862/863 exec=863 (dend=2) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X499:"499:xpc10" 1428 : major_start_pcl=859 edge_private_start/end=860/861 exec=860 (dend=2) //Simple greedy schedule for res2: Thread=xpc10 state=X499:"499:xpc10" //res2: Thread=xpc10 state=X499:"499:xpc10" //*-------+------+---------+----------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------------* //| 859 | - | R0 CTRL | | //| 859 | 1428 | R0 DATA | @_FPD/CC/SCALbx38_ARD0 te=te:859 read(0) | //| 860 | 1428 | R1 DATA | | //| 860+E | 1428 | W0 DATA | @_FPD/CC/SCALbx40_ARE0 te=te:860 write(0, E68) | //| 861 | 1428 | W1 DATA | | //| 859 | 1429 | R0 DATA | | //| 862 | 1429 | R1 DATA | @_FPD/CC/SCALbx38_ARD0 te=te:862 read(TMp1.V_0_GP) | //| 863 | 1429 | R2 DATA | | //| 863+E | 1429 | W0 DATA | PLI: test=%u target_rh... | //*-------+------+---------+----------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X500:"500:xpc10" 1430 : major_start_pcl=864 edge_private_start/end=-1/-1 exec=864 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X500:"500:xpc10" //res2: Thread=xpc10 state=X500:"500:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 864 | - | R0 CTRL | | //| 864 | 1430 | R0 DATA | | //| 864+E | 1430 | W0 DATA | TMp1.V_0_GP te=te:864 scalarw(1+TMp1.V_0_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X501:"501:xpc10" 1432 : major_start_pcl=865 edge_private_start/end=867/880 exec=879 (dend=14) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X501:"501:xpc10" 1431 : major_start_pcl=865 edge_private_start/end=866/866 exec=865 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X501:"501:xpc10" //res2: Thread=xpc10 state=X501:"501:xpc10" //*-------+------+----------+---------------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+----------+---------------------------------------------------------------------------------------------------------------------------------------* //| 865 | - | R0 CTRL | | //| 865 | 1431 | R0 DATA | | //| 865+E | 1431 | W0 DATA | @_FPD/CC/SCALbx38_ARD0 te=te:865 write(7, 2.71) | //| 866 | 1431 | W1 DATA | | //| 865 | 1432 | R0 DATA | fpcvt14 te=te:865 cvt(TMp1.V_0_GP) fpcvt16 te=te:865 cvt(lTMTMaV_1_GP) | //| 867 | 1432 | R1 DATA | | //| 868 | 1432 | R2 DATA | CVFPMULTIPLIER28 te=te:868 *fixed-func-ALU*(10, C64f(lTMTMaV_1_GP)) CVFPMULTIPLIER26 te=te:868 *fixed-func-ALU*(2, C64f(TMp1.V_0_GP)) | //| 869 | 1432 | R3 DATA | | //| 870 | 1432 | R4 DATA | | //| 871 | 1432 | R5 DATA | CVFPADDER20 te=te:871 *fixed-func-ALU*(2*(C64f(TMp1.V_0_GP)), 10*(C64f(lTMTMaV_1_GP))) | //| 872 | 1432 | R6 DATA | | //| 873 | 1432 | R7 DATA | | //| 874 | 1432 | R8 DATA | | //| 875 | 1432 | R9 DATA | CVFPADDER18 te=te:875 *fixed-func-ALU*(1, E66) | //| 876 | 1432 | R10 DATA | | //| 877 | 1432 | R11 DATA | | //| 878 | 1432 | R12 DATA | | //| 879 | 1432 | R13 DATA | | //| 879+E | 1432 | W0 DATA | @_FPD/CC/SCALbx38_ARD0 te=te:879 write(TMp1.V_0_GP, E67) | //| 880 | 1432 | W1 DATA | | //*-------+------+----------+---------------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X502:"502:xpc10" 1433 : major_start_pcl=881 edge_private_start/end=-1/-1 exec=881 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X502:"502:xpc10" //res2: Thread=xpc10 state=X502:"502:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 881 | - | R0 CTRL | | //| 881 | 1433 | R0 DATA | | //| 881+E | 1433 | W0 DATA | TMp1.V_0_GP te=te:881 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X503:"503:xpc10" 1435 : major_start_pcl=882 edge_private_start/end=883/883 exec=883 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X503:"503:xpc10" 1434 : major_start_pcl=882 edge_private_start/end=-1/-1 exec=882 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X503:"503:xpc10" //res2: Thread=xpc10 state=X503:"503:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 882 | - | R0 CTRL | | //| 882 | 1434 | R0 DATA | | //| 882+E | 1434 | W0 DATA | PLI: | //| 882 | 1435 | R0 DATA | @_FPD/CC/SCALbx36_ARC0 te=te:882 read(E87) | //| 883 | 1435 | R1 DATA | | //| 883+E | 1435 | W0 DATA | PLI: %F | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X504:"504:xpc10" 1436 : major_start_pcl=884 edge_private_start/end=-1/-1 exec=884 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X504:"504:xpc10" //res2: Thread=xpc10 state=X504:"504:xpc10" //*-------+------+---------+------* //| pc | eno | Phaser | Work | //*-------+------+---------+------* //| 884 | - | R0 CTRL | | //| 884 | 1436 | R0 DATA | | //| 884+E | 1436 | W0 DATA | | //*-------+------+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X505:"505:xpc10" 1437 : major_start_pcl=885 edge_private_start/end=-1/-1 exec=885 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X505:"505:xpc10" //res2: Thread=xpc10 state=X505:"505:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 885 | - | R0 CTRL | | //| 885 | 1437 | R0 DATA | | //| 885+E | 1437 | W0 DATA | lTMTMaV_1_GP te=te:885 scalarw(1+lTMTMaV_1_GP) | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X506:"506:xpc10" 1439 : major_start_pcl=886 edge_private_start/end=-1/-1 exec=886 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X506:"506:xpc10" 1438 : major_start_pcl=886 edge_private_start/end=-1/-1 exec=886 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X506:"506:xpc10" //res2: Thread=xpc10 state=X506:"506:xpc10" //*-------+------+---------+-----------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------* //| 886 | - | R0 CTRL | | //| 886 | 1438 | R0 DATA | | //| 886+E | 1438 | W0 DATA | PLI: | //| 886 | 1439 | R0 DATA | | //| 886+E | 1439 | W0 DATA | PLI: | //*-------+------+---------+-----------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X507:"507:xpc10" 1440 : major_start_pcl=887 edge_private_start/end=-1/-1 exec=887 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X507:"507:xpc10" //res2: Thread=xpc10 state=X507:"507:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 887 | - | R0 CTRL | | //| 887 | 1440 | R0 DATA | | //| 887+E | 1440 | W0 DATA | TMp1.V_0_GP te=te:887 scalarw(1+TMp1.V_0_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X508:"508:xpc10" 1442 : major_start_pcl=888 edge_private_start/end=889/889 exec=889 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X508:"508:xpc10" 1441 : major_start_pcl=888 edge_private_start/end=-1/-1 exec=888 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X508:"508:xpc10" //res2: Thread=xpc10 state=X508:"508:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 888 | - | R0 CTRL | | //| 888 | 1441 | R0 DATA | | //| 888+E | 1441 | W0 DATA | PLI: | //| 888 | 1442 | R0 DATA | @_FPD/CC/SCALbx36_ARC0 te=te:888 read(E87) | //| 889 | 1442 | R1 DATA | | //| 889+E | 1442 | W0 DATA | PLI: %F | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X509:"509:xpc10" 1444 : major_start_pcl=890 edge_private_start/end=-1/-1 exec=890 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X509:"509:xpc10" 1443 : major_start_pcl=890 edge_private_start/end=-1/-1 exec=890 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X509:"509:xpc10" //res2: Thread=xpc10 state=X509:"509:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 890 | - | R0 CTRL | | //| 890 | 1443 | R0 DATA | | //| 890+E | 1443 | W0 DATA | lTMTMaV_1_GP te=te:890 scalarw(1+lTMTMaV_1_GP) | //| 890 | 1444 | R0 DATA | | //| 890+E | 1444 | W0 DATA | TMm1.V_1_GP te=te:890 scalarw(0) | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X510:"510:xpc10" 1446 : major_start_pcl=891 edge_private_start/end=-1/-1 exec=891 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X510:"510:xpc10" 1445 : major_start_pcl=891 edge_private_start/end=-1/-1 exec=891 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X510:"510:xpc10" //res2: Thread=xpc10 state=X510:"510:xpc10" //*-------+------+---------+-----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------* //| 891 | - | R0 CTRL | | //| 891 | 1445 | R0 DATA | | //| 891+E | 1445 | W0 DATA | lTMTMaV_1_GP te=te:891 scalarw(0) | //| 891 | 1446 | R0 DATA | | //| 891+E | 1446 | W0 DATA | TMp1.V_0_GP te=te:891 scalarw(0) | //*-------+------+---------+-----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X511:"511:xpc10" 1447 : major_start_pcl=892 edge_private_start/end=-1/-1 exec=892 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X511:"511:xpc10" //res2: Thread=xpc10 state=X511:"511:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 892 | - | R0 CTRL | | //| 892 | 1447 | R0 DATA | | //| 892+E | 1447 | W0 DATA | TMm1.V_2_GP te=te:892 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X512:"512:xpc10" 1449 : major_start_pcl=893 edge_private_start/end=895/902 exec=902 (dend=8) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X512:"512:xpc10" 1448 : major_start_pcl=893 edge_private_start/end=894/894 exec=893 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X512:"512:xpc10" //res2: Thread=xpc10 state=X512:"512:xpc10" //*-------+------+---------+---------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------------------------------------* //| 893 | - | R0 CTRL | | //| 893 | 1448 | R0 DATA | | //| 893+E | 1448 | W0 DATA | @_FPD/CC/SCALbx36_ARC0 te=te:893 write(E87, C64f(TMm1.V_1_GP)) | //| 894 | 1448 | W1 DATA | | //| 893 | 1449 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:893 read(E88) @_FPD/CC/SCALbx32_ARA0 te=te:893 read(E89) | //| 895 | 1449 | R1 DATA | CVFPMULTIPLIER28 te=te:895 *fixed-func-ALU*(E90, E91) | //| 896 | 1449 | R2 DATA | | //| 897 | 1449 | R3 DATA | | //| 898 | 1449 | R4 DATA | CVFPADDER20 te=te:898 *fixed-func-ALU*(TMm1.V_1_GP, E92) | //| 899 | 1449 | R5 DATA | | //| 900 | 1449 | R6 DATA | | //| 901 | 1449 | R7 DATA | | //| 902 | 1449 | R8 DATA | | //| 902+E | 1449 | W0 DATA | TMm1.V_1_GP te=te:902 scalarw(E93) | //*-------+------+---------+---------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X513:"513:xpc10" 1450 : major_start_pcl=903 edge_private_start/end=-1/-1 exec=903 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X513:"513:xpc10" //res2: Thread=xpc10 state=X513:"513:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 903 | - | R0 CTRL | | //| 903 | 1450 | R0 DATA | | //| 903+E | 1450 | W0 DATA | TMp1.V_0_GP te=te:903 scalarw(1+TMp1.V_0_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X514:"514:xpc10" 1452 : major_start_pcl=904 edge_private_start/end=-1/-1 exec=904 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X514:"514:xpc10" 1451 : major_start_pcl=904 edge_private_start/end=-1/-1 exec=904 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X514:"514:xpc10" //res2: Thread=xpc10 state=X514:"514:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 904 | - | R0 CTRL | | //| 904 | 1451 | R0 DATA | | //| 904+E | 1451 | W0 DATA | lTMTMaV_1_GP te=te:904 scalarw(1+lTMTMaV_1_GP) | //| 904 | 1452 | R0 DATA | | //| 904+E | 1452 | W0 DATA | TMm1.V_1_GP te=te:904 scalarw(0) | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X515:"515:xpc10" 1453 : major_start_pcl=905 edge_private_start/end=-1/-1 exec=905 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X515:"515:xpc10" //res2: Thread=xpc10 state=X515:"515:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 905 | - | R0 CTRL | | //| 905 | 1453 | R0 DATA | | //| 905+E | 1453 | W0 DATA | TMm1.V_2_GP te=te:905 scalarw(1+TMm1.V_2_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X516:"516:xpc10" 1455 : major_start_pcl=906 edge_private_start/end=908/915 exec=915 (dend=8) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X516:"516:xpc10" 1454 : major_start_pcl=906 edge_private_start/end=907/907 exec=906 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X516:"516:xpc10" //res2: Thread=xpc10 state=X516:"516:xpc10" //*-------+------+---------+---------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+---------------------------------------------------------------------------------------* //| 906 | - | R0 CTRL | | //| 906 | 1454 | R0 DATA | | //| 906+E | 1454 | W0 DATA | @_FPD/CC/SCALbx36_ARC0 te=te:906 write(E87, C64f(TMm1.V_1_GP)) | //| 907 | 1454 | W1 DATA | | //| 906 | 1455 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:906 read(E88) @_FPD/CC/SCALbx32_ARA0 te=te:906 read(E89) | //| 908 | 1455 | R1 DATA | CVFPMULTIPLIER28 te=te:908 *fixed-func-ALU*(E90, E91) | //| 909 | 1455 | R2 DATA | | //| 910 | 1455 | R3 DATA | | //| 911 | 1455 | R4 DATA | CVFPADDER20 te=te:911 *fixed-func-ALU*(TMm1.V_1_GP, E92) | //| 912 | 1455 | R5 DATA | | //| 913 | 1455 | R6 DATA | | //| 914 | 1455 | R7 DATA | | //| 915 | 1455 | R8 DATA | | //| 915+E | 1455 | W0 DATA | TMm1.V_1_GP te=te:915 scalarw(E93) | //*-------+------+---------+---------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X517:"517:xpc10" 1456 : major_start_pcl=916 edge_private_start/end=-1/-1 exec=916 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X517:"517:xpc10" //res2: Thread=xpc10 state=X517:"517:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 916 | - | R0 CTRL | | //| 916 | 1456 | R0 DATA | | //| 916+E | 1456 | W0 DATA | TMp1.V_0_GP te=te:916 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X518:"518:xpc10" 1458 : major_start_pcl=917 edge_private_start/end=918/918 exec=918 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X518:"518:xpc10" 1457 : major_start_pcl=917 edge_private_start/end=-1/-1 exec=917 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X518:"518:xpc10" //res2: Thread=xpc10 state=X518:"518:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 917 | - | R0 CTRL | | //| 917 | 1457 | R0 DATA | | //| 917+E | 1457 | W0 DATA | PLI: | //| 917 | 1458 | R0 DATA | @_FPD/CC/SCALbx32_ARA0 te=te:917 read(E87) | //| 918 | 1458 | R1 DATA | | //| 918+E | 1458 | W0 DATA | PLI: %F | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X519:"519:xpc10" 1459 : major_start_pcl=919 edge_private_start/end=-1/-1 exec=919 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X519:"519:xpc10" //res2: Thread=xpc10 state=X519:"519:xpc10" //*-------+------+---------+------* //| pc | eno | Phaser | Work | //*-------+------+---------+------* //| 919 | - | R0 CTRL | | //| 919 | 1459 | R0 DATA | | //| 919+E | 1459 | W0 DATA | | //*-------+------+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X520:"520:xpc10" 1460 : major_start_pcl=920 edge_private_start/end=-1/-1 exec=920 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X520:"520:xpc10" //res2: Thread=xpc10 state=X520:"520:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 920 | - | R0 CTRL | | //| 920 | 1460 | R0 DATA | | //| 920+E | 1460 | W0 DATA | lTMTMaV_1_GP te=te:920 scalarw(1+lTMTMaV_1_GP) | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X521:"521:xpc10" 1462 : major_start_pcl=921 edge_private_start/end=-1/-1 exec=921 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X521:"521:xpc10" 1461 : major_start_pcl=921 edge_private_start/end=-1/-1 exec=921 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X521:"521:xpc10" //res2: Thread=xpc10 state=X521:"521:xpc10" //*-------+------+---------+-----------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------* //| 921 | - | R0 CTRL | | //| 921 | 1461 | R0 DATA | | //| 921+E | 1461 | W0 DATA | PLI: | //| 921 | 1462 | R0 DATA | | //| 921+E | 1462 | W0 DATA | PLI: | //*-------+------+---------+-----------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X522:"522:xpc10" 1463 : major_start_pcl=922 edge_private_start/end=-1/-1 exec=922 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X522:"522:xpc10" //res2: Thread=xpc10 state=X522:"522:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 922 | - | R0 CTRL | | //| 922 | 1463 | R0 DATA | | //| 922+E | 1463 | W0 DATA | TMp1.V_0_GP te=te:922 scalarw(1+TMp1.V_0_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X523:"523:xpc10" 1465 : major_start_pcl=923 edge_private_start/end=924/924 exec=924 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X523:"523:xpc10" 1464 : major_start_pcl=923 edge_private_start/end=-1/-1 exec=923 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X523:"523:xpc10" //res2: Thread=xpc10 state=X523:"523:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 923 | - | R0 CTRL | | //| 923 | 1464 | R0 DATA | | //| 923+E | 1464 | W0 DATA | PLI: | //| 923 | 1465 | R0 DATA | @_FPD/CC/SCALbx32_ARA0 te=te:923 read(E87) | //| 924 | 1465 | R1 DATA | | //| 924+E | 1465 | W0 DATA | PLI: %F | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X524:"524:xpc10" 1466 : major_start_pcl=925 edge_private_start/end=-1/-1 exec=925 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X524:"524:xpc10" //res2: Thread=xpc10 state=X524:"524:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 925 | - | R0 CTRL | | //| 925 | 1466 | R0 DATA | | //| 925+E | 1466 | W0 DATA | TMp1.V_0_GP te=te:925 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X525:"525:xpc10" 1468 : major_start_pcl=926 edge_private_start/end=927/927 exec=927 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X525:"525:xpc10" 1467 : major_start_pcl=926 edge_private_start/end=-1/-1 exec=926 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X525:"525:xpc10" //res2: Thread=xpc10 state=X525:"525:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 926 | - | R0 CTRL | | //| 926 | 1467 | R0 DATA | | //| 926+E | 1467 | W0 DATA | PLI: | //| 926 | 1468 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:926 read(E87) | //| 927 | 1468 | R1 DATA | | //| 927+E | 1468 | W0 DATA | PLI: %F | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X526:"526:xpc10" 1469 : major_start_pcl=928 edge_private_start/end=-1/-1 exec=928 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X526:"526:xpc10" //res2: Thread=xpc10 state=X526:"526:xpc10" //*-------+------+---------+------* //| pc | eno | Phaser | Work | //*-------+------+---------+------* //| 928 | - | R0 CTRL | | //| 928 | 1469 | R0 DATA | | //| 928+E | 1469 | W0 DATA | | //*-------+------+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X527:"527:xpc10" 1470 : major_start_pcl=929 edge_private_start/end=-1/-1 exec=929 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X527:"527:xpc10" //res2: Thread=xpc10 state=X527:"527:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 929 | - | R0 CTRL | | //| 929 | 1470 | R0 DATA | | //| 929+E | 1470 | W0 DATA | lTMTMaV_1_GP te=te:929 scalarw(1+lTMTMaV_1_GP) | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X528:"528:xpc10" 1472 : major_start_pcl=930 edge_private_start/end=-1/-1 exec=930 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X528:"528:xpc10" 1471 : major_start_pcl=930 edge_private_start/end=-1/-1 exec=930 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X528:"528:xpc10" //res2: Thread=xpc10 state=X528:"528:xpc10" //*-------+------+---------+-----------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------* //| 930 | - | R0 CTRL | | //| 930 | 1471 | R0 DATA | | //| 930+E | 1471 | W0 DATA | PLI: | //| 930 | 1472 | R0 DATA | | //| 930+E | 1472 | W0 DATA | PLI: | //*-------+------+---------+-----------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X529:"529:xpc10" 1473 : major_start_pcl=931 edge_private_start/end=-1/-1 exec=931 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X529:"529:xpc10" //res2: Thread=xpc10 state=X529:"529:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 931 | - | R0 CTRL | | //| 931 | 1473 | R0 DATA | | //| 931+E | 1473 | W0 DATA | TMp1.V_0_GP te=te:931 scalarw(1+TMp1.V_0_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X530:"530:xpc10" 1475 : major_start_pcl=932 edge_private_start/end=933/933 exec=933 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X530:"530:xpc10" 1474 : major_start_pcl=932 edge_private_start/end=-1/-1 exec=932 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X530:"530:xpc10" //res2: Thread=xpc10 state=X530:"530:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 932 | - | R0 CTRL | | //| 932 | 1474 | R0 DATA | | //| 932+E | 1474 | W0 DATA | PLI: | //| 932 | 1475 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:932 read(E87) | //| 933 | 1475 | R1 DATA | | //| 933+E | 1475 | W0 DATA | PLI: %F | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X531:"531:xpc10" 1477 : major_start_pcl=934 edge_private_start/end=935/935 exec=934 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X531:"531:xpc10" 1476 : major_start_pcl=934 edge_private_start/end=-1/-1 exec=934 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X531:"531:xpc10" //res2: Thread=xpc10 state=X531:"531:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 934 | - | R0 CTRL | | //| 934 | 1476 | R0 DATA | | //| 934+E | 1476 | W0 DATA | TMm1.V_2_GP te=te:934 scalarw(1+TMp1.V_0_GP) | //| 934 | 1477 | R0 DATA | | //| 934+E | 1477 | W0 DATA | @_FPD/CC/SCALbx32_ARA0 te=te:934 write(E94, 1) | //| 935 | 1477 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X532:"532:xpc10" 1479 : major_start_pcl=936 edge_private_start/end=937/943 exec=943 (dend=7) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X532:"532:xpc10" 1478 : major_start_pcl=936 edge_private_start/end=-1/-1 exec=936 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X532:"532:xpc10" //res2: Thread=xpc10 state=X532:"532:xpc10" //*-------+------+---------+----------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------------* //| 936 | - | R0 CTRL | | //| 936 | 1478 | R0 DATA | | //| 936+E | 1478 | W0 DATA | TMp1.V_0_GP te=te:936 scalarw(1+TMp1.V_0_GP) | //| 936 | 1479 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:936 read(E88) | //| 937 | 1479 | R1 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:937 read(E65) | //| 938 | 1479 | R2 DATA | CVFPDIVIDER14 te=te:938 *fixed-func-ALU*(E90, E76) | //| 939 | 1479 | R3 DATA | | //| 940 | 1479 | R4 DATA | | //| 941 | 1479 | R5 DATA | | //| 942 | 1479 | R6 DATA | | //| 943 | 1479 | R7 DATA | | //| 943+E | 1479 | W0 DATA | TMm1.V_1_GP te=te:943 scalarw(E95) | //*-------+------+---------+----------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X533:"533:xpc10" 1481 : major_start_pcl=944 edge_private_start/end=-1/-1 exec=944 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X533:"533:xpc10" 1480 : major_start_pcl=944 edge_private_start/end=-1/-1 exec=944 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X533:"533:xpc10" //res2: Thread=xpc10 state=X533:"533:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 944 | - | R0 CTRL | | //| 944 | 1480 | R0 DATA | | //| 944+E | 1480 | W0 DATA | PLI:UU= | //| 944 | 1481 | R0 DATA | | //| 944+E | 1481 | W0 DATA | TMm1.V_2_GP te=te:944 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X534:"534:xpc10" 1482 : major_start_pcl=945 edge_private_start/end=946/946 exec=945 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X534:"534:xpc10" //res2: Thread=xpc10 state=X534:"534:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 945 | - | R0 CTRL | | //| 945 | 1482 | R0 DATA | | //| 945+E | 1482 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:945 write(E88, 0) | //| 946 | 1482 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X535:"535:xpc10" 1483 : major_start_pcl=947 edge_private_start/end=948/948 exec=947 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X535:"535:xpc10" //res2: Thread=xpc10 state=X535:"535:xpc10" //*-------+------+---------+----------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------------------------* //| 947 | - | R0 CTRL | | //| 947 | 1483 | R0 DATA | | //| 947+E | 1483 | W0 DATA | @_FPD/CC/SCALbx32_ARA0 te=te:947 write(E88, C64f(TMm1.V_1_GP)) | //| 948 | 1483 | W1 DATA | | //*-------+------+---------+----------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X536:"536:xpc10" 1484 : major_start_pcl=949 edge_private_start/end=-1/-1 exec=949 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X536:"536:xpc10" //res2: Thread=xpc10 state=X536:"536:xpc10" //*-------+------+---------+-----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+-----------------------------------------------* //| 949 | - | R0 CTRL | | //| 949 | 1484 | R0 DATA | | //| 949+E | 1484 | W0 DATA | lTMTMaV_1_GP te=te:949 scalarw(1+TMp1.V_0_GP) | //*-------+------+---------+-----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X537:"537:xpc10" 1486 : major_start_pcl=950 edge_private_start/end=951/960 exec=959 (dend=10) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X537:"537:xpc10" 1485 : major_start_pcl=950 edge_private_start/end=-1/-1 exec=950 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X537:"537:xpc10" //res2: Thread=xpc10 state=X537:"537:xpc10" //*-------+------+---------+----------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------------------------* //| 950 | - | R0 CTRL | | //| 950 | 1485 | R0 DATA | | //| 950+E | 1485 | W0 DATA | TMm1.V_2_GP te=te:950 scalarw(1+TMm1.V_2_GP) | //| 950 | 1486 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:950 read(E96) | //| 951 | 1486 | R1 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:951 read(E97) | //| 952 | 1486 | R2 DATA | CVFPMULTIPLIER28 te=te:952 *fixed-func-ALU*(E98, -TMm1.V_1_GP) | //| 953 | 1486 | R3 DATA | | //| 954 | 1486 | R4 DATA | | //| 955 | 1486 | R5 DATA | CVFPADDER20 te=te:955 *fixed-func-ALU*(E99, E100) | //| 956 | 1486 | R6 DATA | | //| 957 | 1486 | R7 DATA | | //| 958 | 1486 | R8 DATA | | //| 959 | 1486 | R9 DATA | | //| 959+E | 1486 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:959 write(E96, E101) | //| 960 | 1486 | W1 DATA | | //*-------+------+---------+----------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X538:"538:xpc10" 1488 : major_start_pcl=961 edge_private_start/end=962/968 exec=968 (dend=7) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X538:"538:xpc10" 1487 : major_start_pcl=961 edge_private_start/end=-1/-1 exec=961 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X538:"538:xpc10" //res2: Thread=xpc10 state=X538:"538:xpc10" //*-------+------+---------+----------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------------* //| 961 | - | R0 CTRL | | //| 961 | 1487 | R0 DATA | | //| 961+E | 1487 | W0 DATA | TMp1.V_0_GP te=te:961 scalarw(1+TMp1.V_0_GP) | //| 961 | 1488 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:961 read(E88) | //| 962 | 1488 | R1 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:962 read(E65) | //| 963 | 1488 | R2 DATA | CVFPDIVIDER16 te=te:963 *fixed-func-ALU*(E90, E76) | //| 964 | 1488 | R3 DATA | | //| 965 | 1488 | R4 DATA | | //| 966 | 1488 | R5 DATA | | //| 967 | 1488 | R6 DATA | | //| 968 | 1488 | R7 DATA | | //| 968+E | 1488 | W0 DATA | TMm1.V_1_GP te=te:968 scalarw(E95) | //*-------+------+---------+----------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X539:"539:xpc10" 1489 : major_start_pcl=969 edge_private_start/end=-1/-1 exec=969 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X539:"539:xpc10" //res2: Thread=xpc10 state=X539:"539:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 969 | - | R0 CTRL | | //| 969 | 1489 | R0 DATA | | //| 969+E | 1489 | W0 DATA | lTMTMaV_1_GP te=te:969 scalarw(1+lTMTMaV_1_GP) | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X540:"540:xpc10" 1491 : major_start_pcl=970 edge_private_start/end=971/980 exec=979 (dend=10) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X540:"540:xpc10" 1490 : major_start_pcl=970 edge_private_start/end=-1/-1 exec=970 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X540:"540:xpc10" //res2: Thread=xpc10 state=X540:"540:xpc10" //*-------+------+---------+----------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------------------------* //| 970 | - | R0 CTRL | | //| 970 | 1490 | R0 DATA | | //| 970+E | 1490 | W0 DATA | TMm1.V_2_GP te=te:970 scalarw(1+TMm1.V_2_GP) | //| 970 | 1491 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:970 read(E96) | //| 971 | 1491 | R1 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:971 read(E97) | //| 972 | 1491 | R2 DATA | CVFPMULTIPLIER28 te=te:972 *fixed-func-ALU*(E98, -TMm1.V_1_GP) | //| 973 | 1491 | R3 DATA | | //| 974 | 1491 | R4 DATA | | //| 975 | 1491 | R5 DATA | CVFPADDER20 te=te:975 *fixed-func-ALU*(E99, E100) | //| 976 | 1491 | R6 DATA | | //| 977 | 1491 | R7 DATA | | //| 978 | 1491 | R8 DATA | | //| 979 | 1491 | R9 DATA | | //| 979+E | 1491 | W0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:979 write(E96, E101) | //| 980 | 1491 | W1 DATA | | //*-------+------+---------+----------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X541:"541:xpc10" 1492 : major_start_pcl=981 edge_private_start/end=-1/-1 exec=981 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X541:"541:xpc10" //res2: Thread=xpc10 state=X541:"541:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 981 | - | R0 CTRL | | //| 981 | 1492 | R0 DATA | | //| 981+E | 1492 | W0 DATA | TMm1.V_2_GP te=te:981 scalarw(1+TMm1.V_2_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X542:"542:xpc10" 1494 : major_start_pcl=982 edge_private_start/end=983/983 exec=982 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X542:"542:xpc10" 1493 : major_start_pcl=982 edge_private_start/end=-1/-1 exec=982 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X542:"542:xpc10" //res2: Thread=xpc10 state=X542:"542:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 982 | - | R0 CTRL | | //| 982 | 1493 | R0 DATA | | //| 982+E | 1493 | W0 DATA | TMm1.V_2_GP te=te:982 scalarw(1+TMp1.V_0_GP) | //| 982 | 1494 | R0 DATA | | //| 982+E | 1494 | W0 DATA | @_FPD/CC/SCALbx32_ARA0 te=te:982 write(E94, 1) | //| 983 | 1494 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X543:"543:xpc10" 1495 : major_start_pcl=984 edge_private_start/end=-1/-1 exec=984 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X543:"543:xpc10" //res2: Thread=xpc10 state=X543:"543:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 984 | - | R0 CTRL | | //| 984 | 1495 | R0 DATA | | //| 984+E | 1495 | W0 DATA | TMp1.V_0_GP te=te:984 scalarw(1+TMp1.V_0_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X544:"544:xpc10" 1497 : major_start_pcl=985 edge_private_start/end=986/986 exec=985 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X544:"544:xpc10" 1496 : major_start_pcl=985 edge_private_start/end=-1/-1 exec=985 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X544:"544:xpc10" //res2: Thread=xpc10 state=X544:"544:xpc10" //*-------+------+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+------------------------------------------------* //| 985 | - | R0 CTRL | | //| 985 | 1496 | R0 DATA | | //| 985+E | 1496 | W0 DATA | TMp1.V_0_GP te=te:985 scalarw(0) | //| 985 | 1497 | R0 DATA | | //| 985+E | 1497 | W0 DATA | @_FPD/CC/SCALbx32_ARA0 te=te:985 write(E65, 1) | //| 986 | 1497 | W1 DATA | | //*-------+------+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X545:"545:xpc10" 1498 : major_start_pcl=987 edge_private_start/end=-1/-1 exec=987 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X545:"545:xpc10" //res2: Thread=xpc10 state=X545:"545:xpc10" //*-------+------+---------+----------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------* //| 987 | - | R0 CTRL | | //| 987 | 1498 | R0 DATA | | //| 987+E | 1498 | W0 DATA | TMm1.V_2_GP te=te:987 scalarw(0) | //*-------+------+---------+----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X546:"546:xpc10" 1500 : major_start_pcl=988 edge_private_start/end=989/989 exec=989 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X546:"546:xpc10" 1499 : major_start_pcl=988 edge_private_start/end=-1/-1 exec=988 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X546:"546:xpc10" //res2: Thread=xpc10 state=X546:"546:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 988 | - | R0 CTRL | | //| 988 | 1499 | R0 DATA | | //| 988+E | 1499 | W0 DATA | PLI: | //| 988 | 1500 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:988 read(E69) | //| 989 | 1500 | R1 DATA | | //| 989+E | 1500 | W0 DATA | PLI: %F | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X547:"547:xpc10" 1501 : major_start_pcl=990 edge_private_start/end=-1/-1 exec=990 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X547:"547:xpc10" //res2: Thread=xpc10 state=X547:"547:xpc10" //*-------+------+---------+------* //| pc | eno | Phaser | Work | //*-------+------+---------+------* //| 990 | - | R0 CTRL | | //| 990 | 1501 | R0 DATA | | //| 990+E | 1501 | W0 DATA | | //*-------+------+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X548:"548:xpc10" 1502 : major_start_pcl=991 edge_private_start/end=-1/-1 exec=991 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X548:"548:xpc10" //res2: Thread=xpc10 state=X548:"548:xpc10" //*-------+------+---------+----------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+----------------------------------------------* //| 991 | - | R0 CTRL | | //| 991 | 1502 | R0 DATA | | //| 991+E | 1502 | W0 DATA | TMm1.V_2_GP te=te:991 scalarw(1+TMm1.V_2_GP) | //*-------+------+---------+----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X549:"549:xpc10" 1504 : major_start_pcl=992 edge_private_start/end=993/993 exec=993 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X549:"549:xpc10" 1503 : major_start_pcl=992 edge_private_start/end=-1/-1 exec=992 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X549:"549:xpc10" //res2: Thread=xpc10 state=X549:"549:xpc10" //*-------+------+---------+--------------------------------------------* //| pc | eno | Phaser | Work | //*-------+------+---------+--------------------------------------------* //| 992 | - | R0 CTRL | | //| 992 | 1503 | R0 DATA | | //| 992+E | 1503 | W0 DATA | PLI: | //| 992 | 1504 | R0 DATA | @_FPD/CC/SCALbx34_ARB0 te=te:992 read(E69) | //| 993 | 1504 | R1 DATA | | //| 993+E | 1504 | W0 DATA | PLI: %F | //*-------+------+---------+--------------------------------------------* // //---------------------------------------------------------- //Report from enumbers::: //Concise expression alias report. // // E1 =.= C64f(@_FPD/CC/SCALbx44_ARG0[0]) // // E2 =.= C64f(@_FPD/CC/SCALbx44_ARG0[9]) // // E3 =.= C64f(@_FPD/CC/SCALbx44_ARG0[18]) // // E4 =.= C64f(@_FPD/CC/SCALbx44_ARG0[27]) // // E5 =.= C64f(@_FPD/CC/SCALbx44_ARG0[36]) // // E6 =.= C64f(@_FPD/CC/SCALbx44_ARG0[45]) // // E7 =.= C64f(@_FPD/CC/SCALbx44_ARG0[54]) // // E8 =.= C64f(@_FPD/CC/SCALbx44_ARG0[63]) // // E9 =.= C64f(@_FPD/CC/SCALbx44_ARG0[1]) // // E10 =.= C64f(@_FPD/CC/SCALbx44_ARG0[2]) // // E11 =.= C64f(@_FPD/CC/SCALbx44_ARG0[3]) // // E12 =.= C64f(@_FPD/CC/SCALbx44_ARG0[4]) // // E13 =.= C64f(@_FPD/CC/SCALbx44_ARG0[5]) // // E14 =.= C64f(@_FPD/CC/SCALbx44_ARG0[6]) // // E15 =.= C64f(@_FPD/CC/SCALbx44_ARG0[7]) // // E16 =.= C64f(@_FPD/CC/SCALbx44_ARG0[8]) // // E17 =.= C64f(@_FPD/CC/SCALbx44_ARG0[10]) // // E18 =.= C64f(@_FPD/CC/SCALbx44_ARG0[11]) // // E19 =.= C64f(@_FPD/CC/SCALbx44_ARG0[12]) // // E20 =.= C64f(@_FPD/CC/SCALbx44_ARG0[13]) // // E21 =.= C64f(@_FPD/CC/SCALbx44_ARG0[14]) // // E22 =.= C64f(@_FPD/CC/SCALbx44_ARG0[15]) // // E23 =.= C64f(@_FPD/CC/SCALbx44_ARG0[16]) // // E24 =.= C64f(@_FPD/CC/SCALbx44_ARG0[17]) // // E25 =.= C64f(@_FPD/CC/SCALbx44_ARG0[19]) // // E26 =.= C64f(@_FPD/CC/SCALbx44_ARG0[20]) // // E27 =.= C64f(@_FPD/CC/SCALbx44_ARG0[21]) // // E28 =.= C64f(@_FPD/CC/SCALbx44_ARG0[22]) // // E29 =.= C64f(@_FPD/CC/SCALbx44_ARG0[23]) // // E30 =.= C64f(@_FPD/CC/SCALbx44_ARG0[24]) // // E31 =.= C64f(@_FPD/CC/SCALbx44_ARG0[25]) // // E32 =.= C64f(@_FPD/CC/SCALbx44_ARG0[26]) // // E33 =.= C64f(@_FPD/CC/SCALbx44_ARG0[28]) // // E34 =.= C64f(@_FPD/CC/SCALbx44_ARG0[29]) // // E35 =.= C64f(@_FPD/CC/SCALbx44_ARG0[30]) // // E36 =.= C64f(@_FPD/CC/SCALbx44_ARG0[31]) // // E37 =.= C64f(@_FPD/CC/SCALbx44_ARG0[32]) // // E38 =.= C64f(@_FPD/CC/SCALbx44_ARG0[33]) // // E39 =.= C64f(@_FPD/CC/SCALbx44_ARG0[34]) // // E40 =.= C64f(@_FPD/CC/SCALbx44_ARG0[35]) // // E41 =.= C64f(@_FPD/CC/SCALbx44_ARG0[37]) // // E42 =.= C64f(@_FPD/CC/SCALbx44_ARG0[38]) // // E43 =.= C64f(@_FPD/CC/SCALbx44_ARG0[39]) // // E44 =.= C64f(@_FPD/CC/SCALbx44_ARG0[40]) // // E45 =.= C64f(@_FPD/CC/SCALbx44_ARG0[41]) // // E46 =.= C64f(@_FPD/CC/SCALbx44_ARG0[42]) // // E47 =.= C64f(@_FPD/CC/SCALbx44_ARG0[43]) // // E48 =.= C64f(@_FPD/CC/SCALbx44_ARG0[44]) // // E49 =.= C64f(@_FPD/CC/SCALbx44_ARG0[46]) // // E50 =.= C64f(@_FPD/CC/SCALbx44_ARG0[47]) // // E51 =.= C64f(@_FPD/CC/SCALbx44_ARG0[48]) // // E52 =.= C64f(@_FPD/CC/SCALbx44_ARG0[49]) // // E53 =.= C64f(@_FPD/CC/SCALbx44_ARG0[50]) // // E54 =.= C64f(@_FPD/CC/SCALbx44_ARG0[51]) // // E55 =.= C64f(@_FPD/CC/SCALbx44_ARG0[52]) // // E56 =.= C64f(@_FPD/CC/SCALbx44_ARG0[53]) // // E57 =.= C64f(@_FPD/CC/SCALbx44_ARG0[55]) // // E58 =.= C64f(@_FPD/CC/SCALbx44_ARG0[56]) // // E59 =.= C64f(@_FPD/CC/SCALbx44_ARG0[57]) // // E60 =.= C64f(@_FPD/CC/SCALbx44_ARG0[58]) // // E61 =.= C64f(@_FPD/CC/SCALbx44_ARG0[59]) // // E62 =.= C64f(@_FPD/CC/SCALbx44_ARG0[60]) // // E63 =.= C64f(@_FPD/CC/SCALbx44_ARG0[61]) // // E64 =.= C64f(@_FPD/CC/SCALbx44_ARG0[62]) // // E65 =.= C((C64u(TMp1.V_0_GP))+S64'8*(C64u(TMp1.V_0_GP))) // // E66 =.= 2*(C64f(TMp1.V_0_GP))+10*(C64f(lTMTMaV_1_GP)) // // E67 =.= 1+2*(C64f(TMp1.V_0_GP))+10*(C64f(lTMTMaV_1_GP)) // // E68 =.= C64f(@_FPD/CC/SCALbx38_ARD0[0]) // // E69 =.= C((C64u(TMm1.V_2_GP))+S64'8*(C64u(TMp1.V_0_GP))) // // E70 =.= @_FPD/CC/SCALbx44_ARG0[C((C64u(TMm1.V_2_GP))+S64'8*(C64u(TMp1.V_0_GP)))] // // E71 =.= @_FPD/CC/SCALbx42_ARF0[TMm1.V_2_GP] // // E72 =.= @_FPD/CC/SCALbx44_ARG0[C((C64u(TMm1.V_2_GP))+S64'8*(C64u(TMp1.V_0_GP)))]*@_FPD/CC/SCALbx42_ARF0[TMm1.V_2_GP] // // E73 =.= TMm1.V_1_GP+@_FPD/CC/SCALbx44_ARG0[C((C64u(TMm1.V_2_GP))+S64'8*(C64u(TMp1.V_0_GP)))]*@_FPD/CC/SCALbx42_ARF0[TMm1.V_2_GP] // // E74 =.= @_FPD/CC/SCALbx40_ARE0[TMp1.V_0_GP] // // E75 =.= @_FPD/CC/SCALbx40_ARE0[TMp1.V_0_GP]+-TMm1.V_1_GP // // E76 =.= @_FPD/CC/SCALbx34_ARB0[C((C64u(TMp1.V_0_GP))+S64'8*(C64u(TMp1.V_0_GP)))] // // E77 =.= (@_FPD/CC/SCALbx40_ARE0[TMp1.V_0_GP]+-TMm1.V_1_GP)/@_FPD/CC/SCALbx34_ARB0[C((C64u(TMp1.V_0_GP))+S64'8*(C64u(TMp1.V_0_GP)))] // // E78 =.= @_FPD/CC/SCALbx34_ARB0[C((C64u(TMm1.V_2_GP))+S64'8*(C64u(TMp1.V_0_GP)))] // // E79 =.= @_FPD/CC/SCALbx42_ARF0[TMm1.V_2_GP]*@_FPD/CC/SCALbx34_ARB0[C((C64u(TMm1.V_2_GP))+S64'8*(C64u(TMp1.V_0_GP)))] // // E80 =.= TMm1.V_1_GP+@_FPD/CC/SCALbx42_ARF0[TMm1.V_2_GP]*@_FPD/CC/SCALbx34_ARB0[C((C64u(TMm1.V_2_GP))+S64'8*(C64u(TMp1.V_0_GP)))] // // E81 =.= @_FPD/CC/SCALbx38_ARD0[TMp1.V_0_GP] // // E82 =.= @_FPD/CC/SCALbx38_ARD0[TMp1.V_0_GP]+-TMm1.V_1_GP // // E83 =.= @_FPD/CC/SCALbx40_ARE0[TMm1.V_2_GP] // // E84 =.= @_FPD/CC/SCALbx32_ARA0[C((C64u(TMm1.V_2_GP))+S64'8*(C64u(TMp1.V_0_GP)))] // // E85 =.= @_FPD/CC/SCALbx40_ARE0[TMm1.V_2_GP]*@_FPD/CC/SCALbx32_ARA0[C((C64u(TMm1.V_2_GP))+S64'8*(C64u(TMp1.V_0_GP)))] // // E86 =.= TMm1.V_1_GP+@_FPD/CC/SCALbx40_ARE0[TMm1.V_2_GP]*@_FPD/CC/SCALbx32_ARA0[C((C64u(TMm1.V_2_GP))+S64'8*(C64u(TMp1.V_0_GP)))] // // E87 =.= C((C64u(TMp1.V_0_GP))+S64'8*(C64u(lTMTMaV_1_GP))) // // E88 =.= C((C64u(TMp1.V_0_GP))+S64'8*(C64u(TMm1.V_2_GP))) // // E89 =.= C((C64u(TMm1.V_2_GP))+S64'8*(C64u(lTMTMaV_1_GP))) // // E90 =.= @_FPD/CC/SCALbx34_ARB0[C((C64u(TMp1.V_0_GP))+S64'8*(C64u(TMm1.V_2_GP)))] // // E91 =.= @_FPD/CC/SCALbx32_ARA0[C((C64u(TMm1.V_2_GP))+S64'8*(C64u(lTMTMaV_1_GP)))] // // E92 =.= @_FPD/CC/SCALbx34_ARB0[C((C64u(TMp1.V_0_GP))+S64'8*(C64u(TMm1.V_2_GP)))]*@_FPD/CC/SCALbx32_ARA0[C((C64u(TMm1.V_2_GP))+S64'8*(C64u(lTMTMaV_1_GP)))] // // E93 =.= TMm1.V_1_GP+@_FPD/CC/SCALbx34_ARB0[C((C64u(TMp1.V_0_GP))+S64'8*(C64u(TMm1.V_2_GP)))]*@_FPD/CC/SCALbx32_ARA0[C((C64u(TMm1.V_2_GP))+S64'8*(C64u(lTMTMaV_1_GP)))] // // E94 =.= C((C64u(TMm1.V_2_GP))+S64'8*(C64u(TMm1.V_2_GP))) // // E95 =.= @_FPD/CC/SCALbx34_ARB0[C((C64u(TMp1.V_0_GP))+S64'8*(C64u(TMm1.V_2_GP)))]/@_FPD/CC/SCALbx34_ARB0[C((C64u(TMp1.V_0_GP))+S64'8*(C64u(TMp1.V_0_GP)))] // // E96 =.= C((C64u(lTMTMaV_1_GP))+S64'8*(C64u(TMm1.V_2_GP))) // // E97 =.= C((C64u(lTMTMaV_1_GP))+S64'8*(C64u(TMp1.V_0_GP))) // // E98 =.= @_FPD/CC/SCALbx34_ARB0[C((C64u(lTMTMaV_1_GP))+S64'8*(C64u(TMp1.V_0_GP)))] // // E99 =.= @_FPD/CC/SCALbx34_ARB0[C((C64u(lTMTMaV_1_GP))+S64'8*(C64u(TMm1.V_2_GP)))] // // E100 =.= @_FPD/CC/SCALbx34_ARB0[C((C64u(lTMTMaV_1_GP))+S64'8*(C64u(TMp1.V_0_GP)))]*-TMm1.V_1_GP // // E101 =.= @_FPD/CC/SCALbx34_ARB0[C((C64u(lTMTMaV_1_GP))+S64'8*(C64u(TMm1.V_2_GP)))]+@_FPD/CC/SCALbx34_ARB0[C((C64u(lTMTMaV_1_GP))+S64'8*(C64u(TMp1.V_0_GP)))]*-TMm1.V_1_GP // //---------------------------------------------------------- //Report from verilog_render::: //1 vectors of width 10 // //107 vectors of width 1 // //83 vectors of width 64 // //4 vectors of width 6 // //4 vectors of width 32 // //4 vectors of width 3 // //96 bits in scalar variables // //Total state bits in module = 5689 bits. // //2136 continuously assigned (wire/non-state) bits // //Total number of leaf cells = 0 // //Major Statistics Report: //Thread .cctor uid=cctor10 has 2 CIL instructions in 1 basic blocks //Thread .cctor uid=cctor12 has 2 CIL instructions in 1 basic blocks //Thread .cctor uid=cctor14 has 23 CIL instructions in 1 basic blocks //Thread Main uid=Main10 has 398 CIL instructions in 120 basic blocks //Thread mpc10 has 550 bevelab control states (pauses) //Reindexed thread xpc10 with 994 minor control states // eof (HPR L/S Verilog)