// CBG Orangepath HPR L/S System // Verilog output file generated at 12/10/2016 09:31:00 // Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 0.2.16h : 9th-October-2016 Unix 3.13.0.65 // /home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/kiwic.exe -res2-loadstore-port-count=0 -vnl-resets=synchronous -vnl-roundtrip=disable -kiwic-cil-dump=combined -kiwic-kcode-dump=enable -kiwic-register-colours=1 -bevelab-default-pause-mode=soft -bevelab-soft-pause-threshold=39 -vnl-rootmodname=cordic1 -repack-to-roms=enable cordic.exe -vnl=cordic.v `timescale 1ns/1ns module cordic1(output reg done, input clk, input reset); function signed [63:0] hpr_abs1; input signed [63:0] hpr_abs1_a; hpr_abs1 = (hpr_abs1_a > 0) ? hpr_abs1_a: -hpr_abs1_a; endfunction function signed [63:0] rtl_sign_extend0; input [31:0] arg; rtl_sign_extend0 = { {32{arg[31]}}, arg[31:0] }; endfunction integer CTMT4Main_V_1; integer CTMT4Main_V_2; reg signed [63:0] CTMT4Main_V_3; reg signed [63:0] CTMTMaV_5_GP; reg TCsi3_9_V_0; reg signed [63:0] TCsi3_9_V_1; reg signed [63:0] CTMTMaV_4_GP; integer fastspilldup16_GP; reg signed [63:0] TCsi3_9_V_4; reg signed [63:0] TCsi3_9_V_5; reg signed [63:0] A_64_SS_CC_SCALbx14_ARC0[35:0]; reg signed [63:0] A_64_SS_CC_SCALbx12_ARB0[35:0]; reg signed [63:0] A_64_SS_CC_SCALbx10_ARA0[39:0]; reg [4:0] xpc10nz; always @(posedge clk ) begin //Start structure HPR cordic if (reset) begin CTMTMaV_4_GP <= 64'd0; fastspilldup16_GP <= 32'd0; TCsi3_9_V_4 <= 64'd0; TCsi3_9_V_5 <= 64'd0; TCsi3_9_V_1 <= 64'd0; TCsi3_9_V_0 <= 32'd0; CTMT4Main_V_3 <= 64'd0; CTMTMaV_5_GP <= 64'd0; CTMT4Main_V_1 <= 32'd0; CTMT4Main_V_2 <= 32'd0; done <= 32'd0; xpc10nz <= 32'd0; end else begin case (xpc10nz) 5'sd11/*11:xpc10nz*/: begin if ((CTMT4Main_V_1==32'sd36/*36:CTMT4Main_V_1*/) && (CTMT4Main_V_2>=32'sh24)) $display("Result: %1d/%1d", CTMT4Main_V_1 , 32'sh24); if ((CTMT4Main_V_1==32'sd36/*36:CTMT4Main_V_1*/) && (CTMT4Main_V_2>=32'sh24)) begin $display("RESULT: PASS"); $display("cordic: Testbench finished"); end if ((CTMT4Main_V_1!=32'sd36/*36:CTMT4Main_V_1*/) && (CTMT4Main_V_2>=32'sh24)) $display("Result: %1d/%1d" , CTMT4Main_V_1, 32'sh24); if ((CTMT4Main_V_1!=32'sd36/*36:CTMT4Main_V_1*/) && (CTMT4Main_V_2>=32'sh24)) begin $display("RESULT: FAIL"); $display("cordic: Testbench finished"); end end 5'sd13/*13:xpc10nz*/: $finish(32'sd0); endcase if ((64'sh_1388<CTMTMaV_5_GP)) begin if ((xpc10nz==5'sd10/*10:xpc10nz*/)) begin $display("Test: input=%1d expected=%1d output=%1d ", A_64_SS_CC_SCALbx12_ARB0[CTMT4Main_V_2], CTMT4Main_V_3 , CTMTMaV_4_GP); $display(" test %1d error=%1d", CTMT4Main_V_2, CTMTMaV_5_GP); end end else if ((xpc10nz==5'sd10/*10:xpc10nz*/)) $display("Test: input=%1d expected=%1d output=%1d ", A_64_SS_CC_SCALbx12_ARB0 [CTMT4Main_V_2], CTMT4Main_V_3, CTMTMaV_4_GP); case (xpc10nz) 5'sd2/*2:xpc10nz*/: $display("cordic: Testbench start"); 5'sd4/*4:xpc10nz*/: begin if ((CTMTMaV_5_GP>=64'sh0) && (CTMTMaV_5_GP<64'sh_3925_2e48_6db4) && (CTMTMaV_5_GP<64'sh_1c92_9724_36da) && (CTMTMaV_5_GP <64'she49_4b92_1b6d)) begin CTMTMaV_4_GP <= 64'sh0; fastspilldup16_GP <= 32'sd0; TCsi3_9_V_4 <= 64'sh2_284b_177a_e2c2; TCsi3_9_V_5 <= 64'sh2_284b_177a_e2c2; TCsi3_9_V_1 <= 64'sh2_284b_177a_e2c2; TCsi3_9_V_0 <= 1'h0; CTMTMaV_5_GP <= CTMTMaV_5_GP+(0-A_64_SS_CC_SCALbx10_ARA0[64'sd0]); xpc10nz <= 5'sd6/*6:xpc10nz*/; end if ((CTMTMaV_5_GP<64'sh0) && (-64'sh_1c92_9724_36da+CTMTMaV_5_GP<64'sh_3925_2e48_6db4) && (-64'sh_1c92_9724_36da +CTMTMaV_5_GP>=64'sh_1c92_9724_36da) && (-64'sh_3925_2e48_6db4+CTMTMaV_5_GP<64'she49_4b92_1b6d)) begin TCsi3_9_V_1 <= 64'sh2_284b_177a_e2c2; TCsi3_9_V_0 <= 32'd0; CTMTMaV_5_GP <= -64'sh_3925_2e48_6db4+CTMTMaV_5_GP; xpc10nz <= 5'sd19/*19:xpc10nz*/; end if ((CTMTMaV_5_GP<64'sh0) && (-64'sh_1c92_9724_36da+CTMTMaV_5_GP<64'she49_4b92_1b6d) && (-64'sh_1c92_9724_36da +CTMTMaV_5_GP<64'sh_3925_2e48_6db4) && (-64'sh_1c92_9724_36da+CTMTMaV_5_GP<64'sh_1c92_9724_36da)) begin TCsi3_9_V_1 <= 64'sh2_284b_177a_e2c2; TCsi3_9_V_0 <= 32'd1; CTMTMaV_5_GP <= -64'sh_1c92_9724_36da+CTMTMaV_5_GP; xpc10nz <= 5'sd19/*19:xpc10nz*/; end if ((CTMTMaV_5_GP>=64'sh0) && (CTMTMaV_5_GP<64'sh_3925_2e48_6db4) && (CTMTMaV_5_GP>=64'sh_1c92_9724_36da ) && (-64'sh_1c92_9724_36da+CTMTMaV_5_GP<64'she49_4b92_1b6d)) begin TCsi3_9_V_1 <= 64'sh2_284b_177a_e2c2; TCsi3_9_V_0 <= 32'd1; CTMTMaV_5_GP <= -64'sh_1c92_9724_36da+CTMTMaV_5_GP; xpc10nz <= 5'sd19/*19:xpc10nz*/; end if ((CTMTMaV_5_GP<64'sh0) && (-64'sh_1c92_9724_36da+CTMTMaV_5_GP<64'sh_3925_2e48_6db4) && (-64'sh_1c92_9724_36da +CTMTMaV_5_GP>=64'sh_1c92_9724_36da) && (-64'sh_3925_2e48_6db4+CTMTMaV_5_GP>=64'she49_4b92_1b6d)) begin TCsi3_9_V_0 <= 32'd0; CTMTMaV_5_GP <= 64'sh_55b7_c56c_a48e+(0-CTMTMaV_5_GP); xpc10nz <= 5'sd5/*5:xpc10nz*/; end if ((CTMTMaV_5_GP<64'sh0) && (-64'sh_1c92_9724_36da+CTMTMaV_5_GP>=64'she49_4b92_1b6d) && (-64'sh_1c92_9724_36da +CTMTMaV_5_GP<64'sh_3925_2e48_6db4) && (-64'sh_1c92_9724_36da+CTMTMaV_5_GP<64'sh_1c92_9724_36da)) begin TCsi3_9_V_0 <= 32'd1; CTMTMaV_5_GP <= 64'sh_3925_2e48_6db4+(0-CTMTMaV_5_GP); xpc10nz <= 5'sd5/*5:xpc10nz*/; end if ((CTMTMaV_5_GP<64'sh0) && (-64'sh_1c92_9724_36da+CTMTMaV_5_GP>=64'sh_3925_2e48_6db4)) begin TCsi3_9_V_0 <= 32'd1; CTMTMaV_5_GP <= -64'sh_55b7_c56c_a48e+CTMTMaV_5_GP; xpc10nz <= 5'sd20/*20:xpc10nz*/; end if ((CTMTMaV_5_GP>=64'sh0) && (CTMTMaV_5_GP<64'sh_3925_2e48_6db4) && (CTMTMaV_5_GP>=64'sh_1c92_9724_36da ) && (-64'sh_1c92_9724_36da+CTMTMaV_5_GP>=64'she49_4b92_1b6d)) begin TCsi3_9_V_0 <= 32'd1; CTMTMaV_5_GP <= 64'sh_3925_2e48_6db4+(0-CTMTMaV_5_GP); xpc10nz <= 5'sd5/*5:xpc10nz*/; end if ((CTMTMaV_5_GP>=64'sh0) && (CTMTMaV_5_GP<64'sh_3925_2e48_6db4) && (CTMTMaV_5_GP<64'sh_1c92_9724_36da ) && (CTMTMaV_5_GP>=64'she49_4b92_1b6d)) begin TCsi3_9_V_0 <= 1'h0; CTMTMaV_5_GP <= 64'sh_1c92_9724_36da+(0-CTMTMaV_5_GP); xpc10nz <= 5'sd5/*5:xpc10nz*/; end if ((CTMTMaV_5_GP>=64'sh0) && (CTMTMaV_5_GP>=64'sh_3925_2e48_6db4)) begin TCsi3_9_V_0 <= 1'h0; CTMTMaV_5_GP <= -64'sh_3925_2e48_6db4+CTMTMaV_5_GP; xpc10nz <= 5'sd20/*20:xpc10nz*/; end end 5'sd20/*20:xpc10nz*/: begin if ((CTMTMaV_5_GP>=64'sh0) && (CTMTMaV_5_GP<64'sh_3925_2e48_6db4) && (CTMTMaV_5_GP<64'sh_1c92_9724_36da) && (CTMTMaV_5_GP <64'she49_4b92_1b6d)) begin CTMTMaV_4_GP <= 64'sh0; fastspilldup16_GP <= 32'sd0; TCsi3_9_V_4 <= 64'sh2_284b_177a_e2c2; TCsi3_9_V_5 <= 64'sh2_284b_177a_e2c2; TCsi3_9_V_1 <= 64'sh2_284b_177a_e2c2; CTMTMaV_5_GP <= CTMTMaV_5_GP+(0-A_64_SS_CC_SCALbx10_ARA0[64'sd0]); xpc10nz <= 5'sd6/*6:xpc10nz*/; end if ((CTMTMaV_5_GP<64'sh0) && (CTMTMaV_5_GP<64'sh_3925_2e48_6db4) && (CTMTMaV_5_GP<64'sh_1c92_9724_36da) && (CTMTMaV_5_GP<64'she49_4b92_1b6d)) begin CTMTMaV_4_GP <= 64'sh0; fastspilldup16_GP <= 32'sd0; TCsi3_9_V_4 <= 64'sh2_284b_177a_e2c2; TCsi3_9_V_5 <= -64'sh2_284b_177a_e2c2; TCsi3_9_V_1 <= 64'sh2_284b_177a_e2c2; CTMTMaV_5_GP <= CTMTMaV_5_GP+A_64_SS_CC_SCALbx10_ARA0[64'sd0]; xpc10nz <= 5'sd18/*18:xpc10nz*/; end if ((CTMTMaV_5_GP<64'sh_3925_2e48_6db4) && (CTMTMaV_5_GP>=64'sh_1c92_9724_36da) && (-64'sh_1c92_9724_36da +CTMTMaV_5_GP>=64'she49_4b92_1b6d)) begin TCsi3_9_V_0 <= (TCsi3_9_V_0==32'sd0/*0:TCsi3.9_V_0*/); CTMTMaV_5_GP <= 64'sh_3925_2e48_6db4+(0-CTMTMaV_5_GP); xpc10nz <= 5'sd5/*5:xpc10nz*/; end if ((CTMTMaV_5_GP<64'sh_3925_2e48_6db4) && (CTMTMaV_5_GP>=64'sh_1c92_9724_36da) && (-64'sh_1c92_9724_36da +CTMTMaV_5_GP<64'she49_4b92_1b6d)) begin TCsi3_9_V_1 <= 64'sh2_284b_177a_e2c2; TCsi3_9_V_0 <= (TCsi3_9_V_0==32'sd0/*0:TCsi3.9_V_0*/); CTMTMaV_5_GP <= -64'sh_1c92_9724_36da+CTMTMaV_5_GP; end if ((CTMTMaV_5_GP<64'sh_3925_2e48_6db4) && (CTMTMaV_5_GP<64'sh_1c92_9724_36da) && (CTMTMaV_5_GP>=64'she49_4b92_1b6d )) begin TCsi3_9_V_1 <= 64'sh2_284b_177a_e2c2; CTMTMaV_5_GP <= 64'sh_1c92_9724_36da+(0-CTMTMaV_5_GP); end if ((CTMTMaV_5_GP>=64'sh_3925_2e48_6db4)) begin CTMTMaV_5_GP <= -64'sh_3925_2e48_6db4+CTMTMaV_5_GP; xpc10nz <= 5'sd20/*20:xpc10nz*/; end if (((CTMTMaV_5_GP<64'sh_1c92_9724_36da)? (CTMTMaV_5_GP>=64'she49_4b92_1b6d): (-64'sh_1c92_9724_36da+CTMTMaV_5_GP <64'she49_4b92_1b6d)) && (CTMTMaV_5_GP<64'sh_3925_2e48_6db4)) xpc10nz <= 5'sd19/*19:xpc10nz*/; end endcase if ((CTMTMaV_5_GP<64'sh0)) case (xpc10nz) 5'sd5/*5:xpc10nz*/: begin CTMTMaV_4_GP <= 64'sh0; fastspilldup16_GP <= 32'sd0; TCsi3_9_V_4 <= 64'sh2_284b_177a_e2c2; TCsi3_9_V_5 <= -64'sh2_284b_177a_e2c2; TCsi3_9_V_1 <= 64'sh2_284b_177a_e2c2; CTMTMaV_5_GP <= CTMTMaV_5_GP+A_64_SS_CC_SCALbx10_ARA0[64'sd0]; xpc10nz <= 5'sd18/*18:xpc10nz*/; end 5'sd19/*19:xpc10nz*/: begin CTMTMaV_4_GP <= 64'sh0; fastspilldup16_GP <= 32'sd0; TCsi3_9_V_4 <= 64'sh0+TCsi3_9_V_1; xpc10nz <= 5'sd16/*16:xpc10nz*/; end endcase else case (xpc10nz) 5'sd5/*5:xpc10nz*/: begin CTMTMaV_4_GP <= 64'sh0; fastspilldup16_GP <= 32'sd0; TCsi3_9_V_4 <= 64'sh2_284b_177a_e2c2; TCsi3_9_V_5 <= 64'sh2_284b_177a_e2c2; TCsi3_9_V_1 <= 64'sh2_284b_177a_e2c2; CTMTMaV_5_GP <= CTMTMaV_5_GP+(0-A_64_SS_CC_SCALbx10_ARA0[64'sd0]); xpc10nz <= 5'sd6/*6:xpc10nz*/; end 5'sd19/*19:xpc10nz*/: begin CTMTMaV_4_GP <= 64'sh0; fastspilldup16_GP <= 32'sd0; TCsi3_9_V_4 <= TCsi3_9_V_1; TCsi3_9_V_5 <= 64'sh0+TCsi3_9_V_1; xpc10nz <= 5'sd15/*15:xpc10nz*/; end endcase case (xpc10nz) 5'sd7/*7:xpc10nz*/: begin if (!TCsi3_9_V_0 && (fastspilldup16_GP>=32'sd40)) begin CTMTMaV_4_GP <= CTMTMaV_4_GP; CTMTMaV_5_GP <= rtl_sign_extend0(hpr_abs1(CTMTMaV_4_GP+(0-CTMT4Main_V_3))); xpc10nz <= 5'sd9/*9:xpc10nz*/; end if (TCsi3_9_V_0 && (fastspilldup16_GP>=32'sd40)) begin CTMTMaV_4_GP <= $signed((0-CTMTMaV_4_GP)); xpc10nz <= 5'sd8/*8:xpc10nz*/; end if ((CTMTMaV_5_GP>=64'sh0) && (fastspilldup16_GP<32'sd40)) begin TCsi3_9_V_4 <= TCsi3_9_V_1+(0-(CTMTMaV_4_GP>>>(32'sd63&fastspilldup16_GP))); xpc10nz <= 5'sd14/*14:xpc10nz*/; end if ((CTMTMaV_5_GP<64'sh0) && (fastspilldup16_GP<32'sd40)) begin TCsi3_9_V_4 <= TCsi3_9_V_1+(CTMTMaV_4_GP>>>(32'sd63&fastspilldup16_GP)); xpc10nz <= 5'sd16/*16:xpc10nz*/; end end 5'sd11/*11:xpc10nz*/: if ((CTMT4Main_V_2<32'sh24)) xpc10nz <= 5'sd3/*3:xpc10nz*/; else begin done <= 1'h1; xpc10nz <= 5'sd12/*12:xpc10nz*/; end endcase if ((64'sh_1388<CTMTMaV_5_GP)) begin if ((xpc10nz==5'sd9/*9:xpc10nz*/)) begin fastspilldup16_GP <= CTMT4Main_V_1; CTMT4Main_V_1 <= CTMT4Main_V_1; end end else if ((xpc10nz==5'sd9/*9:xpc10nz*/)) begin fastspilldup16_GP <= CTMT4Main_V_1; CTMT4Main_V_1 <= 32'sd1+CTMT4Main_V_1; end case (xpc10nz) 5'sd0/*0:xpc10nz*/: begin done <= 1'h0; xpc10nz <= 5'sd1/*1:xpc10nz*/; end 5'sd1/*1:xpc10nz*/: xpc10nz <= 5'sd2/*2:xpc10nz*/; 5'sd2/*2:xpc10nz*/: begin CTMT4Main_V_1 <= 32'sd0; CTMT4Main_V_2 <= 32'sd0; xpc10nz <= 5'sd3/*3:xpc10nz*/; end 5'sd3/*3:xpc10nz*/: begin CTMT4Main_V_3 <= $signed(A_64_SS_CC_SCALbx14_ARC0[CTMT4Main_V_2]); CTMTMaV_5_GP <= $signed(A_64_SS_CC_SCALbx12_ARB0[CTMT4Main_V_2]); xpc10nz <= 5'sd4/*4:xpc10nz*/; end 5'sd6/*6:xpc10nz*/: begin CTMTMaV_4_GP <= TCsi3_9_V_5; fastspilldup16_GP <= 32'sd1+fastspilldup16_GP; TCsi3_9_V_1 <= TCsi3_9_V_4; xpc10nz <= 5'sd7/*7:xpc10nz*/; end 5'sd8/*8:xpc10nz*/: begin CTMTMaV_5_GP <= rtl_sign_extend0(hpr_abs1(CTMTMaV_4_GP+(0-CTMT4Main_V_3))); xpc10nz <= 5'sd9/*9:xpc10nz*/; end 5'sd9/*9:xpc10nz*/: xpc10nz <= 5'sd10/*10:xpc10nz*/; 5'sd10/*10:xpc10nz*/: begin CTMT4Main_V_2 <= 32'sd1+CTMT4Main_V_2; xpc10nz <= 5'sd11/*11:xpc10nz*/; end 5'sd12/*12:xpc10nz*/: xpc10nz <= 5'sd13/*13:xpc10nz*/; 5'sd13/*13:xpc10nz*/: xpc10nz <= 5'sd13/*13:xpc10nz*/; 5'sd14/*14:xpc10nz*/: begin TCsi3_9_V_5 <= CTMTMaV_4_GP+(TCsi3_9_V_1>>>(32'sd63&fastspilldup16_GP)); xpc10nz <= 5'sd15/*15:xpc10nz*/; end 5'sd15/*15:xpc10nz*/: begin CTMTMaV_5_GP <= CTMTMaV_5_GP+(0-A_64_SS_CC_SCALbx10_ARA0[fastspilldup16_GP]); xpc10nz <= 5'sd6/*6:xpc10nz*/; end 5'sd16/*16:xpc10nz*/: begin TCsi3_9_V_5 <= CTMTMaV_4_GP+(0-(TCsi3_9_V_1>>>(32'sd63&fastspilldup16_GP))); xpc10nz <= 5'sd17/*17:xpc10nz*/; end 5'sd17/*17:xpc10nz*/: begin CTMTMaV_5_GP <= CTMTMaV_5_GP+A_64_SS_CC_SCALbx10_ARA0[fastspilldup16_GP]; xpc10nz <= 5'sd18/*18:xpc10nz*/; end 5'sd18/*18:xpc10nz*/: begin CTMTMaV_4_GP <= TCsi3_9_V_5; fastspilldup16_GP <= 32'sd1+fastspilldup16_GP; TCsi3_9_V_1 <= TCsi3_9_V_4; xpc10nz <= 5'sd7/*7:xpc10nz*/; end endcase end //End structure HPR cordic end initial begin //ROM data table: 40 words of 64 bits. A_64_SS_CC_SCALbx10_ARA0[0] = 64'h724_a5c9_0db6; A_64_SS_CC_SCALbx10_ARA0[1] = 64'h437_8382_a698; A_64_SS_CC_SCALbx10_ARA0[2] = 64'h23a_62a9_7465; A_64_SS_CC_SCALbx10_ARA0[3] = 64'h121_895a_4e7c; A_64_SS_CC_SCALbx10_ARA0[4] = 64'h91_5482_8d78; A_64_SS_CC_SCALbx10_ARA0[5] = 64'h48_bc64_495f; A_64_SS_CC_SCALbx10_ARA0[6] = 64'h24_6077_cb3d; A_64_SS_CC_SCALbx10_ARA0[7] = 64'h12_3084_a4a9; A_64_SS_CC_SCALbx10_ARA0[8] = 64'h9_184b_6a88; A_64_SS_CC_SCALbx10_ARA0[9] = 64'h4_8c26_d84d; A_64_SS_CC_SCALbx10_ARA0[10] = 64'h2_4613_9088; A_64_SS_CC_SCALbx10_ARA0[11] = 64'h1_2309_ccd0; A_64_SS_CC_SCALbx10_ARA0[12] = 64'h_9184_e6f9; A_64_SS_CC_SCALbx10_ARA0[13] = 64'h_48c2_738f; A_64_SS_CC_SCALbx10_ARA0[14] = 64'h_2461_39ca; A_64_SS_CC_SCALbx10_ARA0[15] = 64'h_1230_9ce5; A_64_SS_CC_SCALbx10_ARA0[16] = 64'h918_4e73; A_64_SS_CC_SCALbx10_ARA0[17] = 64'h48c_2739; A_64_SS_CC_SCALbx10_ARA0[18] = 64'h246_139d; A_64_SS_CC_SCALbx10_ARA0[19] = 64'h123_09ce; A_64_SS_CC_SCALbx10_ARA0[20] = 64'h91_84e7; A_64_SS_CC_SCALbx10_ARA0[21] = 64'h48_c274; A_64_SS_CC_SCALbx10_ARA0[22] = 64'h24_613a; A_64_SS_CC_SCALbx10_ARA0[23] = 64'h12_309d; A_64_SS_CC_SCALbx10_ARA0[24] = 64'h9_184e; A_64_SS_CC_SCALbx10_ARA0[25] = 64'h4_8c27; A_64_SS_CC_SCALbx10_ARA0[26] = 64'h2_4614; A_64_SS_CC_SCALbx10_ARA0[27] = 64'h1_230a; A_64_SS_CC_SCALbx10_ARA0[28] = 64'h_9185; A_64_SS_CC_SCALbx10_ARA0[29] = 64'h_48c2; A_64_SS_CC_SCALbx10_ARA0[30] = 64'h_2461; A_64_SS_CC_SCALbx10_ARA0[31] = 64'h_1231; A_64_SS_CC_SCALbx10_ARA0[32] = 64'h918; A_64_SS_CC_SCALbx10_ARA0[33] = 64'h48c; A_64_SS_CC_SCALbx10_ARA0[34] = 64'h246; A_64_SS_CC_SCALbx10_ARA0[35] = 64'h123; A_64_SS_CC_SCALbx10_ARA0[36] = 64'h92; A_64_SS_CC_SCALbx10_ARA0[37] = 64'h49; A_64_SS_CC_SCALbx10_ARA0[38] = 64'h24; A_64_SS_CC_SCALbx10_ARA0[39] = 64'h12; end initial begin //ROM data table: 36 words of 64 bits. A_64_SS_CC_SCALbx14_ARC0[0] = 64'h0; A_64_SS_CC_SCALbx14_ARC0[1] = 64'h1_190c_a02d_e523; A_64_SS_CC_SCALbx14_ARC0[2] = 64'h2_1696_6b2a_c779; A_64_SS_CC_SCALbx14_ARC0[3] = 64'h2_dfcb_f291_2523; A_64_SS_CC_SCALbx14_ARC0[4] = 64'h3_60fb_19d0_a9f1; A_64_SS_CC_SCALbx14_ARC0[5] = 64'h3_8d7e_a4c6_8000; A_64_SS_CC_SCALbx14_ARC0[6] = 64'h3_60fb_19d0_a9f1; A_64_SS_CC_SCALbx14_ARC0[7] = 64'h2_dfcb_f291_2523; A_64_SS_CC_SCALbx14_ARC0[8] = 64'h2_1696_6b2a_c779; A_64_SS_CC_SCALbx14_ARC0[9] = 64'h1_190c_a02d_e523; A_64_SS_CC_SCALbx14_ARC0[10] = 64'h0; A_64_SS_CC_SCALbx14_ARC0[11] = -64'h1_190c_a02d_e523; A_64_SS_CC_SCALbx14_ARC0[12] = -64'h2_1696_6b2a_c779; A_64_SS_CC_SCALbx14_ARC0[13] = -64'h2_dfcb_f291_2523; A_64_SS_CC_SCALbx14_ARC0[14] = -64'h3_60fb_19d0_a9f1; A_64_SS_CC_SCALbx14_ARC0[15] = -64'h3_8d7e_a4c6_8000; A_64_SS_CC_SCALbx14_ARC0[16] = -64'h3_60fb_19d0_a9f1; A_64_SS_CC_SCALbx14_ARC0[17] = -64'h2_dfcb_f291_2523; A_64_SS_CC_SCALbx14_ARC0[18] = -64'h2_1696_6b2a_c779; A_64_SS_CC_SCALbx14_ARC0[19] = -64'h1_190c_a02d_e523; A_64_SS_CC_SCALbx14_ARC0[20] = 64'h0; A_64_SS_CC_SCALbx14_ARC0[21] = 64'h1_190c_a02d_e524; A_64_SS_CC_SCALbx14_ARC0[22] = 64'h2_1696_6b2a_c778; A_64_SS_CC_SCALbx14_ARC0[23] = 64'h2_dfcb_f291_2523; A_64_SS_CC_SCALbx14_ARC0[24] = 64'h3_60fb_19d0_a9f1; A_64_SS_CC_SCALbx14_ARC0[25] = 64'h3_8d7e_a4c6_8000; A_64_SS_CC_SCALbx14_ARC0[26] = 64'h3_60fb_19d0_a9f1; A_64_SS_CC_SCALbx14_ARC0[27] = 64'h2_dfcb_f291_2523; A_64_SS_CC_SCALbx14_ARC0[28] = 64'h2_1696_6b2a_c779; A_64_SS_CC_SCALbx14_ARC0[29] = 64'h1_190c_a02d_e523; A_64_SS_CC_SCALbx14_ARC0[30] = 64'h0; A_64_SS_CC_SCALbx14_ARC0[31] = -64'h1_190c_a02d_e523; A_64_SS_CC_SCALbx14_ARC0[32] = -64'h2_1696_6b2a_c778; A_64_SS_CC_SCALbx14_ARC0[33] = -64'h2_dfcb_f291_2524; A_64_SS_CC_SCALbx14_ARC0[34] = -64'h3_60fb_19d0_a9f2; A_64_SS_CC_SCALbx14_ARC0[35] = -64'h3_8d7e_a4c6_8000; end initial begin //ROM data table: 36 words of 64 bits. A_64_SS_CC_SCALbx12_ARB0[0] = 64'h0; A_64_SS_CC_SCALbx12_ARB0[1] = 64'h2db_7583_9f15; A_64_SS_CC_SCALbx12_ARB0[2] = 64'h5b6_eb07_3e2b; A_64_SS_CC_SCALbx12_ARB0[3] = 64'h892_608a_dd41; A_64_SS_CC_SCALbx12_ARB0[4] = 64'hb6d_d60e_7c57; A_64_SS_CC_SCALbx12_ARB0[5] = 64'he49_4b92_1b6c; A_64_SS_CC_SCALbx12_ARB0[6] = 64'h_1124_c115_ba82; A_64_SS_CC_SCALbx12_ARB0[7] = 64'h_1400_3699_5998; A_64_SS_CC_SCALbx12_ARB0[8] = 64'h_16db_ac1c_f8ae; A_64_SS_CC_SCALbx12_ARB0[9] = 64'h_19b7_21a0_97c4; A_64_SS_CC_SCALbx12_ARB0[10] = 64'h_1c92_9724_36d9; A_64_SS_CC_SCALbx12_ARB0[11] = 64'h_1f6e_0ca7_d5ef; A_64_SS_CC_SCALbx12_ARB0[12] = 64'h_2249_822b_7505; A_64_SS_CC_SCALbx12_ARB0[13] = 64'h_2524_f7af_141b; A_64_SS_CC_SCALbx12_ARB0[14] = 64'h_2800_6d32_b331; A_64_SS_CC_SCALbx12_ARB0[15] = 64'h_2adb_e2b6_5246; A_64_SS_CC_SCALbx12_ARB0[16] = 64'h_2db7_5839_f15c; A_64_SS_CC_SCALbx12_ARB0[17] = 64'h_3092_cdbd_9072; A_64_SS_CC_SCALbx12_ARB0[18] = 64'h_336e_4341_2f88; A_64_SS_CC_SCALbx12_ARB0[19] = 64'h_3649_b8c4_ce9e; A_64_SS_CC_SCALbx12_ARB0[20] = 64'h_3925_2e48_6db3; A_64_SS_CC_SCALbx12_ARB0[21] = 64'h_3c00_a3cc_0cc9; A_64_SS_CC_SCALbx12_ARB0[22] = 64'h_3edc_194f_abdf; A_64_SS_CC_SCALbx12_ARB0[23] = 64'h_41b7_8ed3_4af5; A_64_SS_CC_SCALbx12_ARB0[24] = 64'h_4493_0456_ea0b; A_64_SS_CC_SCALbx12_ARB0[25] = 64'h_476e_79da_8920; A_64_SS_CC_SCALbx12_ARB0[26] = 64'h_4a49_ef5e_2836; A_64_SS_CC_SCALbx12_ARB0[27] = 64'h_4d25_64e1_c74c; A_64_SS_CC_SCALbx12_ARB0[28] = 64'h_5000_da65_6662; A_64_SS_CC_SCALbx12_ARB0[29] = 64'h_52dc_4fe9_0578; A_64_SS_CC_SCALbx12_ARB0[30] = 64'h_55b7_c56c_a48d; A_64_SS_CC_SCALbx12_ARB0[31] = 64'h_5893_3af0_43a3; A_64_SS_CC_SCALbx12_ARB0[32] = 64'h_5b6e_b073_e2b9; A_64_SS_CC_SCALbx12_ARB0[33] = 64'h_5e4a_25f7_81cf; A_64_SS_CC_SCALbx12_ARB0[34] = 64'h_6125_9b7b_20e4; A_64_SS_CC_SCALbx12_ARB0[35] = 64'h_6401_10fe_bffa; end // 1 vectors of width 5 // 6 vectors of width 64 // 1 vectors of width 1 // 112 array locations of width 64 // 96 bits in scalar variables // Total state bits in module = 7654 bits. // Total number of leaf cells = 0 endmodule // // LCP delay estimations included: turn off with -vnl-lcp-delay-estimate=disable //HPR L/S (orangepath) auxiliary reports. //KiwiC compilation report //Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 0.2.16h : 9th-October-2016 //12/10/2016 09:30:47 //Cmd line args: /home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/kiwic.exe -res2-loadstore-port-count=0 -vnl-resets=synchronous -vnl-roundtrip=disable -kiwic-cil-dump=combined -kiwic-kcode-dump=enable -kiwic-register-colours=1 -bevelab-default-pause-mode=soft -bevelab-soft-pause-threshold=39 -vnl-rootmodname=cordic1 -repack-to-roms=enable cordic.exe -vnl=cordic.v //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation KiKiwi for prefix KiwiSystem/Kiwi //---------------------------------------------------------- //Report from kiwife virtual to physical register colouring/mapping for thread T400::: //: Linear scan colouring done for 0 vregs using 0 pregs // //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation SyBitConverter for prefix System/BitConverter //---------------------------------------------------------- //Report from kiwife virtual to physical register colouring/mapping for thread T401::: //: Linear scan colouring done for 0 vregs using 0 pregs // //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation CS0.4 for prefix CS/0.4 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation CS0.10 for prefix CS/0.10 //---------------------------------------------------------- //Report from kiwife virtual to physical register colouring/mapping for thread T402::: //Allocate phy reg purpose=fastspill_dup msg=allocation for thread T402 for V5001 dt=$star1$/@/64/SS usecount=1 // //Allocate phy reg purpose=fastspill_dup msg=allocation for thread T402 for V5003 dt=$star1$/@/64/SS usecount=2 // //: Linear scan colouring done for 2 vregs using 1 pregs // //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation @64 for prefix @/64 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation CS0.2 for prefix CS/0.2 //---------------------------------------------------------- //Report from kiwife virtual to physical register colouring/mapping for thread T403::: //Allocate phy reg purpose=fastspill_dup msg=allocation for thread T403 for V5005 dt=$star1$/@/64/SS usecount=1 // //: Linear scan colouring done for 1 vregs using 1 pregs // //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation CTMTMa_SPILL for prefix CordicTestbench/T404/Main/T404/Main/_SPILL //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation CTMT4Main for prefix CordicTestbench/T404/Main/T404/Main //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TCs3._SPILL for prefix T404/Cordic/sin/3.9/_SPILL //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation TCsi3.9 for prefix T404/Cordic/sin/3.9 //---------------------------------------------------------- //Report from kiwife virtual to physical register colouring/mapping for thread T404::: //Allocate phy reg purpose=localvar msg=allocation for thread T404 for V5006 dt=BOOL usecount=1 // //Allocate phy reg purpose=localvar msg=allocation for thread T404 for V5007 dt=SINT usecount=1 // //Allocate phy reg purpose=localvar msg=allocation for thread T404 for V5008 dt=SINT usecount=1 // //Allocate phy reg purpose=localvar msg=allocation for thread T404 for V5009 dt=64/SS usecount=1 // //Allocate phy reg purpose=actual_parameter msg=allocation for thread T404 for V5012 dt=64/SS usecount=1 // //Allocate phy reg purpose=localvar msg=allocation for thread T404 for V5013 dt=BOOL usecount=1 // //Allocate phy reg purpose=localvar msg=allocation for thread T404 for V5015 dt=64/SS usecount=1 // //Allocate phy reg purpose=localvar msg=allocation for thread T404 for V5016 dt=SINT usecount=1 // //Allocate phy reg purpose=localvar msg=allocation for thread T404 for V5010 dt=64/SS usecount=2 // //Allocate phy reg purpose=localvar msg=allocation for thread T404 for V5011 dt=64/SS usecount=2 // //Allocate phy reg purpose=fastspill_dup msg=allocation for thread T404 for V5020 dt=SINT usecount=2 // //: Linear scan colouring done for 11 vregs using 8 pregs // //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation CTMTMaV_5 for prefix CordicTestbench/T404/Main/T404/Main/V_5 //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation CTMTMaV_4 for prefix CordicTestbench/T404/Main/T404/Main/V_4 //---------------------------------------------------------- //Report from KiwiC-fe.rpt::: //KiwiC: front end input processing of class or method called KiwiSystem/Kiwi // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor10 // //KiwiC start_thread (or entry point) id=cctor10 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+0 // //KiwiC: front end input processing of class or method called System/BitConverter // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor12 // //KiwiC start_thread (or entry point) id=cctor12 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+1 // //KiwiC: front end input processing of class or method called CordicTestbench // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor16 // //KiwiC start_thread (or entry point) id=cctor16 // //Register sharing: general fastspilldup12/GP used for fastspilldup12 // //Register sharing: general fastspilldup12/GP used for fastspilldup12 // //Register sharing: general fastspilldup12/GP used for fastspilldup10 // //Register sharing: general fastspilldup12/GP used for fastspilldup10 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+2 // //KiwiC: front end input processing of class or method called Cordic // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor14 // //KiwiC start_thread (or entry point) id=cctor14 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+3 // //KiwiC: front end input processing of class or method called CordicTestbench // //root_compiler: start elaborating class 'CordicTestbench' // //elaborating class 'CordicTestbench' // //compiling static method as entry point: style=Root idl=CordicTestbench/Main // //Performing root elaboration of method Main // //KiwiC start_thread (or entry point) id=Main10 // //Register sharing: general fastspilldup16/GP used for fastspilldup16 // //Register sharing: general fastspilldup16/GP used for fastspilldup16 // //Register sharing: general fastspilldup16/GP used for T404/Cordic/sin/3.9/V_3 // //Register sharing: general fastspilldup16/GP used for T404/Cordic/sin/3.9/V_3 // //Register sharing: general CordicTestbench/T404/Main/T404/Main/V_4/GP used for CordicTestbench/T404/Main/T404/Main/V_4 // //Register sharing: general CordicTestbench/T404/Main/T404/Main/V_4/GP used for CordicTestbench/T404/Main/T404/Main/V_4 // //Register sharing: general CordicTestbench/T404/Main/T404/Main/V_4/GP used for T404/Cordic/sin/3.9/V_2 // //Register sharing: general CordicTestbench/T404/Main/T404/Main/V_4/GP used for T404/Cordic/sin/3.9/V_2 // //Register sharing: general CordicTestbench/T404/Main/T404/Main/V_5/GP used for CordicTestbench/T404/Main/T404/Main/V_5 // //Register sharing: general CordicTestbench/T404/Main/T404/Main/V_5/GP used for CordicTestbench/T404/Main/T404/Main/V_5 // //Register sharing: general CordicTestbench/T404/Main/T404/Main/V_5/GP used for sin/theta // //Register sharing: general CordicTestbench/T404/Main/T404/Main/V_5/GP used for sin/theta // //root_compiler class done: CordicTestbench // //Report of all settings used from the recipe or command line: // // cil-uwind-budget=10000 // // kiwic-finish=enable // // kiwic-cil-dump=combined // // kiwic-kcode-dump=enable // // kiwic-register-colours=1 // // array-4d-name=KIWIARRAY4D // // array-3d-name=KIWIARRAY3D // // array-2d-name=KIWIARRAY2D // // kiwi-dll=Kiwi.dll // // kiwic-dll=Kiwic.dll // // kiwic-zerolength-arrays=disable // // kiwic-fpgaconsole-default=enable // // postgen-optimise=enable // // gtrace-loglevel=20 // // firstpass-loglevel=20 // // root=$attributeroot // // srcfile=cordic.exe // //END OF KIWIC REPORT FILE // //---------------------------------------------------------- //Report from enumbers::: //Concise expression alias report. // // -- No expression aliases to report // //---------------------------------------------------------- //Report from restructure2::: //Offchip Load/Store (and other) Ports = Nothing to Report // //---------------------------------------------------------- //Report from restructure2::: //Restructure Technology Settings //*---------------------------+---------+---------------------------------------------------------------------------------* //| Key | Value | Description | //*---------------------------+---------+---------------------------------------------------------------------------------* //| int_flr_mul | -3000 | | //| fp_fl_dp_div | 5 | | //| fp_fl_dp_add | 4 | | //| fp_fl_dp_mul | 3 | | //| fp_fl_sp_div | 5 | | //| fp_fl_sp_add | 4 | | //| fp_fl_sp_mul | 3 | | //| res2-loadstore-port-count | 0 | | //| max_no_fp_addsubs | 6 | Maximum number of adders and subtractors (or combos) to instantiate per thread. | //| max_no_fp_muls | 6 | Maximum number of f/p multipliers or dividers to instantiate per thread. | //| max_no_int_muls | 3 | Maximum number of int multipliers to instantiate per thread. | //| max_no_fp_divs | 2 | Maximum number of f/p dividers to instantiate per thread. | //| max_no_int_divs | 2 | Maximum number of int dividers to instantiate per thread. | //| res2-offchip-threshold | 1000000 | | //| res2-combrom-threshold | 64 | | //| res2-combram-threshold | 32 | | //| res2-regfile-threshold | 8 | | //*---------------------------+---------+---------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: //PC codings points for xpc10 //*--------------------------+-----+-------------+------+------+-------+-----+-------------+------* //| gb-flag/Pause | eno | hwm | root | exec | start | end | antecedants | next | //*--------------------------+-----+-------------+------+------+-------+-----+-------------+------* //| X0:"0:xpc10" | 900 | hwm=0.0.0 | 0 | 0 | - | - | --- | 1 | //| X1:"1:xpc10" | 901 | hwm=0.0.0 | 1 | 1 | - | - | --- | 2 | //| X2:"2:xpc10" | 902 | hwm=0.0.0 | 2 | 2 | - | - | --- | 3 | //| X4:"4:xpc10" | 903 | hwm=0.0.0 | 3 | 3 | - | - | --- | 4 | //| X8:"8:xpc10" | 913 | hwm=0.0.0 | 4 | 4 | - | - | --- | 20 | //| X8:"8:xpc10" | 912 | hwm=0.0.0 | 4 | 4 | - | - | --- | 6 | //| X8:"8:xpc10" | 911 | hwm=0.0.0 | 4 | 4 | - | - | --- | 5 | //| X8:"8:xpc10" | 910 | hwm=0.0.0 | 4 | 4 | - | - | --- | 19 | //| X8:"8:xpc10" | 909 | hwm=0.0.0 | 4 | 4 | - | - | --- | 5 | //| X8:"8:xpc10" | 908 | hwm=0.0.0 | 4 | 4 | - | - | --- | 20 | //| X8:"8:xpc10" | 907 | hwm=0.0.0 | 4 | 4 | - | - | --- | 19 | //| X8:"8:xpc10" | 906 | hwm=0.0.0 | 4 | 4 | - | - | --- | 5 | //| X8:"8:xpc10" | 905 | hwm=0.0.0 | 4 | 4 | - | - | --- | 19 | //| X8:"8:xpc10" | 904 | hwm=0.0.0 | 4 | 4 | - | - | --- | 5 | //| X16:"16:xpc10" | 915 | hwm=0.0.0 | 5 | 5 | - | - | --- | 18 | //| X16:"16:xpc10" | 914 | hwm=0.0.0 | 5 | 5 | - | - | --- | 6 | //| X32:"32:xpc10" | 916 | hwm=0.0.0 | 6 | 6 | - | - | --- | 7 | //| X64:"64:xpc10" | 920 | hwm=0.0.0 | 7 | 7 | - | - | --- | 16 | //| X64:"64:xpc10" | 919 | hwm=0.0.0 | 7 | 7 | - | - | --- | 14 | //| X64:"64:xpc10" | 918 | hwm=0.0.0 | 7 | 7 | - | - | --- | 9 | //| X64:"64:xpc10" | 917 | hwm=0.0.0 | 7 | 7 | - | - | --- | 8 | //| X128:"128:xpc10" | 921 | hwm=0.0.0 | 8 | 8 | - | - | --- | 9 | //| X256:"256:xpc10" | 923 | hwm=0.0.0 | 9 | 9 | - | - | --- | 10 | //| X256:"256:xpc10" | 922 | hwm=0.0.0 | 9 | 9 | - | - | --- | 10 | //| X512:"512:xpc10" | 925 | hwm=0.0.0 | 10 | 10 | - | - | --- | 11 | //| X512:"512:xpc10" | 924 | hwm=0.0.0 | 10 | 10 | - | - | --- | 11 | //| X1024:"1024:xpc10" | 928 | hwm=0.0.0 | 11 | 11 | - | - | --- | 3 | //| X1024:"1024:xpc10" | 927 | hwm=0.0.0 | 11 | 11 | - | - | --- | 12 | //| X1024:"1024:xpc10" | 926 | hwm=0.0.0 | 11 | 11 | - | - | --- | 12 | //| X2048:"2048:xpc10" | 929 | hwm=0.0.0 | 12 | 12 | - | - | --- | 13 | //| X4096:"4096:xpc10" | 930 | hwm=0.0.0 | 13 | 13 | - | - | --- | 13 | //| X8192:"8192:xpc10" | 931 | hwm=0.0.0 | 14 | 14 | - | - | --- | 15 | //| X16384:"16384:xpc10" | 932 | hwm=0.0.0 | 15 | 15 | - | - | --- | 6 | //| X32768:"32768:xpc10" | 933 | hwm=0.0.0 | 16 | 16 | - | - | --- | 17 | //| X65536:"65536:xpc10" | 934 | hwm=0.0.0 | 17 | 17 | - | - | --- | 18 | //| X131072:"131072:xpc10" | 935 | hwm=0.0.0 | 18 | 18 | - | - | --- | 7 | //| X262144:"262144:xpc10" | 937 | hwm=0.0.0 | 19 | 19 | - | - | --- | 16 | //| X262144:"262144:xpc10" | 936 | hwm=0.0.0 | 19 | 19 | - | - | --- | 15 | //| X524288:"524288:xpc10" | 943 | hwm=0.0.0 | 20 | 20 | - | - | --- | 18 | //| X524288:"524288:xpc10" | 942 | hwm=0.0.0 | 20 | 20 | - | - | --- | 6 | //| X524288:"524288:xpc10" | 941 | hwm=0.0.0 | 20 | 20 | - | - | --- | 19 | //| X524288:"524288:xpc10" | 940 | hwm=0.0.0 | 20 | 20 | - | - | --- | 19 | //| X524288:"524288:xpc10" | 939 | hwm=0.0.0 | 20 | 20 | - | - | --- | 5 | //| X524288:"524288:xpc10" | 938 | hwm=0.0.0 | 20 | 20 | - | - | --- | 20 | //*--------------------------+-----+-------------+------+------+-------+-----+-------------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X0:"0:xpc10" 900 : major_start_pcl=0 edge_private_start/end=-1/-1 exec=0 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X0:"0:xpc10" //res2: Thread=xpc10 state=X0:"0:xpc10" //*-----+-----+---------+----------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+----------------------------* //| 0 | - | R0 CTRL | | //| 0 | 900 | R0 DATA | | //| 0+E | 900 | W0 DATA | done te=te:0 scalarw(U1'0) | //*-----+-----+---------+----------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X1:"1:xpc10" 901 : major_start_pcl=1 edge_private_start/end=-1/-1 exec=1 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X1:"1:xpc10" //res2: Thread=xpc10 state=X1:"1:xpc10" //*-----+-----+---------+------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------* //| 1 | - | R0 CTRL | | //| 1 | 901 | R0 DATA | | //| 1+E | 901 | W0 DATA | | //*-----+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X2:"2:xpc10" 902 : major_start_pcl=2 edge_private_start/end=-1/-1 exec=2 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X2:"2:xpc10" //res2: Thread=xpc10 state=X2:"2:xpc10" //*-----+-----+---------+------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------------------------------------------------------------------------------------------------* //| 2 | - | R0 CTRL | | //| 2 | 902 | R0 DATA | | //| 2+E | 902 | W0 DATA | CTMT4Main_V_2 te=te:2 scalarw(0) CTMT4Main_V_1 te=te:2 scalarw(0) PLI:cordic: Testbench st... | //*-----+-----+---------+------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X4:"4:xpc10" 903 : major_start_pcl=3 edge_private_start/end=-1/-1 exec=3 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X4:"4:xpc10" //res2: Thread=xpc10 state=X4:"4:xpc10" //*-----+-----+---------+--------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+--------------------------------------------------------------------* //| 3 | - | R0 CTRL | | //| 3 | 903 | R0 DATA | | //| 3+E | 903 | W0 DATA | CTMTMaV_5_GP te=te:3 scalarw(E1) CTMT4Main_V_3 te=te:3 scalarw(E2) | //*-----+-----+---------+--------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8:"8:xpc10" 913 : major_start_pcl=4 edge_private_start/end=-1/-1 exec=4 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8:"8:xpc10" 912 : major_start_pcl=4 edge_private_start/end=-1/-1 exec=4 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8:"8:xpc10" 911 : major_start_pcl=4 edge_private_start/end=-1/-1 exec=4 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8:"8:xpc10" 910 : major_start_pcl=4 edge_private_start/end=-1/-1 exec=4 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8:"8:xpc10" 909 : major_start_pcl=4 edge_private_start/end=-1/-1 exec=4 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8:"8:xpc10" 908 : major_start_pcl=4 edge_private_start/end=-1/-1 exec=4 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8:"8:xpc10" 907 : major_start_pcl=4 edge_private_start/end=-1/-1 exec=4 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8:"8:xpc10" 906 : major_start_pcl=4 edge_private_start/end=-1/-1 exec=4 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8:"8:xpc10" 905 : major_start_pcl=4 edge_private_start/end=-1/-1 exec=4 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8:"8:xpc10" 904 : major_start_pcl=4 edge_private_start/end=-1/-1 exec=4 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X8:"8:xpc10" //res2: Thread=xpc10 state=X8:"8:xpc10" //*-----+-----+---------+-------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+-------------------------------------------------------------------------------------------------------------------------------* //| 4 | - | R0 CTRL | | //| 4 | 904 | R0 DATA | | //| 4+E | 904 | W0 DATA | CTMTMaV_5_GP te=te:4 scalarw(E3) TCsi3.9_V_0 te=te:4 scalarw(0) | //| 4 | 905 | R0 DATA | | //| 4+E | 905 | W0 DATA | CTMTMaV_5_GP te=te:4 scalarw(E4) TCsi3.9_V_0 te=te:4 scalarw(0) TCsi3.9_V_1 te=te:4 scalarw(S64'607252935008962) | //| 4 | 906 | R0 DATA | | //| 4+E | 906 | W0 DATA | CTMTMaV_5_GP te=te:4 scalarw(E5) TCsi3.9_V_0 te=te:4 scalarw(1) | //| 4 | 907 | R0 DATA | | //| 4+E | 907 | W0 DATA | CTMTMaV_5_GP te=te:4 scalarw(E6) TCsi3.9_V_0 te=te:4 scalarw(1) TCsi3.9_V_1 te=te:4 scalarw(S64'607252935008962) | //| 4 | 908 | R0 DATA | | //| 4+E | 908 | W0 DATA | CTMTMaV_5_GP te=te:4 scalarw(E7) TCsi3.9_V_0 te=te:4 scalarw(1) | //| 4 | 909 | R0 DATA | | //| 4+E | 909 | W0 DATA | CTMTMaV_5_GP te=te:4 scalarw(E5) TCsi3.9_V_0 te=te:4 scalarw(1) | //| 4 | 910 | R0 DATA | | //| 4+E | 910 | W0 DATA | CTMTMaV_5_GP te=te:4 scalarw(E6) TCsi3.9_V_0 te=te:4 scalarw(1) TCsi3.9_V_1 te=te:4 scalarw(S64'607252935008962) | //| 4 | 911 | R0 DATA | | //| 4+E | 911 | W0 DATA | CTMTMaV_5_GP te=te:4 scalarw(E8) TCsi3.9_V_0 te=te:4 scalarw(U1'0) | //| 4 | 912 | R0 DATA | | //| 4+E | 912 | W0 DATA | CTMTMaV_5_GP te=te:4 scalarw(E9) TCsi3.9_V_0 te=te:4 scalarw(U1'0) TCsi3.9_V_1 te=te:4 scalarw(S64'607252935008962) TCsi3.9_\ | //| | | | V_5 te=te:4 scalarw(S'607252935008962) TCsi3.9_V_4 te=te:4 scalarw(S'607252935008962) fastspilldup16_GP te=te:4 scalarw(0) C\ | //| | | | TMTMaV_4_GP te=te:4 scalarw(S64'0) | //| 4 | 913 | R0 DATA | | //| 4+E | 913 | W0 DATA | CTMTMaV_5_GP te=te:4 scalarw(E4) TCsi3.9_V_0 te=te:4 scalarw(U1'0) | //*-----+-----+---------+-------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X16:"16:xpc10" 915 : major_start_pcl=5 edge_private_start/end=-1/-1 exec=5 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X16:"16:xpc10" 914 : major_start_pcl=5 edge_private_start/end=-1/-1 exec=5 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X16:"16:xpc10" //res2: Thread=xpc10 state=X16:"16:xpc10" //*-----+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------* //| 5 | - | R0 CTRL | | //| 5 | 914 | R0 DATA | | //| 5+E | 914 | W0 DATA | CTMTMaV_5_GP te=te:5 scalarw(E9) TCsi3.9_V_1 te=te:5 scalarw(S64'607252935008962) TCsi3.9_V_5 te=te:5 scalarw(S'607252935008962) TCsi3.9_V_4 te=te:5 scalarw(S'607252\ | //| | | | 935008962) fastspilldup16_GP te=te:5 scalarw(0) CTMTMaV_4_GP te=te:5 scalarw(S64'0) | //| 5 | 915 | R0 DATA | | //| 5+E | 915 | W0 DATA | CTMTMaV_5_GP te=te:5 scalarw(E10) TCsi3.9_V_1 te=te:5 scalarw(S64'607252935008962) TCsi3.9_V_5 te=te:5 scalarw(S'-607252935008962) TCsi3.9_V_4 te=te:5 scalarw(S'6072\ | //| | | | 52935008962) fastspilldup16_GP te=te:5 scalarw(0) CTMTMaV_4_GP te=te:5 scalarw(S64'0) | //*-----+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X32:"32:xpc10" 916 : major_start_pcl=6 edge_private_start/end=-1/-1 exec=6 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X32:"32:xpc10" //res2: Thread=xpc10 state=X32:"32:xpc10" //*-----+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------* //| 6 | - | R0 CTRL | | //| 6 | 916 | R0 DATA | | //| 6+E | 916 | W0 DATA | TCsi3.9_V_1 te=te:6 scalarw(C64(TCsi3.9_V_4)) fastspilldup16_GP te=te:6 scalarw(1+fastspilldup16_GP) CTMTMaV_4_GP te=te:6 scalarw(C64(TCsi3.9_V_5)) | //*-----+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X64:"64:xpc10" 920 : major_start_pcl=7 edge_private_start/end=-1/-1 exec=7 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X64:"64:xpc10" 919 : major_start_pcl=7 edge_private_start/end=-1/-1 exec=7 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X64:"64:xpc10" 918 : major_start_pcl=7 edge_private_start/end=-1/-1 exec=7 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X64:"64:xpc10" 917 : major_start_pcl=7 edge_private_start/end=-1/-1 exec=7 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X64:"64:xpc10" //res2: Thread=xpc10 state=X64:"64:xpc10" //*-----+-----+---------+-----------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+-----------------------------------------------------------------------------------* //| 7 | - | R0 CTRL | | //| 7 | 917 | R0 DATA | | //| 7+E | 917 | W0 DATA | CTMTMaV_4_GP te=te:7 scalarw(C64(-CTMTMaV_4_GP)) | //| 7 | 918 | R0 DATA | | //| 7+E | 918 | W0 DATA | CTMTMaV_5_GP te=te:7 scalarw(E11) CTMTMaV_4_GP te=te:7 scalarw(C64(CTMTMaV_4_GP)) | //| 7 | 919 | R0 DATA | | //| 7+E | 919 | W0 DATA | TCsi3.9_V_4 te=te:7 scalarw(E12) | //| 7 | 920 | R0 DATA | | //| 7+E | 920 | W0 DATA | TCsi3.9_V_4 te=te:7 scalarw(E13) | //*-----+-----+---------+-----------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X128:"128:xpc10" 921 : major_start_pcl=8 edge_private_start/end=-1/-1 exec=8 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X128:"128:xpc10" //res2: Thread=xpc10 state=X128:"128:xpc10" //*-----+-----+---------+-----------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+-----------------------------------* //| 8 | - | R0 CTRL | | //| 8 | 921 | R0 DATA | | //| 8+E | 921 | W0 DATA | CTMTMaV_5_GP te=te:8 scalarw(E14) | //*-----+-----+---------+-----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X256:"256:xpc10" 923 : major_start_pcl=9 edge_private_start/end=-1/-1 exec=9 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X256:"256:xpc10" 922 : major_start_pcl=9 edge_private_start/end=-1/-1 exec=9 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X256:"256:xpc10" //res2: Thread=xpc10 state=X256:"256:xpc10" //*-----+-----+---------+---------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+---------------------------------------------------------------------------------------------------------* //| 9 | - | R0 CTRL | | //| 9 | 922 | R0 DATA | | //| 9+E | 922 | W0 DATA | CTMT4Main_V_1 te=te:9 scalarw(1+(C(CTMT4Main_V_1))) fastspilldup16_GP te=te:9 scalarw(C(CTMT4Main_V_1)) | //| 9 | 923 | R0 DATA | | //| 9+E | 923 | W0 DATA | CTMT4Main_V_1 te=te:9 scalarw(C(CTMT4Main_V_1)) fastspilldup16_GP te=te:9 scalarw(C(CTMT4Main_V_1)) | //*-----+-----+---------+---------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X512:"512:xpc10" 925 : major_start_pcl=10 edge_private_start/end=-1/-1 exec=10 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X512:"512:xpc10" 924 : major_start_pcl=10 edge_private_start/end=-1/-1 exec=10 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X512:"512:xpc10" //res2: Thread=xpc10 state=X512:"512:xpc10" //*------+-----+---------+-------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------------------------------------------------------------------* //| 10 | - | R0 CTRL | | //| 10 | 924 | R0 DATA | | //| 10+E | 924 | W0 DATA | CTMT4Main_V_2 te=te:10 scalarw(1+CTMT4Main_V_2) PLI: test %u error=%u PLI:Test: input=%u expec... | //| 10 | 925 | R0 DATA | | //| 10+E | 925 | W0 DATA | CTMT4Main_V_2 te=te:10 scalarw(1+CTMT4Main_V_2) PLI:Test: input=%u expec... | //*------+-----+---------+-------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X1024:"1024:xpc10" 928 : major_start_pcl=11 edge_private_start/end=-1/-1 exec=11 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X1024:"1024:xpc10" 927 : major_start_pcl=11 edge_private_start/end=-1/-1 exec=11 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X1024:"1024:xpc10" 926 : major_start_pcl=11 edge_private_start/end=-1/-1 exec=11 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X1024:"1024:xpc10" //res2: Thread=xpc10 state=X1024:"1024:xpc10" //*------+-----+---------+-----------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-----------------------------------------------------------------------------------------------* //| 11 | - | R0 CTRL | | //| 11 | 926 | R0 DATA | | //| 11+E | 926 | W0 DATA | done te=te:11 scalarw(U1'1) PLI:cordic: Testbench fi... PLI:RESULT: PASS PLI:Result: %u/%u | //| 11 | 927 | R0 DATA | | //| 11+E | 927 | W0 DATA | done te=te:11 scalarw(U1'1) PLI:cordic: Testbench fi... PLI:RESULT: FAIL PLI:Result: %u/%u | //| 11 | 928 | R0 DATA | | //| 11+E | 928 | W0 DATA | | //*------+-----+---------+-----------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X2048:"2048:xpc10" 929 : major_start_pcl=12 edge_private_start/end=-1/-1 exec=12 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X2048:"2048:xpc10" //res2: Thread=xpc10 state=X2048:"2048:xpc10" //*------+-----+---------+------* //| pc | eno | Phaser | Work | //*------+-----+---------+------* //| 12 | - | R0 CTRL | | //| 12 | 929 | R0 DATA | | //| 12+E | 929 | W0 DATA | | //*------+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X4096:"4096:xpc10" 930 : major_start_pcl=13 edge_private_start/end=-1/-1 exec=13 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X4096:"4096:xpc10" //res2: Thread=xpc10 state=X4096:"4096:xpc10" //*------+-----+---------+-----------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-----------------------* //| 13 | - | R0 CTRL | | //| 13 | 930 | R0 DATA | | //| 13+E | 930 | W0 DATA | PLI:GSAI:hpr_sysexit | //*------+-----+---------+-----------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8192:"8192:xpc10" 931 : major_start_pcl=14 edge_private_start/end=-1/-1 exec=14 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X8192:"8192:xpc10" //res2: Thread=xpc10 state=X8192:"8192:xpc10" //*------+-----+---------+-----------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-----------------------------------* //| 14 | - | R0 CTRL | | //| 14 | 931 | R0 DATA | | //| 14+E | 931 | W0 DATA | TCsi3.9_V_5 te=te:14 scalarw(E15) | //*------+-----+---------+-----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X16384:"16384:xpc10" 932 : major_start_pcl=15 edge_private_start/end=-1/-1 exec=15 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X16384:"16384:xpc10" //res2: Thread=xpc10 state=X16384:"16384:xpc10" //*------+-----+---------+------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+------------------------------------* //| 15 | - | R0 CTRL | | //| 15 | 932 | R0 DATA | | //| 15+E | 932 | W0 DATA | CTMTMaV_5_GP te=te:15 scalarw(E16) | //*------+-----+---------+------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X32768:"32768:xpc10" 933 : major_start_pcl=16 edge_private_start/end=-1/-1 exec=16 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X32768:"32768:xpc10" //res2: Thread=xpc10 state=X32768:"32768:xpc10" //*------+-----+---------+-----------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-----------------------------------* //| 16 | - | R0 CTRL | | //| 16 | 933 | R0 DATA | | //| 16+E | 933 | W0 DATA | TCsi3.9_V_5 te=te:16 scalarw(E17) | //*------+-----+---------+-----------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X65536:"65536:xpc10" 934 : major_start_pcl=17 edge_private_start/end=-1/-1 exec=17 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X65536:"65536:xpc10" //res2: Thread=xpc10 state=X65536:"65536:xpc10" //*------+-----+---------+------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+------------------------------------* //| 17 | - | R0 CTRL | | //| 17 | 934 | R0 DATA | | //| 17+E | 934 | W0 DATA | CTMTMaV_5_GP te=te:17 scalarw(E18) | //*------+-----+---------+------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X131072:"131072:xpc10" 935 : major_start_pcl=18 edge_private_start/end=-1/-1 exec=18 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X131072:"131072:xpc10" //res2: Thread=xpc10 state=X131072:"131072:xpc10" //*------+-----+---------+--------------------------------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+--------------------------------------------------------------------------------------------------------------------------------------------------------* //| 18 | - | R0 CTRL | | //| 18 | 935 | R0 DATA | | //| 18+E | 935 | W0 DATA | TCsi3.9_V_1 te=te:18 scalarw(C64(TCsi3.9_V_4)) fastspilldup16_GP te=te:18 scalarw(1+fastspilldup16_GP) CTMTMaV_4_GP te=te:18 scalarw(C64(TCsi3.9_V_5)) | //*------+-----+---------+--------------------------------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X262144:"262144:xpc10" 937 : major_start_pcl=19 edge_private_start/end=-1/-1 exec=19 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X262144:"262144:xpc10" 936 : major_start_pcl=19 edge_private_start/end=-1/-1 exec=19 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X262144:"262144:xpc10" //res2: Thread=xpc10 state=X262144:"262144:xpc10" //*------+-----+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------* //| 19 | - | R0 CTRL | | //| 19 | 936 | R0 DATA | | //| 19+E | 936 | W0 DATA | TCsi3.9_V_5 te=te:19 scalarw(S64'0+TCsi3.9_V_1) TCsi3.9_V_4 te=te:19 scalarw(TCsi3.9_V_1) fastspilldup16_GP te=te:19 scalarw(0) CTMTMaV_4_GP te=te:19 scalarw(S64'0) | //| 19 | 937 | R0 DATA | | //| 19+E | 937 | W0 DATA | TCsi3.9_V_4 te=te:19 scalarw(S64'0+TCsi3.9_V_1) fastspilldup16_GP te=te:19 scalarw(0) CTMTMaV_4_GP te=te:19 scalarw(S64'0) | //*------+-----+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X524288:"524288:xpc10" 943 : major_start_pcl=20 edge_private_start/end=-1/-1 exec=20 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X524288:"524288:xpc10" 942 : major_start_pcl=20 edge_private_start/end=-1/-1 exec=20 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X524288:"524288:xpc10" 941 : major_start_pcl=20 edge_private_start/end=-1/-1 exec=20 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X524288:"524288:xpc10" 940 : major_start_pcl=20 edge_private_start/end=-1/-1 exec=20 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X524288:"524288:xpc10" 939 : major_start_pcl=20 edge_private_start/end=-1/-1 exec=20 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X524288:"524288:xpc10" 938 : major_start_pcl=20 edge_private_start/end=-1/-1 exec=20 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X524288:"524288:xpc10" //res2: Thread=xpc10 state=X524288:"524288:xpc10" //*------+-----+---------+-------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------------------------------------------------------------------------------* //| 20 | - | R0 CTRL | | //| 20 | 938 | R0 DATA | | //| 20+E | 938 | W0 DATA | CTMTMaV_5_GP te=te:20 scalarw(E4) | //| 20 | 939 | R0 DATA | | //| 20+E | 939 | W0 DATA | CTMTMaV_5_GP te=te:20 scalarw(E5) TCsi3.9_V_0 te=te:20 scalarw(E19) | //| 20 | 940 | R0 DATA | | //| 20+E | 940 | W0 DATA | CTMTMaV_5_GP te=te:20 scalarw(E6) TCsi3.9_V_0 te=te:20 scalarw(E19) TCsi3.9_V_1 te=te:20 scalarw(S64'60725293500\ | //| | | | 8962) | //| 20 | 941 | R0 DATA | | //| 20+E | 941 | W0 DATA | CTMTMaV_5_GP te=te:20 scalarw(E8) TCsi3.9_V_1 te=te:20 scalarw(S64'607252935008962) | //| 20 | 942 | R0 DATA | | //| 20+E | 942 | W0 DATA | CTMTMaV_5_GP te=te:20 scalarw(E9) TCsi3.9_V_1 te=te:20 scalarw(S64'607252935008962) TCsi3.9_V_5 te=te:20 scalarw\ | //| | | | (S'607252935008962) TCsi3.9_V_4 te=te:20 scalarw(S'607252935008962) fastspilldup16_GP te=te:20 scalarw(0) CTMTMa\ | //| | | | V_4_GP te=te:20 scalarw(S64'0) | //| 20 | 943 | R0 DATA | | //| 20+E | 943 | W0 DATA | CTMTMaV_5_GP te=te:20 scalarw(E10) TCsi3.9_V_1 te=te:20 scalarw(S64'607252935008962) TCsi3.9_V_5 te=te:20 scalar\ | //| | | | w(S'-607252935008962) TCsi3.9_V_4 te=te:20 scalarw(S'607252935008962) fastspilldup16_GP te=te:20 scalarw(0) CTMT\ | //| | | | MaV_4_GP te=te:20 scalarw(S64'0) | //*------+-----+---------+-------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from enumbers::: //Concise expression alias report. // // E1 =.= C64(@64_SS/CC/SCALbx12_ARB0[CTMT4Main_V_2]) // // E2 =.= C64(@64_SS/CC/SCALbx14_ARC0[CTMT4Main_V_2]) // // E3 =.= S'94247779607694+-CTMTMaV_5_GP // // E4 =.= S'-62831853071796+CTMTMaV_5_GP // // E5 =.= S'62831853071796+-CTMTMaV_5_GP // // E6 =.= S'-31415926535898+CTMTMaV_5_GP // // E7 =.= S'-94247779607694+CTMTMaV_5_GP // // E8 =.= S64'31415926535898+-CTMTMaV_5_GP // // E9 =.= CTMTMaV_5_GP+-@64_SS/CC/SCALbx10_ARA0[0] // // E10 =.= CTMTMaV_5_GP+@64_SS/CC/SCALbx10_ARA0[0] // // E11 =.= C64(*APPLY:hpr_abs((C64(CTMTMaV_4_GP))+-CTMT4Main_V_3)) // // E12 =.= TCsi3.9_V_1+-(CTMTMaV_4_GP>>(63&fastspilldup16_GP)) // // E13 =.= TCsi3.9_V_1+(CTMTMaV_4_GP>>(63&fastspilldup16_GP)) // // E14 =.= C64(*APPLY:hpr_abs(CTMTMaV_4_GP+-CTMT4Main_V_3)) // // E15 =.= CTMTMaV_4_GP+(TCsi3.9_V_1>>(63&fastspilldup16_GP)) // // E16 =.= CTMTMaV_5_GP+-@64_SS/CC/SCALbx10_ARA0[fastspilldup16_GP] // // E17 =.= CTMTMaV_4_GP+-(TCsi3.9_V_1>>(63&fastspilldup16_GP)) // // E18 =.= CTMTMaV_5_GP+@64_SS/CC/SCALbx10_ARA0[fastspilldup16_GP] // // E19 =.= TCsi3.9_V_0==X0:"0:TCsi3.9_V_0" // // E20 =.= {[CTMTMaV_5_GP<S64'0, S'-31415926535898+CTMTMaV_5_GP<S64'62831853071796, S'-31415926535898+CTMTMaV_5_GP>=S64'31415926535898, S'-62831853071796+CTMTMaV_5_GP>=S64'15707963267949]} // // E21 =.= {[CTMTMaV_5_GP<S64'0, S'-31415926535898+CTMTMaV_5_GP<S64'62831853071796, S'-31415926535898+CTMTMaV_5_GP>=S64'31415926535898, S'-62831853071796+CTMTMaV_5_GP<S64'15707963267949]} // // E22 =.= {[CTMTMaV_5_GP<S64'0, S'-31415926535898+CTMTMaV_5_GP>=S64'15707963267949, S'-31415926535898+CTMTMaV_5_GP<S64'62831853071796, S'-31415926535898+CTMTMaV_5_GP<S64'31415926535898]} // // E23 =.= {[CTMTMaV_5_GP<S64'0, S'-31415926535898+CTMTMaV_5_GP<S64'15707963267949, S'-31415926535898+CTMTMaV_5_GP<S64'62831853071796, S'-31415926535898+CTMTMaV_5_GP<S64'31415926535898]} // // E24 =.= {[CTMTMaV_5_GP<S64'0, S'-31415926535898+CTMTMaV_5_GP>=S64'62831853071796]} // // E25 =.= {[CTMTMaV_5_GP>=S64'0, CTMTMaV_5_GP<S64'62831853071796, CTMTMaV_5_GP>=S64'31415926535898, S'-31415926535898+CTMTMaV_5_GP>=S64'15707963267949]} // // E26 =.= {[CTMTMaV_5_GP>=S64'0, CTMTMaV_5_GP<S64'62831853071796, CTMTMaV_5_GP>=S64'31415926535898, S'-31415926535898+CTMTMaV_5_GP<S64'15707963267949]} // // E27 =.= {[CTMTMaV_5_GP>=S64'0, CTMTMaV_5_GP<S64'62831853071796, CTMTMaV_5_GP<S64'31415926535898, CTMTMaV_5_GP>=S64'15707963267949]} // // E28 =.= {[CTMTMaV_5_GP>=S64'0, CTMTMaV_5_GP<S64'62831853071796, CTMTMaV_5_GP<S64'31415926535898, CTMTMaV_5_GP<S64'15707963267949]} // // E29 =.= {[CTMTMaV_5_GP>=S64'0, CTMTMaV_5_GP>=S64'62831853071796]} // // E30 =.= {[|-|TCsi3.9_V_0, fastspilldup16_GP>=40]} // // E31 =.= {[!(|-|TCsi3.9_V_0), fastspilldup16_GP>=40]} // // E32 =.= {[CTMTMaV_5_GP>=S64'0, fastspilldup16_GP<40]} // // E33 =.= {[CTMTMaV_5_GP<S64'0, fastspilldup16_GP<40]} // // E34 =.= {[CTMT4Main_V_1==X36:"36:CTMT4Main_V_1", CTMT4Main_V_2>=S32'36]} // // E35 =.= {[CTMT4Main_V_1!=X36:"36:CTMT4Main_V_1", CTMT4Main_V_2>=S32'36]} // // E36 =.= CTMTMaV_5_GP>=S64'62831853071796 // // E37 =.= {[CTMTMaV_5_GP<S64'62831853071796, CTMTMaV_5_GP>=S64'31415926535898, S'-31415926535898+CTMTMaV_5_GP>=S64'15707963267949]} // // E38 =.= {[CTMTMaV_5_GP<S64'62831853071796, CTMTMaV_5_GP>=S64'31415926535898, S'-31415926535898+CTMTMaV_5_GP<S64'15707963267949]} // // E39 =.= {[CTMTMaV_5_GP<S64'62831853071796, CTMTMaV_5_GP<S64'31415926535898, CTMTMaV_5_GP>=S64'15707963267949]} // // E40 =.= {[CTMTMaV_5_GP<S64'0, CTMTMaV_5_GP<S64'62831853071796, CTMTMaV_5_GP<S64'31415926535898, CTMTMaV_5_GP<S64'15707963267949]} // //---------------------------------------------------------- //Report from verilog_render::: //1 vectors of width 5 // //6 vectors of width 64 // //1 vectors of width 1 // //112 array locations of width 64 // //96 bits in scalar variables // //Total state bits in module = 7654 bits. // //Total number of leaf cells = 0 // //Major Statistics Report: //Thread .cctor uid=cctor10 has 3 CIL instructions in 1 basic blocks //Thread .cctor uid=cctor12 has 2 CIL instructions in 1 basic blocks //Thread .cctor uid=cctor16 has 10 CIL instructions in 1 basic blocks //Thread .cctor uid=cctor14 has 5 CIL instructions in 1 basic blocks //Thread Main uid=Main10 has 98 CIL instructions in 36 basic blocks //Thread mpc10 has 21 bevelab control states (pauses) //Reindexed thread xpc10 with 21 minor control states // eof (HPR L/S Verilog)