CVNL is an old program that will read in Verilog netlists (.vnl) files and write them out in a selected format. Before processing, the program cross-checks all input and output ports to ensure Verilog's wiring rules are met. The input file is generally eithe written by hand if it is a pad ring or is the -vnl Verilog netlist output from cv2.100/200.
The program will flatten the design starting from the module specified with -root on the command line and proceed downwards until encountering a module which is declared as primitive or a member of a technology library. It does not handled parameter overrides so the -flatten option within cv2.100/200 should be used as much as possible first.
The resulting flattened module is then output in the format selected. If the -dontflatten command line flag is given, all instances within the root module will be considered primitive and so not expanded (flattened), hence only the root module will be output.
Primitive modules will not be flattened but will be left as instances. Primitive modules can be defined in a file using the 'primitive ... endprimitive' keywords or perhaps with the preprocessor 'celldefine' macro if it is working at the moment. All modules which are found in files which appear on the command line after the flag -libs in the command line will also be treated as primitive.
Note that CVNL will only accept a subset of the Verilog language as its input and this subset is a heirarchic netlist. Full-blooded Verilog modules must first be compiled into vnl with another program.
The format of the command line is
cvnl [ options ] fn [ fn ... ] -libs fn [ fn ...] \n", argv[0]);
The files before the -libs flag are the primary source files which will be processed and those after are library files which will be used only for cross-checking.
The output formats available are as follows.
With ranger3 format, the -powernames option enables a list of comma-separated additional supply names to be supplied.
The `-root rootmodule' command line flag selects a module of those present in the input files to be used as the root for output and or flattening.
-tech technology-library specifies a technology library file. The library file must be on the CVPATH and has suffix `.mas'. For example, to use the xi4000 library the file `xi4000.mas' must be on the CVPATH. Only the xnf output format currently requires a technology library to be given.
-o
The -device
The -ncd command line option disables module interconnectivity checks, enabling inputs to be undriven and outputs to be joined, etc..
The -autogen option causes the program to render a used module in the output even when the module definition is not present in the target technology library (a prototype must be present in the included input files though).
The -report option causes the program to report how many gate inputs and outpus are in use and related statistics. Report is perhaps not implemented today.
If the -dontflatten command line flag is given, all instances within the root module will be considered primitive and so not expanded (flattened), hence only the root module will be output.
The `-edif' command line flag selects an EDIF netlist output format.
CVNL can generate a Seetrax Ranger netlist when it is given the -ranger3 command line option. A typical command line would be
$ cvnl -root PCB myfile.vnl -libs mylib1 mylib2 -ranger3 -o outputfn
Note that the root module may not have ports for a Ranger3 output.
Note that it is not possible to pass a bus into a component in the Ranger3 format: therefore every connection to a component from a bus must be spelled out separately. This does not mean that busses cannot be declared as such with ranged declarations: they simply may not be used as such.
The pin numbers generated in the Ranger3 output format are in the order found on the declaration of the component. This will be the order of the connections in a positional instantiation, but for an associative instantiation (using dot format) (which is preferred for large devices) the order in the instance is clearly unimportant.
The cvnl program is able to read a Verilog hierarchic netlist and write out a flat Verilog netlist containing a single module. It may be run as follows:
$ cvnl -vnl -oHowever it is preferable to flatten with cv2.100/200 these days.-root +
CVNL is a program which process a structural Verilog source file. The input is typically the output from cv2.100/200 where the -vnl option has been used.
To generate XNF for Xilinx series 3000 devices the program needs a command line with the following fields
cvnl -xnf -tech xi3000 -o
[ -device ] [ -root ] ...
The source files must contain Verilog definitions of the root module and all modules structurally instantiated in its components. Anything not defined, or defined as primitive, is assumed to be a leaf in the technology library in use. If such a module is not in the named library, then an error is generated, or if the autogen command line flag is given, it generates a module of the same name in the netlist (so that xnfmerge or similar have later to resolve them).