/**
 * \file
 *
 * \brief Instance description for CRCCU
 *
 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
 *
 * \asf_license_start
 *
 * \page License
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 *
 * 3. The name of Atmel may not be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * 4. This software may only be redistributed and used in connection with an
 *    Atmel microcontroller product.
 *
 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 * \asf_license_stop
 *
 */

#ifndef _SAM4L_CRCCU_INSTANCE_
#define _SAM4L_CRCCU_INSTANCE_

/* ========== Register definition for CRCCU peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CRCCU_DSCR             (0x400A4000U) /**< \brief (CRCCU) Descriptor Base Register */
#define REG_CRCCU_DMAEN            (0x400A4008U) /**< \brief (CRCCU) DMA Enable Register */
#define REG_CRCCU_DMADIS           (0x400A400CU) /**< \brief (CRCCU) DMA Disable Register */
#define REG_CRCCU_DMASR            (0x400A4010U) /**< \brief (CRCCU) DMA Status Register */
#define REG_CRCCU_DMAIER           (0x400A4014U) /**< \brief (CRCCU) DMA Interrupt Enable Register */
#define REG_CRCCU_DMAIDR           (0x400A4018U) /**< \brief (CRCCU) DMA Interrupt Disable Register */
#define REG_CRCCU_DMAIMR           (0x400A401CU) /**< \brief (CRCCU) DMA Interrupt Mask Register */
#define REG_CRCCU_DMAISR           (0x400A4020U) /**< \brief (CRCCU) DMA Interrupt Status Register */
#define REG_CRCCU_CR               (0x400A4034U) /**< \brief (CRCCU) Control Register */
#define REG_CRCCU_MR               (0x400A4038U) /**< \brief (CRCCU) Mode Register */
#define REG_CRCCU_SR               (0x400A403CU) /**< \brief (CRCCU) Status Register */
#define REG_CRCCU_IER              (0x400A4040U) /**< \brief (CRCCU) Interrupt Enable Register */
#define REG_CRCCU_IDR              (0x400A4044U) /**< \brief (CRCCU) Interrupt Disable Register */
#define REG_CRCCU_IMR              (0x400A4048U) /**< \brief (CRCCU) Interrupt Mask Register */
#define REG_CRCCU_ISR              (0x400A404CU) /**< \brief (CRCCU) Interrupt Status Register */
#define REG_CRCCU_VERSION          (0x400A40FCU) /**< \brief (CRCCU) Version Register */
#else
#define REG_CRCCU_DSCR             (*(RwReg  *)0x400A4000U) /**< \brief (CRCCU) Descriptor Base Register */
#define REG_CRCCU_DMAEN            (*(WoReg  *)0x400A4008U) /**< \brief (CRCCU) DMA Enable Register */
#define REG_CRCCU_DMADIS           (*(WoReg  *)0x400A400CU) /**< \brief (CRCCU) DMA Disable Register */
#define REG_CRCCU_DMASR            (*(RoReg  *)0x400A4010U) /**< \brief (CRCCU) DMA Status Register */
#define REG_CRCCU_DMAIER           (*(WoReg  *)0x400A4014U) /**< \brief (CRCCU) DMA Interrupt Enable Register */
#define REG_CRCCU_DMAIDR           (*(WoReg  *)0x400A4018U) /**< \brief (CRCCU) DMA Interrupt Disable Register */
#define REG_CRCCU_DMAIMR           (*(RoReg  *)0x400A401CU) /**< \brief (CRCCU) DMA Interrupt Mask Register */
#define REG_CRCCU_DMAISR           (*(RoReg  *)0x400A4020U) /**< \brief (CRCCU) DMA Interrupt Status Register */
#define REG_CRCCU_CR               (*(WoReg  *)0x400A4034U) /**< \brief (CRCCU) Control Register */
#define REG_CRCCU_MR               (*(RwReg  *)0x400A4038U) /**< \brief (CRCCU) Mode Register */
#define REG_CRCCU_SR               (*(RoReg  *)0x400A403CU) /**< \brief (CRCCU) Status Register */
#define REG_CRCCU_IER              (*(WoReg  *)0x400A4040U) /**< \brief (CRCCU) Interrupt Enable Register */
#define REG_CRCCU_IDR              (*(WoReg  *)0x400A4044U) /**< \brief (CRCCU) Interrupt Disable Register */
#define REG_CRCCU_IMR              (*(RoReg  *)0x400A4048U) /**< \brief (CRCCU) Interrupt Mask Register */
#define REG_CRCCU_ISR              (*(RoReg  *)0x400A404CU) /**< \brief (CRCCU) Interrupt Status Register */
#define REG_CRCCU_VERSION          (*(RoReg  *)0x400A40FCU) /**< \brief (CRCCU) Version Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#endif /* _SAM4L_CRCCU_INSTANCE_ */
