EDSAC-2: Sid Barton replaces an EDSAC-2 chassis in the machine.
EDSAC-2: Sid Barton replaces an EDSAC-2 chassis in the machine.
EDSAC-2 was designed and built in the University of Cambridge Computer Laboratory. It provided the main computing service for the University between 1958 and 1965. It implemented floating-point (32-bit mantissa and 8-bit exponent) and followed the von Neumann stored-program design pattern. Primary storage available to the user initially consisted of 1024 words of 40 bits, addressable in half-word locations. A second fixed-store contained a permanent library of scientific, I/O and debugging routines, with a special instruction implemented to invoke these routines (the 59 Order).
The principal improvements over the world-leading EDSAC-1 computer, that was its predecessor in the department, were:
DJW26: The six portfolio binders received.
In 2026, a set of six portfolio springback binders of EDSAC-2 schematics together with a microcode listing and other documents was returned to the Computer Laboratory. This came from the house of DJ Wheeler, so it is currently called the DJW26-portfolio. The binders will be handed over to the University Library soon. Meanwhile, these materials are being studied. Some preliminary findings are being put on this page. Also, interviews with extant users have been recorded and can be released soon.
A complete reverse-engineering and proof of correctness of the EDSAC-2 microcode, based on the DJW26 portfolio, is being assembled on these pages.
This folder is very interesting - no valves, but transistors and a ferrite core shift register! [FIFO queue? ]
Not yet digitised by DJG.
Not yet digitised by DJG.
Creed High Speed Punch with check back. Type 3000. Circuit Manual - February 17th 1962
Again, this is transistorised (OC44 etc) but with some ferrite logic.
Not yet digitised by DJG.
Enclosed is a document entitled - "The Line Printer Buffer Store" that starts 'In orde to makes the best used of the "Hollerith" Parallel Printer on EDSAC 2 a buffer has been built. It consists of 80 x 12 ferrite core store and a number of flip-flops ...'
Otherwise, this might be a copy of Vol.4 - we need to play spot the difference.
Not yet digitised by DJG.
This springback binder contains a single sheet - a schematic for some ferrite logic.
As well as the six springback binders, there is an unbound pile of dyeline schematic prints. From the page titles, these appear, for now, to be schematics for the line printer and were probably in Binder 6 at some earlier time...
The schematics from binders 1 and 2 have mostly been digitised. The microcode had been OCR'd and largely validated for self-consistency. One edition of the fixed-store contents has been assembled into machine code and loaded into a simulator. Operational semantics have been written for each VLIW operation invoked by the microcode. This has formed the basis for a simulator that has, so far, correctly run four instructions from the `Hello World' program supplied with the GJD simulator. That program writes Hello World in dot matrix form on the display CRT, one of the output devices connected to EDSAC-2.
EDSAC-2 Microprogram core matrix (32x32) with drive and sense chassis around the edges
Naming: EDSAC-2 uses single-letter acronmys in most places, such as 'M' for the accumulator. This is painful for the modern user, or when coding the semantics formally, or just when searching textually for a given item. With only 26 letters in the arabic alphabet, letters are commonly reused for different things, although a partially complete disambiguation sheet is provided in the DJW26 documentation. In this analysis, I have avoided single-letter names for those reasons. I have lighty renamed. For instance, I have put the letter 'R' in front of all the register names.
Bit numbering: The 41-bit registers are indexed -1 through to 39. The nominal most-significant bit is bit 0, with bit -1 being used for carry and overflow detection (except in memory, where it is a parity bit). Bit 39 is the least-significant bit when holding a fixed point fraction. The 11-bit registers are indexed 9 through to 19. Eg. RW[e9..19] dentotes the whole of register RW. These bit names are used since they align with the same bit numbers in RX when data is transferred to and from RX in the BIU for memory (or conceivably I/O) into the control unit registers. Actually, there is lane steering (controlled by the G2 flip-flop), so when loading from an odd address, it is bits RX[e29..39] aka RX[v10..0] that are moved to or from RW[e9..19].
Bit inserts and bit extracts: Since part of this analysis emits the EDSAC-2 design as Verilog, and since modern computing generally numbers bits from the right with positive integers, it is necessary to distinguish between bit-fields expressed in EDSAC form from those expressed in standard RTL. Here we distinguish EDSAC with conventional bit numbering by inserting either the letter 'e' or the letter 'v' (for Verilog) right after the open square bracket.
For example, the program counter (or sequence control register) in EDSAC-2 is RR. It has 11 bits. Both RR[e9..19] and RR[v10..0] dentote the whole of register RR, as does not bit-indexing it at all.
Note: the EDSAC bit numbering makes sense for the arithmetic mill registers, as the numbering is the power-of-two weighting (if negated) for fixed-point fractions (as explained in Programing For EDSAC-2).
Registers in Memory: EDSAC and EDSAC-2 refer to an instruction as an 'order' and the opcode is an 'ordercode'. This causes little trouble to the modern reader. On the other hand, the terms 'registers in memory' and 'memory registers' are used in the EDSAC documentation. This is too jarring for the modern reader, I fear, so I have modernised and use the term 'location' to denote a place in memory. Note that the EDSAC-2 memory bus has a word width of 40 bits plus parity. That is the same length as the accumulator register RM. But instructions are 20-bits long, with two being fetched over the memory bus at once. I shall call the 20-bit quantity a half-word, with the bus transferring a whole word at once. The memory itself is half-word addressed. Hence the 11-bit program counter RP, or any other modifier register etc., points to memory on a half-word granularity. EDSAC-2 is big endian, meaning the high order 20 bits of a word are addressed when the lsb of RP, ie RP[e19] or RP[v0], is zero.
The EDSAC-2 central processor unit divides into two main parts plus a memory and I/O third part.
The arithmetic mill is shown at the top. This is implemented using 41-bit registers and an adder. The user programming model registers are M, L and K, here marked RM, RL and RK.
Each register is implemented as a broadside transparent latch, so, to achieve a master-slave edge-triggered effect, such as when left-shifting the accumulator, the current contents need to be explictly transferred into a master section, such as RF for RM using one microcoded step and then transfered back again, modified accordingly. Hence, the system operates a bit like the 8008 microprocessor, being based on two-phase, non-overlapping clock signals.
The control unit is shown lower left. It has a second adder, the control adder. The registers that form part of the user's programming model are RS, RT and RB. RB is the program counter. In later versions of EDSAC-2, a further modifier register, RB was added, supported with new instuctions and as implemented in the GJD simulator. This is not documented in DJW26.
The bus inteface unit (BIU), which also serves for I/O is shown centre right. This contains the RX register that is the source and destination for all data entering or leaving the CPU. There is also a further 40-bit register, RD inside the BIU for output data. I shall add an expanded diagram.
Note that memory is always accessed at the full-word addressed by the top ten bits of RP, i.e. RP[v10..1]. Hence directly addressable memory in EDSAC-2 is 1024x40 or 1024 words, each of 40 bits.
Contemporary parlance divides computer memory into registers, main (aka primary) store and secondary storage (e.g. tapes, disks, SSDs). EDSAC-2 has the the same three forms in its memory heirarchy. [DJG will add a note about caches here, known as the slave store.]
Unfortunately, 'main memory' has a special meaning in EDSAC-2 terms. It refers specifically to 16k words of primary store that were added to the machine at a date after the DJW26 portfolio was frozen. Hence we have a potential source of confusion of terms here!
As already mentioned, EDSAC-2 has a 1024x40 primary storage address space. This is used for both code and data since it is essentially a von Neumann machine. But, even without the 'main store' extension, this address space is replicated two-fold, being partitioned into the fixed and the free 'pages' or 'segments'. The contemporary documentation does not use such a term: it just speaks of two stores. The fixed store is also known as the 'wired' store in some places. It is intended to act like a ROM, containing permanently-installed subroutines. These are invoked with a dedicated instruction (order 59) whose microcode saves the user program counter (that addresses the free store) and commences operation in fixed address space. The fixed space does not seem to be overly fixed, since the first hundred or so words of it are used as scratchpad for these routines and to store the user return address and user's RS content. I am finding out a bit more about that right now.
Also, the machine is not strictly von Neumann, since when executing out of fixed store, certain instructions can access data in the free store! The precise semantics of these is documented as 'guessed' in the GJD simulator. But the microcode from DJW26 is shining a light ...
Note that ferrite core store has destructive read out. Hence, operands and instructions read must be written back again to give the impression of non-destructive read. For EDSAC-2, the write-back can be seen as an explicit step in the microcode. But, in cases like an exchange instruction or a store of just one half-word to a 40-bit word, the data written back is accordingly not the same as the data read. Hence, no write lanes, as we'd call them today, are needed for main store write. What keeps the fixed store 'fixed' is not clear at the moment --- just careful programming?
EDSAC-2 was the world's first operational microcoded machine?
EDSAC-2 ran each instruction by executing a sequence of VLIW (very-long instruction word) instructions (or uops) for each user instruction.
CHECK WHAT THE PAPERS CALL THE uops PLEASE.
Each uop had a name and an address. The names broadly corresponded to the function. For instance, names startin with 'I' implement instruction fetch and those starting with 'J' implement jumps and branches. The address was two-dimensional, locating the uop in a 32-by-32 virtual grid. Each uop was held in the hardwired microcode ROM that was implemented with ferrite cores. The cores were placed in plastic holders, with up to 16 cores per holder and the holders being in something like an 8-by-8 grid. There could be up to four cores at a given address, owing to predicated operation (see below).
Each core implements a four-input AND gate whose output is feeds some number of VLIW sense lines. The input terms and the output sense wires were all threaded through the core (number of turns on the sense wires was?). The microcode ROM data is represented by the physical routing of the sense wires thorough just the cores that should trigger it.
An EDSAC-2 microcode core holder or frame">
The basic structure of the microcode is one-hot, with just one uop being active at any instance. The successor was activated on the next clock pulse of the master clock. (Unlike EDSAC-1, EDSAC-2 was fully static and could be single-steped one uop at a time, with a large panel of neon indicators showing the bits in all the registers and micro-architectural flip-flops.)
Two of the input wires accorded to the row and column of the core's address. Up to two further 'conditional bias' wires provide conditional operation. Conditional operation is needed for user-level IF-THEN logic required for conditional branche orders. But it is also needed at for microcode level loops, such as floating-point normalisation steps. Finally, conditional operation also supports something akin to subroutine calling at the microcode level.
The microcode subroutines are not implemented with a saved return address. They are just a means of invoked a shared common sequence of operations from more than one call site. This is achieved with the provision of so-called 'Y' flip-flops, that the microcode can freely set or clear before jumping to a shared sequence. The sequence is terminated with jumps conditional on the 'Y' flops so that the next step accords with the 'callers' intentions.
... under construction ... July 2026.
... under construction ... July 2026.
PDF(C) CC4BY 2026 DJ Greaves, University of Cambridge. COMPUTER LABORATORY RELICS PROJECT