Department of Computer Science and Technology

Alexandre Joannou

I am a senior researcher in the Computer Architecture Group at the University of Cambridge Computer Laboratory. I completed my PhD thesis , High-performance memory safety - Optimizing the CHERI capability machine, supervised by Professor Simon More, during which I worked on compressed capabilities and efficient tagged memory. I also worked on a formal model of the CHERI MIPS extensions, written in the L3 ISA modeling language. I worked on an ISA modeling framework in the Bluespec System Verilog language, and implementing RVBS (pronounced "rubs"), a RISC-V model (and contributed back to the RISC-V ISA manual in the process). I contribute to the TestRIG effort aiming at providing a framework to help verify RISC-V implementation using fuzz testing. I actively contribute to blarney, a Haskell library for hardware description.

I have been interested to explore the design space around synthesizable ISA-level description. I worked on RVBS which aims to provide a synthesizable RISC-V core from a "pseudo-code-like" code base, close to the instruction semantic descriptions found in ISA documents. It provides a very simple micro architecture and focuses on ease of instruction description and aggregation. I also worked on Pebbles, a RISC-V core framework which aims to provide a choice of multiple possible micro-architectures for a single shared ISA-level description.

I am generally interested in better abstractions for hardware design, modern toolchains and hardware description languages with powerful expressive features, and factorising hardware descriptions and deriving multiple artifacts (simulation executable, synthesizable RTL description, Sat/SMT descriptions of in source assertions...) from a single code base to aid circuit design. This has been what I focused on when contributing to blarney.

And besides all this, I am always keen to go bouldering / sports climbing, and more recently, cycling as well.

Publications

  • Franz A. Fuchs, Jonathan Woodruff, Peter Rugg, Marno van der Maas, Alexandre Joannou, Alexander Richardson, Jessica Clarke, Nathaniel Wesley Filardo, Brooks Davis, John Baldwin, Peter G. Neumann, Simon W. Moore, and Robert N. M. Watson. Architectural Contracts for Safe Speculation, Proceedings of the 2023 IEEE 41st International Conference on Computer Design (ICCD). Washington, DC, USA, November 6-8, 2023
  • Nathaniel Wesley Filardo, Brett F. Gutstein, Jonathan Woodruff, Sam Ainsworth, Lucian Paul-Trifu, Brooks Davis, Hongyan Xia, Edward Tomasz Napierala, Alexander Richardson, John Baldwin, David Chisnall, Jessica Clarke, Khilan Gudka, Alexandre Joannou, A. Theodore Markettos, Alfredo Mazzinghi, Robert M. Norton, Michael Roe, Peter Sewell, Stacey Son, Timothy M. Jones, Simon W. Moore, Peter G. Neumann, and Robert N. M. Watson. Cornucopia: Temporal Safety for CHERI Heaps, Proceedings of the 41st IEEE Symposium on Security and Privacy (Oakland 2020). San Jose, CA, USA, May 18-20, 2020
  • Kyndylan Nienhuis, Alexandre Joannou, Thomas Bauereiss, Anthony Fox, Michael Roe, Brian Campbell, Matthew Naylor, Robert M. Norton, Simon W. Moore, Peter G. Neumann, Ian Stark, Robert N. M. Watson, and Peter Sewell. Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process, Security and Privacy 2020: Proceedings of the 41st IEEE Symposium on Security and Privacy (SP), May 2020
  • Jonathan Woodruff, Alexandre Joannou, Hongyan Xia, Anthony Fox, Robert Norton, Thomas Bauereiss, David Chisnall, Brooks Davis, Khilan Gudka, Nathaniel W. Filardo, A. Theodore Markettos, Michael Roe, Peter G. Neumann, Robert N. M. Watson, and Simon W. Moore. CHERI Concentrate: Practical Compressed Capabilities, IEEE Transactions on Computers, 10.1109/TC.2019.2914037, IEEE, 2019
  • Brooks Davis, Robert N. M. Watson, Alexander Richardson, Peter G. Neumann, Simon W. Moore, John Baldwin, David Chisnall, James Clarke, Nathaniel Wesley Filardo, Khilan Gudka, Alexandre Joannou, Ben Laurie, A. Theodore Markettos, J. Edward Maste, Alfredo Mazzinghi, Edward Tomasz Napierala, Robert M. Norton, Michael Roe, Peter Sewell, Stacey Son, and Jonathan Woodruff. CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment, Proceedings of 2019 Architectural Support for Programming Languages and Operating Systems (ASPLOS’19). Providence, RI, USA, April 13-17, 2019
  • Kyndylan Nienhuis, Alexandre Joannou, Peter Sewell. Proving security properties of CHERI-MIPS, 25th Automated Reasoning Workshop, 2018
  • Hongyan Xia, Jonathan Woodruff, Hadrien Barral, Lawrence Esswood, Alexandre Joannou, Robert Kovacsics, David Chisnall, MichaelRoe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alex Richardson, Simon W. Moore, and Robert N. M. Watson. CheriRTOS: A Capability Model for Embedded Devices, Proceedings of the 2018 IEEE 36th International Conference on Computer Design (ICCD). Orlando, FL, USA, October 7-10, 2018.
  • Alexandre Joannou, Jonathan Woodruff, Robert Kovacsics, Simon W. Moore, Alex Bradbury, Hongyan Xia, Robert N. M. Watson, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alfredo Mazzinghi, Alex Richardson, Stacey Son, and A. Theodore Markettos. Efficient Tagged Memory, Proceedings of the 2017 IEEE 35th International Conference on Computer Design (ICCD). Boston, MA, USA, November 5-8, 2017.
  • David Chisnall, Brooks Davis, Khilan Gudka, David Brazdil, Alexandre Joannou, Jonathan Woodruff, A. Theodore Markettos, J. Edward Maste, Robert Norton, Stacey Son, Michael Roe, Simon W. Moore, Peter G. Neumann, Ben Laurie, and Robert N. M. Watson. CHERI-JNI: Sinking the Java security model into the C, Proceedings of the 22nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2017). Xi'an, China, April 8–12, 2017.
  • Robert N.M. Watson, Robert M. Norton, Jonathan Woodruff, Simon W. Moore, Peter G. Neumann, Jonathan Anderson, David Chisnall, Brooks Davis, Ben Laurie, Michael Roe, Nirav H. Dave, Khilan Gudka, Alexandre Joannou, A. Theodore Markettos, Ed Maste, Steven J. Murdoch, Colin Rothwell, Stacey D. Son, and Munraj Vadera. Fast Protection-Domain Crossing in the CHERI Capability-System Architecture, IEEE Micro vol. 36 no. 5, p. 38-49, Sept.-Oct., 2016

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