Yes/No Test Wrapper

Using Verilog or similar, one can write a test wrapper for a design that produces a single bit of output: yes or no. The wrapper has built in to it a model of the design under test and, for each output compares the the values coming from that model and the model under test using `==' or similar.

in Verilog, a simple example where we are testing a NAND gate, is


         reg fail;              // one such fail variable for whole test
         initial fail = 0;

         initial @(posedge end_of_simulation) if (fail) $display("Failed");
                 else $display("Passed");


         // For each output or module under test, we do the following

         NAND2 device_under_test(outp, ina, inb);
         assign model_output = ~(ina & inb);
         always @(posedge teststrobe) if  (model_output != outp) fail <= 1;

Typically there will be many such statements that update the `fail' variable. (Such a wrapper is not synthesisable beacuse of this.)

Yes/No wrappers allow the results for many simulations run as batch jobs to be quickly analysed. The simulations typically vary in their parametric settings, enabling the fact that, for instance, a design fails at low temperature and high supply voltage to be quickly determined.

Test programmes based on test vectors can perform a similar function, but only provided the output and input sequences are identical for each run. The Yes/No wrapper allows the stimulus input sequences to be a parameter varied from simulation to simulation.