Simulation is a time-intensive method of verifiying that a design performs its desired function.
Set-hold errors from the simulator are not a reliable means of checking that the design will run at speed, since signals may arrive after the hold time when intended to arrive before the set-up time or the critical path may not be excercised during the simulation.
A static timing analyser works from all D-inputs back along the netlist finding the longest paths and then reporting on the maximum clock speed.
Such a tool needs to know which paths are not being used in a design, or which will be static during operation, since these will typically be routed with slow nets. It takes a list of these, typically manually generated, and discounts them from the analysis.
The xdelay command on Thor is such a tool and can be used on a Xilinx .lca file. Try it.