Register Transfer Language

    module TEST(p, q, clk);
       input clk;
       input [4:0] p, q;  
       input r;
       reg [4:0] a, b;
       always @(posedge clk) begin
	     b <= (r) ? q : a;
	     if (p == 3) a <= a + 1; else a <= q;
	     end
    endmodule   

// a generated by CBG CSYN
// CBG CSYN Verilog hdl system.  Release 2.18c. (Oct 97) 
// cv2 test.cv -vnl -root TEST -o a 
// User=djg 
module TEST(p, q, clk);
  wire [4:0] b;
  wire [4:0] a;
  input r;
  input [4:0] q;
  input [4:0] p;
  input clk;
  CVMUX2  i10043(u10043, r, q[0], a[0]);
  CVDFF  u10044(b[0], u10043, clk, 1, 0, 0);
  CVMUX2  i10042(u10042, r, q[1], a[1]);
  CVDFF  u10045(b[1], u10042, clk, 1, 0, 0);
  CVMUX2  i10041(u10041, r, q[2], a[2]);
  CVDFF  u10046(b[2], u10041, clk, 1, 0, 0);
  CVMUX2  i10040(u10040, r, q[3], a[3]);
  CVDFF  u10047(b[3], u10040, clk, 1, 0, 0);
  CVMUX2  i10039(u10039, r, q[4], a[4]);
  CVDFF  u10048(b[4], u10039, clk, 1, 0, 0);
  CVINV  i10037(u10037, a[0]);
  CVMUX2  i10038(u10038, u10025, u10037, q[0]);
  CVDFF  u10049(a[0], u10038, clk, 1, 0, 0);
  CVXOR2  i10035(u10035, a[0], a[1]);
  CVMUX2  i10036(u10036, u10025, u10035, q[1]);
  CVDFF  u10050(a[1], u10036, clk, 1, 0, 0);
  CVXOR2  i10033(u10033, u10026, a[2]);
  CVMUX2  i10034(u10034, u10025, u10033, q[2]);
  CVDFF  u10051(a[2], u10034, clk, 1, 0, 0);
  CVXOR2  i10031(u10031, u10027, a[3]);
  CVMUX2  i10032(u10032, u10025, u10031, q[3]);
  CVDFF  u10052(a[3], u10032, clk, 1, 0, 0);
  CVINV  i10019(u10019, p[0]);
  CVINV  i10020(u10020, p[1]);
  CVOR2  i10021(u10021, u10019, u10020);
  CVOR2  i10022(u10022, u10021, p[2]);
  CVOR2  i10023(u10023, u10022, p[3]);
  CVOR2  i10024(u10024, u10023, p[4]);
  CVINV  i10025(u10025, u10024);
  CVAND2  i10026(u10026, a[0], a[1]);
  CVAND2  i10027(u10027, u10026, a[2]);
  CVAND2  i10028(u10028, u10027, a[3]);
  CVXOR2  i10029(u10029, u10028, a[4]);
  CVMUX2  i10030(u10030, u10025, u10029, q[4]);
  CVDFF  u10053(a[4], u10030, clk, 1, 0, 0);
endmodule