Register Transfer Language

In RTL there is a list of assignments which declare the next state in terms of the current state.
  • All ifs must have an else satatement,
  • The list is unordered. 
    
    module TEST(p, q, clk);

       input clk;
       input [4:0] p, q;  
       input r;

       reg [4:0] a, b;


       always @(posedge clk) begin


	     b <= (r) ? q : a;

	     if (p == 3) a <= a + 1; else a <= q;



	     end
    endmodule

  • If we drop the requirement that there is always an else, then the default action is for the register to be reloaded with its previous value.