Port Typing and Interconnection Rules
Some CAD suites have typed ports and rules about what type combinations
may be interconnected by a net. These rules can either be mandatorary
or just flag warnings when violated.
In Cambridge HDL we find the following port types:
[IN ] an input,
[OUT] an output (also generally known as IO type),
[TRI] a tri-state output,
[BI] a bidirectional port.
In Verilog the same types are defined with the
keywords input, output and, for the last two, inout.
Cambridge HDL has two Net types
[IO] a singly driven net,
[TRI] a tri-state net.
and in Verilog these net types are introduced with the
keywords wire, tri.
Rules for a net of type IO:
must connect to exactly one port of type OUT,
may connect to any number of ports of type IN
Rules for a TRI net:
may connect to any number of ports of type TRI,
may connect to any number of ports of type BI,
may connect to any number of ports of type IN.
Power supplies.
Net names such as VCC and GND are sometimes available as OUT
types. These may be connected to unused device inputs.
In higher level languages (e.g. behavioural Verilog) constants
such as 0 or 1 are used, or integers when assigned to busses.