ALU | Arithemetic and logic unit. |
ASIC | Application specific integrated circuit. |
BICMOS | A process with both CMOS and bipolar transistors on one die. |
CAD | Computer aided design. |
CAE | Computer aided enigneering. |
CAM | Computer aided manufacture. |
CLB | Configurable logic block. |
CRC | Cyclic redundancy check (added to end of a data frame). |
CMOS | Complimentry metal oxide of silicon. |
DRAM | Dynamic random access memory. |
DMA | Direct memory access. |
DSP | Digital signal processor/ing. |
ECL | Emitter coupled logic. |
EMC | Electromagnetic compatibility. |
EMI | Electromagnetic ingress or i(m)missions (sic). |
FET | Field effect transistor. |
FPGA | Field programmable gate array. |
GaAs | Gallium Arsenide. |
HDL | Hardware description language. |
IEEE | Institure of electrical and electronic engineers. |
JTAG | Joint technical advisorary group |
LSI | Large scale integration (say about 5000 gates, 10000 transistors). |
LCA | Logic cell array. |
MCM | Multi-chip module. |
MSI | Medium scale integration (i.e. the larger ttl devices). |
NRE | Non recurring engineering costs. i.e paid once per design. |
PAL | Programmable array logic. |
PCB | Printed circuit board. |
PIN | Personal identification number. |
RTL | Register transfer level. |
SSI | Small scale integration (i.e. about 4 gates on a chip). |
TTL | Transistor-transistor logic. |
Verilog | An HDL language in wide use (not an acronym). |
VHDL | VHSIC Hardware Description Language |
VHSIC | Very High Speed Integrated Circuit |
VNL | Verilog netlist. |
VCO | Voltage controlled oscillator. |
VLSI | Very large scale integration (big chips). |
XNF | Xilinx netlist format. |