Finite State Machine Specification

All synchronous circuits are finite-state machines, but it is sometimes helpful to express them as such, using abstract FSM specifications.

This level of specification may still be considered an RTL since the number of flip-flops has been implicitly specified by the designer. If `one hot' encoding is used, then the number of flops is equal to the number of states, otherwise it is lower bounded by log-base-two of the number of states.

Here is an example FSM definition in a made up language with

  DEFFSM 
     CLK = clk;
     INPUTS = reset, prime, trigger;
     STATES = { running, waiting, idle };
     CODING = ONEHOT;
     TRANSITIONS =
          idle: prime -> waiting;
          waiting: reset -> idle, trigger -> running;
          running: * -> idle;

  ENDFSM

The coding is given as ONEHOT and there are three states, so three flip-flops are implied. If the coding was BINARY, only two flip-flops would be required. For output. It is assumed that the names of the states are available for use in RTL expressions outside the FSM definition.