An example circuit and its netlist

The format of a component instance in the following HDL is

   component  instance_name : type_name (wire1, wire2 ...... wireN);

Here is the HDL version of the divide-by-five counter

       begin circuitone;
         clock :  CLOCK(clk);
         ff1   :  DFF(clk, a, q1, qb1);
         ff2   :  DFF(clk, q1, q2, qb2);
         ff3   :  DFF(clk, q2, q3, qb3);
         nor   :  NOR2(a, q2, q3);
      end circuit;

Note that this circuit, called circuitone has no (explicit) hierarchy and no inputs or outputs. These can be added

      begin subcircuit(clk, rst, q2);
         input clk, rst;
         output q2;
         ff1   :  DFFR(clk, rst, a, q1, qb1);
         ff2   :  DFFR(clk, rst, q1, q2, qb2);
         ff3   :  DFFR(clk, rst, q2, q3, qb3);
         nor   :  NOR2(a, q2, q3);
      end subcircuit;