Exercise: Write down the resolution function for a 6 value logic system where the two new states are a weak logic zero and a weak logic one (This is useful for pullup or pulldown resistors used in open collector logic etc). Actually, there maybe more than one sensible resolution function.
The weak signals lose out to everything but a Z, where they prevail and two different weaks produce an X. Discuss whether banning multiple weak drivers of one net is necessary via port typing rules.
Exercise: Consider whether the 6 value logic system can model resistors in series with nets, rather than simply resistors with one end to the power supply. Explain how such series resistors can form part of a poor-man's tri-state system.
It should be sufficient. A single, non-tri state device with reistors in series with its outputs can be connected to a tri-state bus to be read when all other drivers are Z. Sinclair did this in the ZX80.
Exercise: Consider the truth table for an XOR gate under the four value logic system when the two inputs are connected together. How does this reflect on the power of the four value logic system ?
The gate model cannot tell that its output would always be zero.
Exercise: In certain chips, redundant circuitry is included which can be activated if their is a defect. Given that the cost of patching a broken die using an ion beam or similar to activate the redundant logic has a processing cost equal to about 100 mm2 of processed wafer, is 90 percent successful and requires 10 percent additional area in the design, for what size and type of device is it suitable ? It is necessary to make various assumptions to answer this.
Sketch functions of overall working die cost without and without redundancy versus various parameters, especially size and original defect density and look at the crossover points. For certain memories it may be worthwhile.
Exercise: Ignoring the title, consider whether the `NAND4 Standard Cell' data sheet is intended for standard cell or gate array use ? What information about the cell is needed to prepare an audit of resources used in a design which has used this cell ? The audit refered to is typically a report generated by the CAD tools which gives summary information.
The cells used in standard cell and gate arrays are very similar and it is not possible to tell from the information given. However, the area resources used, if given, would give a hint, since a standard cell will have a dimensions in microns and a gate array cell will have a size in basic array cells.
Exercise: How large a binary counter can the illustrated PAL device implement ? Check that there are sufficient product terms for the most-significant bit.
The PAL has 7 flip-flops (this is a fictional PAL). Therefore a divide by 128 counter can be made. The most significant bit will need 7 product terms and all cells have 8 available, so this is possible.
Exercise: How true is the usual model of signal delay, where the whole signal changes voltage at one time, when we use field programmable gate arrays with high track resistance ? The conductors on FPGAs consist of many sections of real metalic conductor interconnected by the user-programmed connection points. There are then considerable resistances at points along each conductor's path. How would you estimate the various delays for the staggered arrival of a signal on each part of the net ?
The signal on an FPGA arrives at different points at different times, so models for each net are needed instead of adsorbing the delay into the driving gate as it can with a metal conductor on an ASIC. The ECAD workshop 4 demonstrates this.
Exercise: Compile some simple Verilog constructs and examine the gate-level output. Try to correlate any aspect of the input specification (except bus width) with the resulting gates. Is it hard to predict how many gates you are going to generate ?
For simple designs, it is easy to predict. Behavioural sections (always statements) of 10 or more lines length tend to become unpredictable. Fortunately today's ASICs easily support 100K gates and so size is not an issue, but FPGA users have fewer gates and worry about how large their designs will be.
Exercise: Write a 100 percent coverage test program for a 7400 quad NAND gate.
This can be done with four vectors.
Exercise: Consider the testability of devices with built in redundancy.
If the redundancy is automatic, then a signal indicating that it is active needs to be monitored. If the redundancy needs explicit activation, this is normally done during testing. If the redundancy requires blowing fuses in the device and this is intended to be done in the field during product lifetime, this requires a test input.
Exercise: Design a fault simulation algorithm whose expected running time is order nv where there are n nets and v vectors. Design a better algorithm.
The most simple fault simulator tries each of the 2n possible faults in turn and trys all vectors against it, leading to the quadratic run time. Clearly one can stop when a vector fails, producing a considerable, but linear reduction in time. Real fault simulators are covered under ECAD topics in part II.