# Reading e:/modeltech_ae/tcl/vsim/pref.tcl 
# Reading e:/rmf30/cluster/n105_cluster_sim/modelsim.tcl 
# e:/quartus/sopc_builder
# e:/quartus//bin/perl561
# Sopc_Builder Directory: e:/quartus/sopc_builder 
# @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 
# @@ 
# @@ setup_sim.do 
# @@ 
# @@ Defined aliases: 
# @@ 
# @@ s -- Load all design (HDL) files. 
# @@ re-vlog and re-vsim the design. 
# @@ 
# @@ c -- Re-compile memory contents. 
# @@ Builds C- and assembly-language programs 
# @@ (and associated simulation data-files 
# @@ such as UART simulation strings) for 
# @@ refreshing memory contents. 
# @@ Does NOT re-generate hardware (HDL) files 
# @@ 
# @@ w -- Sets-up waveforms for this design 
# @@ Each SOPC-Builder component may have 
# @@ signals 'marked' for display during 
# @@ simulation. This command opens a wave- 
# @@ window containing all such signals. 
# @@ 
# @@ l -- Sets-up list waveforms for this design 
# @@ Each SOPC-Builder component may have 
# @@ signals 'marked' for listing during 
# @@ simulation. This command opens a list- 
# @@ window containing all such signals. 
# @@ 
# @@ h -- print this message 
# @@ 
# @@ 
#  OpenFile "n105_cluster_sim.mpf" 
# Loading project n105_cluster_sim
s
# Model Technology ModelSim ALTERA vlog 5.7e Compiler 2003.07 Jul  9 2003
# -- Compiling module cpu0_data_master_arbitrator
# -- Compiling module cpu0_instruction_master_arbitrator
# -- Compiling module cpu1_data_master_arbitrator
# -- Compiling module cpu1_instruction_master_arbitrator
# -- Compiling module onchip_memory_0_s1_arbitrator
# -- Compiling module onchip_memory_1_s1_arbitrator
# -- Compiling module onchip_memory_2_s1_arbitrator
# -- Compiling module n105_cluster
# -- Compiling module cpu
# -- Compiling module instruction_fetch
# -- Compiling module instruction_decode
# -- Compiling module mem_access_unit
# -- Compiling module alu
# -- Compiling module shifter
# -- Compiling module branch_unit
# -- Compiling module condition_unit
# -- Compiling module reg_fetch
# -- Compiling module write_back
# -- Compiling module cpu0
# -- Compiling module cpu1
# -- Compiling module onchip_memory_0_lane1_module
# -- Compiling module onchip_memory_0_lane0_module
# -- Compiling module onchip_memory_0
# -- Compiling module onchip_memory_1_lane0_module
# -- Compiling module onchip_memory_1
# -- Compiling module onchip_memory_2_lane0_module
# -- Compiling module onchip_memory_2
# -- Compiling module test_bench
# 
# Top level modules:
# 	test_bench
# vsim +nowarnTFMPC test_bench 
# Loading e:/modeltech_ae/win32aloem/../win32aloem/convert_hex2ver.dll
# //  ModelSim ALTERA 5.7e Jul 1 2003 
# //
# //  Copyright Model Technology, a Mentor Graphics Corporation company, 2003
# //                         All Rights Reserved.
# //                   UNPUBLISHED, LICENSED SOFTWARE.
# //         CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
# //        PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
# //
# Loading work.test_bench
# Loading work.n105_cluster
# Loading work.cpu0_data_master_arbitrator
# Loading work.cpu0_instruction_master_arbitrator
# Loading work.cpu0
# Loading work.cpu
# Loading work.instruction_fetch
# Loading work.instruction_decode
# Loading work.mem_access_unit
# Loading work.alu
# Loading work.shifter
# Loading work.branch_unit
# Loading work.condition_unit
# Loading work.reg_fetch
# Loading work.write_back
# Loading work.cpu1_data_master_arbitrator
# Loading work.cpu1_instruction_master_arbitrator
# Loading work.cpu1
# Loading work.onchip_memory_0_s1_arbitrator
# Loading work.onchip_memory_0
# Loading work.onchip_memory_0_lane1_module
# Loading work.onchip_memory_0_lane0_module
# Loading work.onchip_memory_1_s1_arbitrator
# Loading work.onchip_memory_1
# Loading work.onchip_memory_1_lane0_module
# Loading work.onchip_memory_2_s1_arbitrator
# Loading work.onchip_memory_2
# Loading work.onchip_memory_2_lane0_module
# /test_bench/DUT/the_cpu0/the_cpu/the_instruction_decode/instruction_opcode
# /test_bench/DUT/the_cpu0/the_cpu/if_condition
# /test_bench/DUT/the_cpu1/the_cpu/the_instruction_decode/instruction_opcode
# /test_bench/DUT/the_cpu1/the_cpu/if_condition
w
run 3 us
