Many RTL synthesisers support an implied program counter (state machine inference):
reg [2:0] yout; always begin @(posedge clk) yout = 1; @(posedge clk) yout = 4; @(posedge clk) yout = 3; end
Some conditional event control may be possible, for instance, the second assignment could be changed to :
if (din) @(posedge clk) yout = 4;
10: (C) 2008-18, DJ Greaves, University of Cambridge, Computer Laboratory. |