Behavioural - `Non-Synthesisable' RTL continued

Schematic symbol and timing diagram for an edge-triggered RS flop.

   reg q;
   input set, clear;

   always @(posedge set) q = 1;
   always @(posedge clear) q = 0;

Here a variable is updated by more than one thread.

This component is used mainly in specialist phase-locked loops. It can be modelled in Verilog, but is not supported for Verilog synthesis. A real implementation typically uses 8 or 12 NAND gates in a relatively complex arrangement.

Hand-crafted circuit for the edge-triggered RS flop used in practice.