Levels of Modelling Abstraction

Our modelling system must support all stages of the design process, from design entry to fabrication. But we cannot model a complete SoC in detail and expect to simulate the booting of the O/S in reasonable time.

We typically use a model called an ESL Virtual Platform. And where we are interested in the details of a specific module, we need to mix components using different levels of modelling abstraction within a single virtual platform.

Levels commonly used are:

• Functional Modelling: The `output' from a simulation run is accurate.
• Memory Accurate Modelling: The contents and layout of memory is accurate.
• Untimed TLM: No time stamps recorded on transactions.
• Loosely-timed TLM: The number of transactions is accurate, but order may be wrong.
• Approximately-timed TLM: The number and order of transactions is accurate.
• Cycle-Accurate Level Modelling: The number of clock cycles consumed is accurate.
• Event-Level Modelling: The ordering of net changes within a clock cycle is accurate.

Other terms in use are:

• Programmer View Accurate: The contents of visible memory and registers is as per the real hardware, but timing may be inaccurate and other registers or combinational nets that are not designated as part of the `programmers view' may not be modelled accurately.
• Behavioural Modelling: Using a threads package, or other library (e.g. SystemC), hand-crafted programs are written to model the behaviour of each component or subsystem. Major hardware items such as busses, caches or DRAM controllers may be neglected in such a model.

The Programmer's View is often abbreviated as `PV' and if timing is added it is called `PV+T'.

The Programmer's View contains only architecturally-significant registers such as those that the software programmer can manipulate with instructions. Other registers in a particular hardware implementation, such as pipeline stages and holding registers to overcome structural hazards, are not part of the PV.