HOME
UP
  PREV
NEXT (Basic Bus: One initiator (II).)
Part II CST SoC D/M Slide Pack 1 (Intro+SocParts)
SoC Design : 2015/16: Twelve Lectures for CST Part II
Recommended Reading
Example: A Cellphone.
Introduction: What is a SoC 1/2 ?
Introduction: What is a SoC 2/2 ?
Hardware Design Flow
SoC Design Flow Diagram
Levels of Modelling Abstraction
Basic SoC Components
Simple Microprocessor: Bus Connection and Internals
A canonical D8/A16 Micro-Computer
Memory Address Mapping and Decode
ROM - Read Only Memory
A Basic Micro-Controller
Switch/LED Interfacing
UART Device
Programmed I/O
A SoC consists of interconnected IP Blocks
Illustrative, very simple SoC Bus.
Basic Bus: One initiator.
RAM - on chip memory (Static RAM).
Interrupt Wiring: General Structure for Uniprocessor
GPIO - General Purpose Input/Output Pins
Keyboard Controller (scan multiplexed type).
Counter/Timer Block
Video Controller: Framestore
Arbiter
Basic bus: Multiple Initiators.
DMA Controller
Network and Streaming Media Devices
Bus Bridge
Inter-core Interrupter (Doorbell/Mailbox)
Remote Debug (JTAG) Access Port
Clock Frequency Multiplier PLL and Clock Tree
Clock Domain Crossing Bridge
SoC Example - Raspberry Pi
Dynamic RAM : DRAM
DRAM Internal Block Diagram
DRAM & Controller (2).
DRAM & Controller (3).
Cache Design
SoC Example: Helium 210
SoC Example: Atmel SAM9645
Architecture: Bus and Device Structure
Basic Bus: One initiator (II).
Basic bus: Multiple Initiators (II).
Bridged Bus Structures.
Classes of On-Chip Protocol
Practical Bus Protocols on IP Blocks
BVCI Net-Level Protocol.
ARM AXI Bus: The Current Favourite
Supporting out-of-order operation using tags.
Network on Chip: Simple Ring.
Network on chip: Switch Fabrics.
Network on Chip: Higher Dimensions.
NoC Modelling
On-chip Busses Summary.