module shiftregdriver ( input logic clock_50m, input logic reset, output logic shiftreg_clk, output logic shiftreg_loadn, input logic shiftreg_out, output logic [15:0] buttons ); enum {COUNT0=0, /* 16 count values */ COUNT15=15, LOADING=16} CounterStates; logic [4:0] count; logic [8:0] clkdiv; logic clock_100k; always_ff @(posedge clock_50m) begin if (reset) clkdiv <= 0; else clkdiv <= clkdiv + 1; end always_comb begin clock_100k = clkdiv[8]; shiftreg_clk = clock_100k; end always_ff @(posedge clock_100k) begin if (reset) begin count <= LOADING; buttons <= 16'b0; end else if (count == LOADING) begin count <= 0; end else begin buttons[count] <= shiftreg_out; count <= count + 4'b1; end end always_comb shiftreg_loadn <= !(count==LOADING); endmodule