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RTL Operating Frequency and Power Estimation

RTL synthesis is relatively quick but produces a detailed output which is slow to process for a large chip - hence pre-synthesis energy and delay models are desirable.

Place and route will give accurate wiring lengths but is a highly time consuming investment in a given design point.

A simulation of a placed and routed design can give very accurate energy and critical path figures, but is likewise useless for 'what if' style design exploration.

A table of possible approaches:

- - Without Simulation - - Using Simulation -

Without Place and Route Fast - Design exploration.
Area and delay heuristics needed. Can generate indicative activity ratios to be used instead of simulation in further runs.

With Place and Route Static timing analyser will give an accurate clock frequency. Gold standard: only bettered by
measuring a real chip.

-	- Without Simulation -	- Using Simulation -
Without Place and Route	Fast - Design exploration. Area and delay heuristics needed.	Can generate indicative activity ratios to be used instead of simulation in further runs.
With Place and Route	Static timing analyser will give an accurate clock frequency.	Gold standard: only bettered by measuring a real chip.