RTL is not as expressive for algorithms or data structures as most software programming languages.
The concurrency model is that everything executes in lock-step. The programmer keeps all this concurrency in his/her mind.
Users must generate their own, bespoke handshaking and flow control between components.
Verilog and VHDL do not express when a register is live with data - hence automatic refactoring and certain correctness proofs are impossible.
| 27: (C) 2008-15, DJ Greaves, University of Cambridge, Computer Laboratory. |
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