Generative Forms

All hardware description languages and RTLs contain some sort of generate statement.

A generate statement is an itereative construct that is executed at compile time to generate multiple instances of a component. In Bluespec this is a complete, higher-order functional language, but in SystemVerilog we use the following:

 reg[3:0] values[0:4] = {5, 6, 7, 8, 9};

  generate
    genvar i;
    for (i=0; i < 5; i++)  begin: M1
      MUT mut(
      .out,
      .in(values[i]),
      .clk
      );
    end
  endgenerate

11: (C) 2008-15, DJ Greaves, University of Cambridge, Computer Laboratory.