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Part II CST SoC D/M Slide Pack 3 (Power)

  • Power, Performance and Technology
  • Basic Physics
  • Chip Dissipation
  • Detailed Delay Model.
  • Detailed Power Model.
  • Dynamic Frequency and Voltage Scaling Example (DVFS)
  • Semi-Custom Design (repeated slide)
  • 90 Nanometer Gate Length.
  • Deep submicron and Dark Silicon
  • Voltage Operating Point Adjustment
  • Power Saving Techniques
  • Save Power 1: Dynamic Clock Gating
  • Save Power 2: Dynamic Supply Gating
  • Future Trends