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Remote Debug (JTAG) Access Port

(Not lectured for part II).

Various forms exist: connected to bus or connected to a CPU core or both.

External access is often via the »JTAG port which is fairly slow, owing to bit-serial data format, so sometimes parallel bus connections are provided.

The basic facilities commonly provided are

Perform a bus read or write cycles,
Halt/continue/single-step the processor core,
Read/modify processor core registers,
Provide `watchpoints' which halt on certain address bus values.

In a typical setup the debugger (such as GNU gdb) runs on a remote workstation via a TCP connection carrying the RSP protocol to the debug target. For real silicon, the target is a JTAG controller (e.g. connected to the workstation via USB) whereas on a SystemC model it is an SC_MODULE that is listening for RSP on a unix socket.