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ABD - Sequential Logic Equivalence

Two implementations of a two-bit shift register.

They differ in amount of internal state.

They have equivalent observable behaviour (ignoring glitches).

Note, to implement larger delays, the design based on multiplexors might use more logic and less power then the design based on shifting, since fewer nets toggle on each clock edge.

24: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory.