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Structured ASIC

Structured ASIC (masked gate array on smaller die) tried to close gap between ASIC and FPGA

For example, two implementations of the same design (Xilinx EasyPath in 2005): »Xilinx EasyPath
Device NRE Unit cost
Spartan-3 FPGA: 0 12 USD
EasyPath E3S1500 75 KUSD 1 USD

Crossover at 6250 units.

Now entirley replaced with super-FPGAs ?

33: (C) 2008-12, DJ Greaves, University of Cambridge, Computer Laboratory.