SoC Design : 2011/12: 12 Lectures to CST II

A current-day system on a chip (SoC) consists of several different microprocessor subsystems together with memories and I/O interfaces. This course covers SoC design and modelling techniques with emphasis on architectural exploration, assertion-driven design and the concurrent development of hardware and embedded software. This is the ``front end'' of the design automation tool chain. (Back end material, such as design of individual gates, layout, routing and fabrication of silicon chips is not covered.)

A percentage of each lecture is used to develop a running example. Over the course of the lectures, the example evolves into a System On Chip demonstrator with CPU and bus models, device models and device drivers. All code and tools are available online so the examples can be reproduced and exercises undertaken. The main languages used are Verilog and C++ using the SystemC library.

Course has 15 or so topics covering:

• Verilog RTL design with examples. Event-driven simulation with and without delta cycles, basics of synthesis to gates algorithm and design examples. Structural hazards, pipelining, memories and multipliers.
• SystemC overview. The major components of the SystemC C++ class library for hardware modelling are covered with code fragments and demonstrations.
• Basic SoC Components and Bus Structures. CPU, RAM, Timers, DMA, GPIO, Network, Bus structure. Interrupts, DMA and device drivers. Examples. Basic bus bridging.
• ESL + Transactional Modelling. Electronic systems level (ESL) design. Architectural exploration. Firmware modelling methods. Blocking and non-blocking transaction styles. Approximate and loose timing styles. Queue and contention modelling. Examples.
• ABD: Assertions and Monitors. Types of assertion (imperative, safety, liveness, data conservation). Assertion-based design (ABD). PSL/SVA assertions. Temporal logic compilation of fragments to monitoring FSM.
• Further Bus Structures. Busses used in today's SoCs (OPB/BVCI, AHB and AXI). Glue logic synthesis. Transactor synthesis. Pipeline Tolerance. Network on chip.
• Engineering Aspects: FPGA and ASIC design flow. Cell libraries. Market breakdown: CPU/Commodity/ ASIC/FPGA. Further tools used for design of FPGA and ASIC (timing and power modelling, place and route, memory generators, power gating, clock tree, self-test and scan insertion). Dynamic frequency and voltage scaling.
• Future approaches Only presented if time permits. Non-examinable. Recent developments: BlueSpec, IP-XACT, Kiwi, Custom processor synthesis.

In addition to these topics, the running example will demonstrate a few practical aspects of device bus interface design, on chip communication and device control software. Students can run the examples on PWF (please ask for links).