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Dynamic RAM : DRAM

DRAMs for use in PCs are mounted on SIMMS or DIMMS, but for embedded applications, often just soldered to the main PCB. Normally one bank of DRAM is shared over many sub-systems in, say, a mobile phone.

SoC DRAM compatibility might be a generation behind workstation DRAM: e.g. using DDR2

Typical DRAM pin connections:
Clk+/- Clock (200MHz)
Ras- Row address strobe
Cas- Column address strobe
We- Write enable
dq[63:0] Data in/out
reset Power on reset
wq[7:0] Write lane qualifiers
ds[7:0] Data stobes
dm[7:0] Data masks
cs- Chip select
addr[15:0] Address input
bs[2:0] Bank select
spd[3:0] Serial presence detect

High bandwidth: 64 bits times 400 MHz giving 25.6 Gb/s peak.

High capacity: Example 1 Gbyte DIMM made of 8 chips.

High latency: 20 clock cyles access time to a closed bank. Worse if a bank is already open at the wrong place.

17: (C) 2008-11, DJ Greaves, University of Cambridge, Computer Laboratory.