NoC Modelling

Do we want to model every contention point and queuing detail ?

Use a high-level model: Treat the NoC just as a square array corresponding to the floor plan of the chip and in each entry we hold a running average local utilisation.

• Add delay penalty to traversing transaction based on 1/(1-p),
• Log local energy consumption proportional to delay,
• Target routing protocol can be used unmodified or skipped.

Problems:

• Transactions may be out of order if using large quantum LT model.
• Deadlock may be missed ?