Structural Verilog

Level 1/3: Structural Verilog : Structural, Heirarchic, Netlist

        module subcircuit(clk, rst, q2);
           INPUT clk, rst;
           OUTPUT q2;
           DFFR Ff_1(clk, rst, a, q1, qb1),
                Ff_2(clk, rst, q1, q2, qb2),
                Ff_3(clk, rst, q2, q3, qb3);
          NOR2 Nor2_1(a, q2, q3);
        endmodule

Just a netlist.

There are no assignment statements that transfer data between registers in structural RTL (but it's still a form or RTL).