Synthesisable RTL

Abstract syntax for a synthesisable RTL (Verilog/VHDL) without provision for delays:

Expressions:

datatype ex_t =                         // Expressions:
    Num of int                          //  integer constants
  | Net of string                       //  net names
  | Not of ex_t                         //  !x    - logical not
  | Neg of ex_t                         //  ~x    - one's complement
  | Query of ex_t * ex_t * ex_t         //  g?t:f - conditional expression
  | Diadic of diop_t * ex_t * ex_t      //  a+b   - diadic operators + - * / << >>
  | Subscript of ex_t * ex_t            //  a[b]  - array subscription, bit selection.

datatype cmd_t =                       // Commands:
    Assign of ex_t * ex_t              //   a = e;  a[x]=e;  - assignments
  | If1 of ex_t * cmd_t                //   if (e) c;        - one-handed IF
  | If2 of ex_t * cmd_t * cmd_t        //   if (e) c; else c - two-handed IF
  | Block of cmd_t list                //   begin c; c; .. end - block

datatype s_t =                         // Top-level forms:
   Sequential of edge_t * ex_t * cmd_t //    always @(posedge e) c;
|  Combinational of ex_t * ex_t        //    assign e1 = e2;