2b/3: Pure RTL : unordered register transfers.

    module CTR16(ck, din, o);
 
      input ck, din;
      output o;
 
      reg [3:0] count, oldcount;
 
      // Add a four bit decimal value of one to count
      always @(posedge ck) begin
          count <= count + 1;
          if (din) oldcount <= count;
          end

     // Note ^ is exclusive-or operator
     assign o = count[3] ^ count[1];

   endmodule

Registers are assigned in clock domains (one shown).

If we do not assign a register, it retains its old value. In other words, the behavioural 'if' statement is converted to the following pure RTL form that clearly uses a multiplexor.

   oldcount <= (din) ? count : oldcount;

Order of pure RTL assignments does not matter.

Note: combinational logic (continuous assign) has no clock domain.