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NEXT (Basic Bus: One initiator.)
SoC DRAM and Bus/NoC Structures.
The delay and power problem, physical parameters:
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Speed of light on silicon and on a PCB is 200 metres per microsecond.
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A clock frequency of 2 GHz has a wavelength of 2E8/2E9 = 10 cm.
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Synchronous digital clock domain requires connections to be less
than (say) 1/10th of a wavelength.
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RC time constants must also be overcome, so need to register a signal
in several D-types if it passes from one corner of an 8mm chip to the other!
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DRAM is several centimeters away from the SoC and has significant internal delay.
Need to use protocols that are tolerant to registers (4P H/S degrades with reciprocal of delay).
But first let's revist the simple hwen/rwen system used in the 'socparts' section.