FINAL VERSION.

ACS SOC D/M P35: Assessed Essay II

Title:  System On Chip Design and Modelling (40 Credits).

The deadline for Research Essay II is first day of Easter Term (Tues 20th April).


Part A: (Mini-project II): Give an overview of a multi-core system on
chip architecture that you have implemented and tested using
SystemC TLM modelling or another ESL methodology.  Use up to 500 words
and an appropriate number of diagrams. Demonstrate that it worked.

Please refer to part A as a source of examples for part B.

Part B: (Assessed Essay II) Write an essay entitled 'System On Chip
Design and Modelling' that consists of six sections whose headings are
taken from the list below.  Each section should consist of 300 to 600 words
of text and an appropriate number of diagrams.

Section headings (choose six and place in the best order):

1. Relative roles of ISS and cycle-callable models of processor cores
and cache systems. 

    Discuss various abstraction levels for modelling of processor cores, including
    cross compilation of firmware for the modelling workstation through
    to cycle-accurate models of every target instruction.  Mention styles
    for modelling caches (e.g. is the hit ratio estimated or measured ?).

2. Use of assertions and temporal logic in SoC modelling.

    Using  several example assertions that are potentially relevant at several 
    levels of abstraction, explain how they are re-applied at each
    level or mention whether this is not always the case.


3. Ease of design re-partition and architectural exploration.

   Show how a target application can be 'run' (i.e. explored) on SoC models
   that vary in their level of abstraction and show how having a
   lower-level model makes architectural changes, such as changing the number
   of processors, memories or bus/network-on-chip structures more difficult.


4. Statistics collection and modelling contention and queueing.

   Show how performance can be estimated or measured using SoC
   models at various levels of abstraction according to how many
   of the contended resources, such as memory ports or bus bridges
   are actually modelled.

5. Using direct calls between device drivers compared with abstract
and concrete bus/NoC models.

   Explain how firmware and high-level models of devices should
   be modified to run an application without any hardware model
   (i.e. with direct calls between h/w and s/w components) compared 
   with its final form. Include interrupt service routines.

6. Clock frequency and power consumption modelling.

   Discuss how well a high-level SoC model can be used to
   estimate system clock frequency (i.e. critical path) and
   power consumption (including dynamic frequency and voltage 
   scaling) compared with pre-synthesis, post-synthesis and 
   post-layout RTL models.

7. The role of high-level synthesis and synthesis from formal
specifications in SoC design flow.

   Show how part of your example design could have looked
   if synthesised from a higher-level form. (You may have included
   this anyway.)

8. Manual versus automatic generation of glue logic and/or SoC bus/NoC
structures.

   Explain how the components of your example design are
   connected to each other at the various levels of abstraction
   and perhaps discuss the potential for automatic generation of 
   address maps and automatic synthesis of the joining code or logic.


9. A similar topic of your own choosing.



By 'various levels of abstraction' we refer to ESL models spanning:

  1. Application software and device drivers with no hardware model at all,
  2. High-level TLM modelling, loosely timed, with no models of bus or 
network structures,
  3. Lower-level TLM modelling that accurately models contention points,
  4. Cycle-accurate modelling.


Credit Matrix

Up to 10 credits will be awarded for Part A. These marks will be
awarded on the basis of the clarity of the write up and understanding
of the ESL methodology.  Credit will not be awarded for implementing
an overly large or complex system.

For each of the six sections in the assessed essay, up to 5 credit
points will be awarded.

Total available credit: 40 points.

END


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Questions Arising

> Part A: says "Give an overview of a multi-core system on chip architecture
> that you have implemented and tested". Does that refer to ORP 1K ICC we have
> done for ticks 5 and 6, or do we have to design something new?

It can be the same as or based on the tick 5/6 work. However, you
might extend the tick work in minor ways to demonstrate
additional points.

END.