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RTL Summary View of Variant Forms.

Verilog RTL has a synthesisable subset that can be turned into circuits.

Synthesisable Verilog uses one of the following forms and these may be mixed within one module:

The 2a and 2b forms are the 'pure RTL' forms. The order of statements is unimportant (the program counter disappears at compile time).

(C) 2008-10, DJ Greaves, University of Cambridge, Computer Laboratory.