TLM Modelling: Adding The Timing Annotations

The naive way to add approximate timing annotations is to block the SystemC kernel until the required time has elapsed.

   sc_time clock_period  = sc_time(5, SC_NS);  // 200 MHz clock

   int read(A)
   { 
     int r = 0;
     if (A < 0 or A >= SIZE) error(....);
     else r = MEM[A];
     wait(clock_period * 3);   // <-- Directly model memory access time: three cycles say.
     return r;
   }

We can also measure resource utilisation in this way:

  write(A, D)
  {
     if (A > LIM) port1.write(A-LIM, D) else port0.write(A, D)
     opcount += 1;
     if (opcount == 100)
     {
        sc_time delta = sc_time_stamp() - last_measure_time;
        logging.log(100, delta);
        last_measure_time = sc_time_stamp();
        opcount = 0;
     }
  }

In the above, we assume logging.log knows how many bus cycles per unit time can be handled and hence can compute and record the utlisation.