ESL Electronic System Level Modelling

Aims: 1. To Model whole SoC using real firmware and high-level behavioural models.

Aims: 2. To allow seamless and successive replacement of model parts with low-level models/implementations when available and when interested in detail.

Provides:

• Tangible, lightweight prototype of full SoC architecture.

• Rapid Architectural Evaluation: determine bus bandwidth and memory use for a candidate architecture.

• Algorithmic Accuracy: Get real output from an early system, hosting the real application/firmware, possibly in real-time.

• Timing information: Get timing numbers for performance (accurate or loose timing).

• Firmware development: Integrate high-level behavioural models of major components with their device drivers.

Future topic: Embed assertions in the high-level models and use these assertions through to tape out (ABD).

Future world: Behavioural models synthesised to actual system.