SoC D/M Proficiency Tick 2: 5 marks.  SystemC/RTL.

Repeat tick 1. If you used SystemC before, do not use it again.  If you did not
use SystemC before, use it this time.


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Questions arising:

> 1. Is there any tool available that we can use to check if a systemC module is synthesisable?

I do not know of one on the system, but do look in /usr/groups/ecad and use
whatever you can find there. 

You can manually check your design in the OSCI SystemC synthesis draft standard:
http://www.cl.cam.ac.uk/teaching/0910/P35/whitepapers/systemc-synthsubset-1.3.pdf

or you can look at the publications from SystemCrafter.com, 


or from Catapult C (from Mentor)


or from Synopsys
http://www.ece.uah.edu/~milenka/cpe626-04F/secure/systemc/cocentric_systemC/tutorial/tutorial.html

or you can try your code out online 
http://system-synthesis.org/fossy/submit

There are one or two other sites that enable you to try out a small design on
line: I'll put their links here as I confirm them.

>2. Do the “rules” that define a pure RTL design which are included in
> the slides concerning Verilog also apply to SystemC?  For example
> for a pure RTL design in SystemC we need to replace if statements
> with (a) ? (b) : (c) statements?

Yes, that's right, it's the same idea.  A 'pure RTL' module in SystemC
would use the sc_signal type for all local variables and assign to
them all exactly once in the unordered body of an SC_METHOD that was
sensitive to clock pos edge.