Chapter 3 The Hardware Interface, I/O and communications
Exercises
3-1 By looking in Hennessy and Patterson (1990), for example, find out the following:
The execution times of typical instructions of CISC computers such as the VAX series, the IBM System 370, the Motorola 68000 series, the Intel 8086, and 80x86 series.
The execution times of typical instructions of RISC computers such as the Motorola 88000, the SPARC, the MIPS R3000 and the Intel 860.
In both cases note the instruction lengths and their functionality.
Now find out the rate at which networks and peripherals, such as terminals, printers, disks and RAM used as disks can accept or deliver data and also the unit of data that is accepted or delivered.
I leave the details for local research. The instruction execution times will be given as "number of clock cycles" and can be compared on this basis. A given architecture may be fabricated with different technology. Note that a number of RISC instructions are often needed to perform the same task as some CISC instructions.
3-2 What are the advantages and disadvantages of handling devices by a polling scheme compared with an interrupt driven approach? In what kinds of system does the application dictate which approach must be taken?
Polling is simple but the timing is not controllable at a fine grain. You look at a device when you get around to it and not as soon as it needs attention.
Interrupt driven software is more difficult to program but you have the information that a device needs attention and can respond.
In real-time systems you need to know immediately events such as alarms occur. It may be that your schedule allows you to poll for periodic events.
Multi-user systems where terminal lines may lie idle for long periods. That is, the devices that are active vary dynamically. Also, it is wasteful to poll while a user at an active terminal sits and thinks. A reasonable response to all users is a requirement.
3-3 How many memory accesses are made during the hardware exception handling mechanisms described in Sections 3.2 and 3.5? Estimate the total time to achieve the transfer of control from the interrupted program to the exception handling routine in both cases.
Memory accesses for the CISC based exception handling example: 3 The PC and Processor Status Register are written onto a stack in memory. The address of the ISR is read from a table in memory into the PC.
Memory accesses for the RISC based exception handling example: None
3-4 You have hardware support for seven priority interrupt levels. On what basis would you assign these priorities?
It depends on the application area of the system and whether the priority assignment is static or dynamic. For a general purpose multi-user system consider whether devices are dedicated to individual users or shared. The latter should be given priority over the former.
Consider the throughput of the device. It is desirable to keep the disks busy. Especially so in file servers.
There are trade-offs in network handling. It may be possible for very high speed networks to deliver more data than a system can cope with, causing other tasks to run too slowly.
The clock need not have very high priority. It "ticks" relatively slowly compared with instruction execution time.
3-5 What is direct memory access (DMA)? How can a) a single block b) several blocks of data be transferred between main memory and a disk or network?
The processor initiates a DMA transfer but can execute unrelated instructions in parallel with it. An interrupt indicates the end of the transfer.
To initiate a DMA transfer, the disk address, memory address and amount to transfer are passed to the disk controller. It is then instructed to start the (read or write) transfer. This procedure copes with a single block or a number of contiguous blocks on the same track. Some disk interfaces (scatter/gather) are able to transfer to or from a number of non-contiguous blocks in memory to a contiguous area of disk.
3-6 Processors are usually designed to execute in one of two (or more) privilege states, for example, user and supervisor mode. When and how is the state change from user to supervisor mode made?
As part of exception processing.
When and how is the state change from supervisor to user mode made?
By using a special operation which is able to change the processor status as well as transfer control.
Which instructions would you expect to be privileged (executable only in supervisor mode)? What is the mechanism for preventing them from being executed in user mode?
Halt the processor, change memory management hardware, enable or disable interrupts, change the processor status, handle devices directly and so on.
A flag in the processor status indicates user or supervisor mode.
Privileged instructions executed in user mode cause an exception.
3-7 An application should be able to send an arbitrary amount of data to be output to a device. Devices transfer a fixed amount. How is this achieved?
Through the use of buffers. See Chapter 10 and exercise 5.
3-8 Error conditions are often detected at a low level in a system, such as in an exception handling routine. Why should they not be dealt with immediately? Devise a method to allow error handling at user level within the context of the application that caused the error.
Error handling at a low level is overhead on every process in the system. Errors should be handled in the time allocated to the process causing the error.
General purpose exception handling routines can be provided in libraries. Users may be able to supply special purpose ones. The low level error detection mechanism may set a flag (in the process descriptor-see Chapter 6) to indicate that on return to user level exception processing should be carried out instead of a continuation of normal processing.
3-9 How are exceptions handled in a shared memory multiprocessor?
The issue here is which processor should handle a given interrupt or exception. See Section 3.4.
3-10 Compare and contrast peripheral I/O and network I/O.
Network I/O is comparable with device I/O for shared devices.
Network and device interfaces are similar in function. Both may or may not use DMA.
In the case of shared devices, a single operating system controls all interactions with devices, even though data transfers may complete asynchronously. In the case of network I/O an independent computer system may initiate communication with you.
3-11 Define wide area networks and local area networks (see also Section 1.3.8).
The technical differences are becoming less clear as WANs increase in speed and LANs increase in complexity. A LAN may comprise different types of network, for example rings and Ethernet, perhaps connected by a high speed backbone network. Because of the smaller scale and high reliability, functions such as routing, flow control, error control and congestion control may be less complex in LANs than in WANs.
LANs are owned by a private organisation, WANs require PTT co-operation.
3-12 Compare and contrast the Ethernet with a ring-based LAN. Which design type will guarantee bandwidth between connected systems? What kind of applications need such guarantees? Are the guarantees usually made to the application level?
The Ethernet is probabilistic and guarantees of point to point bandwidth cannot be made. Guarantees can be made for some ring-based systems (e.g. those which employ ATM techniques). For example, the Cambridge Ring has an anti-hogging protocol so that a station must pass control on after sending a packet. Token rings may control the maximum amount that can be transmitted before passing on the token.
3-13 What is meant by connectionless and connection oriented communication?
Connection oriented communication has a separate phase for connection set up. This is usually an end-to-end procedure which imposes disproportionate overhead if only a small amount of data is to be transferred. After set-up the connection has a short identifier (compared with the name and address of the final recipient) and decoding and routing overhead is minimised. Resources may be allocated to the connection such as buffer space en-route. It is suitable for the transfer of a large amount of data and where a stream mode of communication is required. Connectionless communication allows a packet of information (a datagram) to be sent to a specified recipient without prior notification. The communication may be unreliable (unacknowledged) or reliable (acknowledged).
A given protocol hierarchy is likely to offer both styles of communication (e.g. UDP and TCP)
3-14 Which of the ISO layers would you expect to be implemented inside an operating system?
The traditional approach is to offer a transport service in the OS and a session service at the interface. Presentation issues are specific to the application.
Microkernel designs have experimented with implementing various functions outside for generality and inside for speed.
3-15 How do you think the ISO layers might be implemented in terms of the modules and processes introduced in Chapter 2? Try this question again after reading Chapter 4.
It appears that each layer has to be prepared to respond to service calls from above, to respond to unsolicited calls from below and to wait for responses to previous requests. At this stage it seems that we need several processes per layer.
After reading Chapter 4 it seems that several processes per layer would involve a large amount of context switching overhead which is highly undesirable in this area. After reading later chapters (8, 15) it seems that we should aim to have the communications service multi-threaded and allow a given thread to traverse the layers. We must have the ability to respond to unsolicited events, perhaps have a dedicated, listening thread and either a pool of available workers or dynamic creation of threads.