|N105_system
LCD_EN <= N_105_system:inst.LCD_E_from_the_lcd_16207_0
clk => N_105_system:inst.clk
clk => debouncer:inst1.CLK
SW2 => debouncer:inst1.SWITCH
LCD_D[0] <= N_105_system:inst.LCD_data_to_and_from_the_lcd_16207_0[0]
LCD_D[1] <= N_105_system:inst.LCD_data_to_and_from_the_lcd_16207_0[1]
LCD_D[2] <= N_105_system:inst.LCD_data_to_and_from_the_lcd_16207_0[2]
LCD_D[3] <= N_105_system:inst.LCD_data_to_and_from_the_lcd_16207_0[3]
LCD_D[4] <= N_105_system:inst.LCD_data_to_and_from_the_lcd_16207_0[4]
LCD_D[5] <= N_105_system:inst.LCD_data_to_and_from_the_lcd_16207_0[5]
LCD_D[6] <= N_105_system:inst.LCD_data_to_and_from_the_lcd_16207_0[6]
LCD_D[7] <= N_105_system:inst.LCD_data_to_and_from_the_lcd_16207_0[7]
LCD_RS <= N_105_system:inst.LCD_RS_from_the_lcd_16207_0
LCD_RW <= N_105_system:inst.LCD_RW_from_the_lcd_16207_0


|N105_system|N_105_system:inst
clk => clk~0.IN6
reset_n => d1_reset_n_sources.DATAIN
LCD_E_from_the_lcd_16207_0 <= lcd_16207_0:the_lcd_16207_0.LCD_E
LCD_RS_from_the_lcd_16207_0 <= lcd_16207_0:the_lcd_16207_0.LCD_RS
LCD_RW_from_the_lcd_16207_0 <= lcd_16207_0:the_lcd_16207_0.LCD_RW
LCD_data_to_and_from_the_lcd_16207_0[0] <= lcd_16207_0:the_lcd_16207_0.LCD_data
LCD_data_to_and_from_the_lcd_16207_0[1] <= lcd_16207_0:the_lcd_16207_0.LCD_data
LCD_data_to_and_from_the_lcd_16207_0[2] <= lcd_16207_0:the_lcd_16207_0.LCD_data
LCD_data_to_and_from_the_lcd_16207_0[3] <= lcd_16207_0:the_lcd_16207_0.LCD_data
LCD_data_to_and_from_the_lcd_16207_0[4] <= lcd_16207_0:the_lcd_16207_0.LCD_data
LCD_data_to_and_from_the_lcd_16207_0[5] <= lcd_16207_0:the_lcd_16207_0.LCD_data
LCD_data_to_and_from_the_lcd_16207_0[6] <= lcd_16207_0:the_lcd_16207_0.LCD_data
LCD_data_to_and_from_the_lcd_16207_0[7] <= lcd_16207_0:the_lcd_16207_0.LCD_data


|N105_system|N_105_system:inst|lcd_16207_0_control_slave_arbitrator:the_lcd_16207_0_control_slave
clk => d1_lcd_16207_0_control_slave_end_xfer~reg0.CLK
clk => lcd_16207_0_control_slave_wait_counter[5].CLK
clk => lcd_16207_0_control_slave_wait_counter[4].CLK
clk => lcd_16207_0_control_slave_wait_counter[3].CLK
clk => lcd_16207_0_control_slave_wait_counter[2].CLK
clk => lcd_16207_0_control_slave_wait_counter[1].CLK
clk => lcd_16207_0_control_slave_wait_counter[0].CLK
clk => d1_reasons_to_wait.CLK
d2_reset_n => lcd_16207_0_control_slave_wait_counter[4].ACLR
d2_reset_n => lcd_16207_0_control_slave_wait_counter[3].ACLR
d2_reset_n => lcd_16207_0_control_slave_wait_counter[2].ACLR
d2_reset_n => lcd_16207_0_control_slave_wait_counter[1].ACLR
d2_reset_n => lcd_16207_0_control_slave_wait_counter[0].ACLR
d2_reset_n => d1_reasons_to_wait.ACLR
d2_reset_n => d1_lcd_16207_0_control_slave_end_xfer~reg0.PRESET
d2_reset_n => lcd_16207_0_control_slave_wait_counter[5].ACLR
lcd_16207_0_control_slave_readdata[0] => lcd_16207_0_control_slave_readdata_from_sa[0].DATAIN
lcd_16207_0_control_slave_readdata[1] => lcd_16207_0_control_slave_readdata_from_sa[1].DATAIN
lcd_16207_0_control_slave_readdata[2] => lcd_16207_0_control_slave_readdata_from_sa[2].DATAIN
lcd_16207_0_control_slave_readdata[3] => lcd_16207_0_control_slave_readdata_from_sa[3].DATAIN
lcd_16207_0_control_slave_readdata[4] => lcd_16207_0_control_slave_readdata_from_sa[4].DATAIN
lcd_16207_0_control_slave_readdata[5] => lcd_16207_0_control_slave_readdata_from_sa[5].DATAIN
lcd_16207_0_control_slave_readdata[6] => lcd_16207_0_control_slave_readdata_from_sa[6].DATAIN
lcd_16207_0_control_slave_readdata[7] => lcd_16207_0_control_slave_readdata_from_sa[7].DATAIN
uoccl_n105_0_data_master_address_to_slave[1] => lcd_16207_0_control_slave_address[0].DATAIN
uoccl_n105_0_data_master_address_to_slave[2] => lcd_16207_0_control_slave_address[1].DATAIN
uoccl_n105_0_data_master_address_to_slave[3] => i~0.IN11
uoccl_n105_0_data_master_address_to_slave[4] => i~0.IN10
uoccl_n105_0_data_master_address_to_slave[5] => i~0.IN9
uoccl_n105_0_data_master_address_to_slave[6] => i~0.IN8
uoccl_n105_0_data_master_address_to_slave[7] => i~0.IN7
uoccl_n105_0_data_master_address_to_slave[8] => i~0.IN6
uoccl_n105_0_data_master_address_to_slave[9] => i~0.IN5
uoccl_n105_0_data_master_address_to_slave[10] => i~0.IN4
uoccl_n105_0_data_master_address_to_slave[11] => i~0.IN3
uoccl_n105_0_data_master_address_to_slave[12] => i~0.IN2
uoccl_n105_0_data_master_address_to_slave[13] => i~0.IN1
uoccl_n105_0_data_master_address_to_slave[14] => i~0.IN0
uoccl_n105_0_data_master_address_to_slave[15] => i~0.IN12
uoccl_n105_0_data_master_byteenable[0] => i227.DATAB
uoccl_n105_0_data_master_read => i12.IN0
uoccl_n105_0_data_master_read => i54.IN0
uoccl_n105_0_data_master_write => i12.IN1
uoccl_n105_0_data_master_write => i57.IN0
uoccl_n105_0_data_master_writedata[0] => lcd_16207_0_control_slave_writedata[0].DATAIN
uoccl_n105_0_data_master_writedata[1] => lcd_16207_0_control_slave_writedata[1].DATAIN
uoccl_n105_0_data_master_writedata[2] => lcd_16207_0_control_slave_writedata[2].DATAIN
uoccl_n105_0_data_master_writedata[3] => lcd_16207_0_control_slave_writedata[3].DATAIN
uoccl_n105_0_data_master_writedata[4] => lcd_16207_0_control_slave_writedata[4].DATAIN
uoccl_n105_0_data_master_writedata[5] => lcd_16207_0_control_slave_writedata[5].DATAIN
uoccl_n105_0_data_master_writedata[6] => lcd_16207_0_control_slave_writedata[6].DATAIN
uoccl_n105_0_data_master_writedata[7] => lcd_16207_0_control_slave_writedata[7].DATAIN
d1_lcd_16207_0_control_slave_end_xfer <= d1_lcd_16207_0_control_slave_end_xfer~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_address[0] <= uoccl_n105_0_data_master_address_to_slave[1].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_address[1] <= uoccl_n105_0_data_master_address_to_slave[2].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_begintransfer <= i9.DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_read <= i41.DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_readdata_from_sa[0] <= lcd_16207_0_control_slave_readdata[0].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_readdata_from_sa[1] <= lcd_16207_0_control_slave_readdata[1].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_readdata_from_sa[2] <= lcd_16207_0_control_slave_readdata[2].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_readdata_from_sa[3] <= lcd_16207_0_control_slave_readdata[3].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_readdata_from_sa[4] <= lcd_16207_0_control_slave_readdata[4].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_readdata_from_sa[5] <= lcd_16207_0_control_slave_readdata[5].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_readdata_from_sa[6] <= lcd_16207_0_control_slave_readdata[6].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_readdata_from_sa[7] <= lcd_16207_0_control_slave_readdata[7].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_wait_counter_eq_0 <= i~4.DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_write <= i49.DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_writedata[0] <= uoccl_n105_0_data_master_writedata[0].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_writedata[1] <= uoccl_n105_0_data_master_writedata[1].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_writedata[2] <= uoccl_n105_0_data_master_writedata[2].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_writedata[3] <= uoccl_n105_0_data_master_writedata[3].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_writedata[4] <= uoccl_n105_0_data_master_writedata[4].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_writedata[5] <= uoccl_n105_0_data_master_writedata[5].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_writedata[6] <= uoccl_n105_0_data_master_writedata[6].DB_MAX_OUTPUT_PORT_TYPE
lcd_16207_0_control_slave_writedata[7] <= uoccl_n105_0_data_master_writedata[7].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_granted_lcd_16207_0_control_slave <= i13.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_qualified_request_lcd_16207_0_control_slave <= i13.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave <= i13.DB_MAX_OUTPUT_PORT_TYPE


|N105_system|N_105_system:inst|lcd_16207_0:the_lcd_16207_0
address[0] => LCD_RW.DATAIN
address[0] => i16.OE
address[0] => i18.OE
address[0] => i20.OE
address[0] => i22.OE
address[0] => i24.OE
address[0] => i26.OE
address[0] => i28.OE
address[0] => i30.OE
address[1] => LCD_RS.DATAIN
read => i6.IN0
write => i6.IN1
writedata[0] => i30.DATAIN
writedata[1] => i28.DATAIN
writedata[2] => i26.DATAIN
writedata[3] => i24.DATAIN
writedata[4] => i22.DATAIN
writedata[5] => i20.DATAIN
writedata[6] => i18.DATAIN
writedata[7] => i16.DATAIN
LCD_E <= i6.DB_MAX_OUTPUT_PORT_TYPE
LCD_RS <= address[1].DB_MAX_OUTPUT_PORT_TYPE
LCD_RW <= address[0].DB_MAX_OUTPUT_PORT_TYPE
LCD_data[0] <= i30
LCD_data[1] <= i28
LCD_data[2] <= i26
LCD_data[3] <= i24
LCD_data[4] <= i22
LCD_data[5] <= i20
LCD_data[6] <= i18
LCD_data[7] <= i16
irq <= <GND>
readdata[0] <= LCD_data[0]~7.DB_MAX_OUTPUT_PORT_TYPE
readdata[1] <= LCD_data[1]~6.DB_MAX_OUTPUT_PORT_TYPE
readdata[2] <= LCD_data[2]~5.DB_MAX_OUTPUT_PORT_TYPE
readdata[3] <= LCD_data[3]~4.DB_MAX_OUTPUT_PORT_TYPE
readdata[4] <= LCD_data[4]~3.DB_MAX_OUTPUT_PORT_TYPE
readdata[5] <= LCD_data[5]~2.DB_MAX_OUTPUT_PORT_TYPE
readdata[6] <= LCD_data[6]~1.DB_MAX_OUTPUT_PORT_TYPE
readdata[7] <= LCD_data[7]~0.DB_MAX_OUTPUT_PORT_TYPE


|N105_system|N_105_system:inst|onchip_ram_s1_arbitrator:the_onchip_ram_s1
clk => d1_onchip_ram_s1_end_xfer~reg0.CLK
clk => uoccl_n105_0_data_master_read_data_valid_onchip_ram_s1_shift_register.CLK
d2_reset_n => onchip_ram_s1_reset_n.DATAIN
d2_reset_n => d1_onchip_ram_s1_end_xfer~reg0.PRESET
d2_reset_n => uoccl_n105_0_data_master_read_data_valid_onchip_ram_s1_shift_register.ACLR
onchip_ram_s1_readdata[0] => onchip_ram_s1_readdata_from_sa[0].DATAIN
onchip_ram_s1_readdata[1] => onchip_ram_s1_readdata_from_sa[1].DATAIN
onchip_ram_s1_readdata[2] => onchip_ram_s1_readdata_from_sa[2].DATAIN
onchip_ram_s1_readdata[3] => onchip_ram_s1_readdata_from_sa[3].DATAIN
onchip_ram_s1_readdata[4] => onchip_ram_s1_readdata_from_sa[4].DATAIN
onchip_ram_s1_readdata[5] => onchip_ram_s1_readdata_from_sa[5].DATAIN
onchip_ram_s1_readdata[6] => onchip_ram_s1_readdata_from_sa[6].DATAIN
onchip_ram_s1_readdata[7] => onchip_ram_s1_readdata_from_sa[7].DATAIN
onchip_ram_s1_readdata[8] => onchip_ram_s1_readdata_from_sa[8].DATAIN
onchip_ram_s1_readdata[9] => onchip_ram_s1_readdata_from_sa[9].DATAIN
onchip_ram_s1_readdata[10] => onchip_ram_s1_readdata_from_sa[10].DATAIN
onchip_ram_s1_readdata[11] => onchip_ram_s1_readdata_from_sa[11].DATAIN
onchip_ram_s1_readdata[12] => onchip_ram_s1_readdata_from_sa[12].DATAIN
onchip_ram_s1_readdata[13] => onchip_ram_s1_readdata_from_sa[13].DATAIN
onchip_ram_s1_readdata[14] => onchip_ram_s1_readdata_from_sa[14].DATAIN
onchip_ram_s1_readdata[15] => onchip_ram_s1_readdata_from_sa[15].DATAIN
uoccl_n105_0_data_master_address_to_slave[1] => onchip_ram_s1_address[0].DATAIN
uoccl_n105_0_data_master_address_to_slave[2] => onchip_ram_s1_address[1].DATAIN
uoccl_n105_0_data_master_address_to_slave[3] => onchip_ram_s1_address[2].DATAIN
uoccl_n105_0_data_master_address_to_slave[4] => onchip_ram_s1_address[3].DATAIN
uoccl_n105_0_data_master_address_to_slave[5] => onchip_ram_s1_address[4].DATAIN
uoccl_n105_0_data_master_address_to_slave[6] => onchip_ram_s1_address[5].DATAIN
uoccl_n105_0_data_master_address_to_slave[7] => onchip_ram_s1_address[6].DATAIN
uoccl_n105_0_data_master_address_to_slave[8] => onchip_ram_s1_address[7].DATAIN
uoccl_n105_0_data_master_address_to_slave[9] => onchip_ram_s1_address[8].DATAIN
uoccl_n105_0_data_master_address_to_slave[10] => onchip_ram_s1_address[9].DATAIN
uoccl_n105_0_data_master_address_to_slave[11] => i~0.IN4
uoccl_n105_0_data_master_address_to_slave[12] => i~0.IN3
uoccl_n105_0_data_master_address_to_slave[13] => i~0.IN2
uoccl_n105_0_data_master_address_to_slave[14] => i~0.IN1
uoccl_n105_0_data_master_address_to_slave[15] => i~0.IN0
uoccl_n105_0_data_master_byteenable[0] => i110.DATAB
uoccl_n105_0_data_master_byteenable[1] => i109.DATAB
uoccl_n105_0_data_master_read => i5.IN0
uoccl_n105_0_data_master_read => i23.IN0
uoccl_n105_0_data_master_read => i26.IN0
uoccl_n105_0_data_master_write => i5.IN1
uoccl_n105_0_data_master_write => i63.IN0
uoccl_n105_0_data_master_writedata[0] => onchip_ram_s1_writedata[0].DATAIN
uoccl_n105_0_data_master_writedata[1] => onchip_ram_s1_writedata[1].DATAIN
uoccl_n105_0_data_master_writedata[2] => onchip_ram_s1_writedata[2].DATAIN
uoccl_n105_0_data_master_writedata[3] => onchip_ram_s1_writedata[3].DATAIN
uoccl_n105_0_data_master_writedata[4] => onchip_ram_s1_writedata[4].DATAIN
uoccl_n105_0_data_master_writedata[5] => onchip_ram_s1_writedata[5].DATAIN
uoccl_n105_0_data_master_writedata[6] => onchip_ram_s1_writedata[6].DATAIN
uoccl_n105_0_data_master_writedata[7] => onchip_ram_s1_writedata[7].DATAIN
uoccl_n105_0_data_master_writedata[8] => onchip_ram_s1_writedata[8].DATAIN
uoccl_n105_0_data_master_writedata[9] => onchip_ram_s1_writedata[9].DATAIN
uoccl_n105_0_data_master_writedata[10] => onchip_ram_s1_writedata[10].DATAIN
uoccl_n105_0_data_master_writedata[11] => onchip_ram_s1_writedata[11].DATAIN
uoccl_n105_0_data_master_writedata[12] => onchip_ram_s1_writedata[12].DATAIN
uoccl_n105_0_data_master_writedata[13] => onchip_ram_s1_writedata[13].DATAIN
uoccl_n105_0_data_master_writedata[14] => onchip_ram_s1_writedata[14].DATAIN
uoccl_n105_0_data_master_writedata[15] => onchip_ram_s1_writedata[15].DATAIN
d1_onchip_ram_s1_end_xfer <= d1_onchip_ram_s1_end_xfer~reg0.DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_address[0] <= uoccl_n105_0_data_master_address_to_slave[1].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_address[1] <= uoccl_n105_0_data_master_address_to_slave[2].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_address[2] <= uoccl_n105_0_data_master_address_to_slave[3].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_address[3] <= uoccl_n105_0_data_master_address_to_slave[4].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_address[4] <= uoccl_n105_0_data_master_address_to_slave[5].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_address[5] <= uoccl_n105_0_data_master_address_to_slave[6].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_address[6] <= uoccl_n105_0_data_master_address_to_slave[7].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_address[7] <= uoccl_n105_0_data_master_address_to_slave[8].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_address[8] <= uoccl_n105_0_data_master_address_to_slave[9].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_address[9] <= uoccl_n105_0_data_master_address_to_slave[10].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_readdata_from_sa[0] <= onchip_ram_s1_readdata[0].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_readdata_from_sa[1] <= onchip_ram_s1_readdata[1].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_readdata_from_sa[2] <= onchip_ram_s1_readdata[2].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_readdata_from_sa[3] <= onchip_ram_s1_readdata[3].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_readdata_from_sa[4] <= onchip_ram_s1_readdata[4].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_readdata_from_sa[5] <= onchip_ram_s1_readdata[5].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_readdata_from_sa[6] <= onchip_ram_s1_readdata[6].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_readdata_from_sa[7] <= onchip_ram_s1_readdata[7].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_readdata_from_sa[8] <= onchip_ram_s1_readdata[8].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_readdata_from_sa[9] <= onchip_ram_s1_readdata[9].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_readdata_from_sa[10] <= onchip_ram_s1_readdata[10].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_readdata_from_sa[11] <= onchip_ram_s1_readdata[11].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_readdata_from_sa[12] <= onchip_ram_s1_readdata[12].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_readdata_from_sa[13] <= onchip_ram_s1_readdata[13].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_readdata_from_sa[14] <= onchip_ram_s1_readdata[14].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_readdata_from_sa[15] <= onchip_ram_s1_readdata[15].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_reset_n <= d2_reset_n.DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writebyteenable[0] <= i78.DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writebyteenable[1] <= i77.DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writedata[0] <= uoccl_n105_0_data_master_writedata[0].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writedata[1] <= uoccl_n105_0_data_master_writedata[1].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writedata[2] <= uoccl_n105_0_data_master_writedata[2].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writedata[3] <= uoccl_n105_0_data_master_writedata[3].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writedata[4] <= uoccl_n105_0_data_master_writedata[4].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writedata[5] <= uoccl_n105_0_data_master_writedata[5].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writedata[6] <= uoccl_n105_0_data_master_writedata[6].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writedata[7] <= uoccl_n105_0_data_master_writedata[7].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writedata[8] <= uoccl_n105_0_data_master_writedata[8].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writedata[9] <= uoccl_n105_0_data_master_writedata[9].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writedata[10] <= uoccl_n105_0_data_master_writedata[10].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writedata[11] <= uoccl_n105_0_data_master_writedata[11].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writedata[12] <= uoccl_n105_0_data_master_writedata[12].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writedata[13] <= uoccl_n105_0_data_master_writedata[13].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writedata[14] <= uoccl_n105_0_data_master_writedata[14].DB_MAX_OUTPUT_PORT_TYPE
onchip_ram_s1_writedata[15] <= uoccl_n105_0_data_master_writedata[15].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_granted_onchip_ram_s1 <= i25.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_qualified_request_onchip_ram_s1 <= i25.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_read_data_valid_onchip_ram_s1 <= uoccl_n105_0_data_master_read_data_valid_onchip_ram_s1_shift_register.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_requests_onchip_ram_s1 <= i6.DB_MAX_OUTPUT_PORT_TYPE


|N105_system|N_105_system:inst|onchip_ram:the_onchip_ram
address[0] => onchip_ram_lane0_address[0].IN4
address[1] => onchip_ram_lane0_address[1].IN4
address[2] => onchip_ram_lane0_address[2].IN4
address[3] => onchip_ram_lane0_address[3].IN4
address[4] => onchip_ram_lane0_address[4].IN4
address[5] => onchip_ram_lane0_address[5].IN4
address[6] => onchip_ram_lane0_address[6].IN4
address[7] => onchip_ram_lane0_address[7].IN4
address[8] => onchip_ram_lane0_address[8].IN4
address[9] => onchip_ram_lane0_address[9].IN4
clk => clk~0.IN4
reset_n => reset_n~0.IN2
writebyteenable[0] => write_lane_0.IN1
writebyteenable[1] => write_lane_1.IN1
writedata[0] => d_lane_0[0].IN1
writedata[1] => d_lane_0[1].IN1
writedata[2] => d_lane_0[2].IN1
writedata[3] => d_lane_0[3].IN1
writedata[4] => d_lane_0[4].IN1
writedata[5] => d_lane_0[5].IN1
writedata[6] => d_lane_0[6].IN1
writedata[7] => d_lane_0[7].IN1
writedata[8] => d_lane_1[0].IN1
writedata[9] => d_lane_1[1].IN1
writedata[10] => d_lane_1[2].IN1
writedata[11] => d_lane_1[3].IN1
writedata[12] => d_lane_1[4].IN1
writedata[13] => d_lane_1[5].IN1
writedata[14] => d_lane_1[6].IN1
writedata[15] => d_lane_1[7].IN1
readdata[0] <= onchip_ram_lane0_module:onchip_ram_lane0.q
readdata[1] <= onchip_ram_lane0_module:onchip_ram_lane0.q
readdata[2] <= onchip_ram_lane0_module:onchip_ram_lane0.q
readdata[3] <= onchip_ram_lane0_module:onchip_ram_lane0.q
readdata[4] <= onchip_ram_lane0_module:onchip_ram_lane0.q
readdata[5] <= onchip_ram_lane0_module:onchip_ram_lane0.q
readdata[6] <= onchip_ram_lane0_module:onchip_ram_lane0.q
readdata[7] <= onchip_ram_lane0_module:onchip_ram_lane0.q
readdata[8] <= onchip_ram_lane1_module:onchip_ram_lane1.q
readdata[9] <= onchip_ram_lane1_module:onchip_ram_lane1.q
readdata[10] <= onchip_ram_lane1_module:onchip_ram_lane1.q
readdata[11] <= onchip_ram_lane1_module:onchip_ram_lane1.q
readdata[12] <= onchip_ram_lane1_module:onchip_ram_lane1.q
readdata[13] <= onchip_ram_lane1_module:onchip_ram_lane1.q
readdata[14] <= onchip_ram_lane1_module:onchip_ram_lane1.q
readdata[15] <= onchip_ram_lane1_module:onchip_ram_lane1.q


|N105_system|N_105_system:inst|onchip_ram:the_onchip_ram|onchip_ram_lane1_module:onchip_ram_lane1
clk => clk~0.IN1
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
rdaddress[0] => read_address[0].IN1
rdaddress[1] => read_address[1].IN1
rdaddress[2] => read_address[2].IN1
rdaddress[3] => read_address[3].IN1
rdaddress[4] => read_address[4].IN1
rdaddress[5] => read_address[5].IN1
rdaddress[6] => read_address[6].IN1
rdaddress[7] => read_address[7].IN1
rdaddress[8] => read_address[8].IN1
rdaddress[9] => read_address[9].IN1
rdclken => rdclken~0.IN1
wraddress[0] => wraddress[0]~9.IN1
wraddress[1] => wraddress[1]~8.IN1
wraddress[2] => wraddress[2]~7.IN1
wraddress[3] => wraddress[3]~6.IN1
wraddress[4] => wraddress[4]~5.IN1
wraddress[5] => wraddress[5]~4.IN1
wraddress[6] => wraddress[6]~3.IN1
wraddress[7] => wraddress[7]~2.IN1
wraddress[8] => wraddress[8]~1.IN1
wraddress[9] => wraddress[9]~0.IN1
wrclock => wrclock~0.IN1
wren => wren~0.IN1
q[0] <= lpm_ram_dp:lpm_ram_dp_component.q
q[1] <= lpm_ram_dp:lpm_ram_dp_component.q
q[2] <= lpm_ram_dp:lpm_ram_dp_component.q
q[3] <= lpm_ram_dp:lpm_ram_dp_component.q
q[4] <= lpm_ram_dp:lpm_ram_dp_component.q
q[5] <= lpm_ram_dp:lpm_ram_dp_component.q
q[6] <= lpm_ram_dp:lpm_ram_dp_component.q
q[7] <= lpm_ram_dp:lpm_ram_dp_component.q


|N105_system|N_105_system:inst|onchip_ram:the_onchip_ram|onchip_ram_lane1_module:onchip_ram_lane1|lpm_ram_dp:lpm_ram_dp_component
data[0] => altdpram:sram.data[0]
data[1] => altdpram:sram.data[1]
data[2] => altdpram:sram.data[2]
data[3] => altdpram:sram.data[3]
data[4] => altdpram:sram.data[4]
data[5] => altdpram:sram.data[5]
data[6] => altdpram:sram.data[6]
data[7] => altdpram:sram.data[7]
rdaddress[0] => altdpram:sram.rdaddress[0]
rdaddress[1] => altdpram:sram.rdaddress[1]
rdaddress[2] => altdpram:sram.rdaddress[2]
rdaddress[3] => altdpram:sram.rdaddress[3]
rdaddress[4] => altdpram:sram.rdaddress[4]
rdaddress[5] => altdpram:sram.rdaddress[5]
rdaddress[6] => altdpram:sram.rdaddress[6]
rdaddress[7] => altdpram:sram.rdaddress[7]
rdaddress[8] => altdpram:sram.rdaddress[8]
rdaddress[9] => altdpram:sram.rdaddress[9]
wraddress[0] => altdpram:sram.wraddress[0]
wraddress[1] => altdpram:sram.wraddress[1]
wraddress[2] => altdpram:sram.wraddress[2]
wraddress[3] => altdpram:sram.wraddress[3]
wraddress[4] => altdpram:sram.wraddress[4]
wraddress[5] => altdpram:sram.wraddress[5]
wraddress[6] => altdpram:sram.wraddress[6]
wraddress[7] => altdpram:sram.wraddress[7]
wraddress[8] => altdpram:sram.wraddress[8]
wraddress[9] => altdpram:sram.wraddress[9]
rdclock => altdpram:sram.outclock
rdclken => altdpram:sram.outclocken
wrclock => altdpram:sram.inclock
wren => altdpram:sram.wren
q[0] <= altdpram:sram.q[0]
q[1] <= altdpram:sram.q[1]
q[2] <= altdpram:sram.q[2]
q[3] <= altdpram:sram.q[3]
q[4] <= altdpram:sram.q[4]
q[5] <= altdpram:sram.q[5]
q[6] <= altdpram:sram.q[6]
q[7] <= altdpram:sram.q[7]


|N105_system|N_105_system:inst|onchip_ram:the_onchip_ram|onchip_ram_lane1_module:onchip_ram_lane1|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram
wren => segment[0][7].WE
wren => segment[0][6].WE
wren => segment[0][5].WE
wren => segment[0][4].WE
wren => segment[0][3].WE
wren => segment[0][2].WE
wren => segment[0][1].WE
wren => segment[0][0].WE
data[0] => segment[0][0].DATAIN
data[1] => segment[0][1].DATAIN
data[2] => segment[0][2].DATAIN
data[3] => segment[0][3].DATAIN
data[4] => segment[0][4].DATAIN
data[5] => segment[0][5].DATAIN
data[6] => segment[0][6].DATAIN
data[7] => segment[0][7].DATAIN
wraddress[0] => segment[0][7].WADDR
wraddress[0] => segment[0][6].WADDR
wraddress[0] => segment[0][5].WADDR
wraddress[0] => segment[0][4].WADDR
wraddress[0] => segment[0][3].WADDR
wraddress[0] => segment[0][2].WADDR
wraddress[0] => segment[0][1].WADDR
wraddress[0] => segment[0][0].WADDR
wraddress[1] => segment[0][7].WADDR1
wraddress[1] => segment[0][6].WADDR1
wraddress[1] => segment[0][5].WADDR1
wraddress[1] => segment[0][4].WADDR1
wraddress[1] => segment[0][3].WADDR1
wraddress[1] => segment[0][2].WADDR1
wraddress[1] => segment[0][1].WADDR1
wraddress[1] => segment[0][0].WADDR1
wraddress[2] => segment[0][7].WADDR2
wraddress[2] => segment[0][6].WADDR2
wraddress[2] => segment[0][5].WADDR2
wraddress[2] => segment[0][4].WADDR2
wraddress[2] => segment[0][3].WADDR2
wraddress[2] => segment[0][2].WADDR2
wraddress[2] => segment[0][1].WADDR2
wraddress[2] => segment[0][0].WADDR2
wraddress[3] => segment[0][7].WADDR3
wraddress[3] => segment[0][6].WADDR3
wraddress[3] => segment[0][5].WADDR3
wraddress[3] => segment[0][4].WADDR3
wraddress[3] => segment[0][3].WADDR3
wraddress[3] => segment[0][2].WADDR3
wraddress[3] => segment[0][1].WADDR3
wraddress[3] => segment[0][0].WADDR3
wraddress[4] => segment[0][7].WADDR4
wraddress[4] => segment[0][6].WADDR4
wraddress[4] => segment[0][5].WADDR4
wraddress[4] => segment[0][4].WADDR4
wraddress[4] => segment[0][3].WADDR4
wraddress[4] => segment[0][2].WADDR4
wraddress[4] => segment[0][1].WADDR4
wraddress[4] => segment[0][0].WADDR4
wraddress[5] => segment[0][7].WADDR5
wraddress[5] => segment[0][6].WADDR5
wraddress[5] => segment[0][5].WADDR5
wraddress[5] => segment[0][4].WADDR5
wraddress[5] => segment[0][3].WADDR5
wraddress[5] => segment[0][2].WADDR5
wraddress[5] => segment[0][1].WADDR5
wraddress[5] => segment[0][0].WADDR5
wraddress[6] => segment[0][7].WADDR6
wraddress[6] => segment[0][6].WADDR6
wraddress[6] => segment[0][5].WADDR6
wraddress[6] => segment[0][4].WADDR6
wraddress[6] => segment[0][3].WADDR6
wraddress[6] => segment[0][2].WADDR6
wraddress[6] => segment[0][1].WADDR6
wraddress[6] => segment[0][0].WADDR6
wraddress[7] => segment[0][7].WADDR7
wraddress[7] => segment[0][6].WADDR7
wraddress[7] => segment[0][5].WADDR7
wraddress[7] => segment[0][4].WADDR7
wraddress[7] => segment[0][3].WADDR7
wraddress[7] => segment[0][2].WADDR7
wraddress[7] => segment[0][1].WADDR7
wraddress[7] => segment[0][0].WADDR7
wraddress[8] => segment[0][7].WADDR8
wraddress[8] => segment[0][6].WADDR8
wraddress[8] => segment[0][5].WADDR8
wraddress[8] => segment[0][4].WADDR8
wraddress[8] => segment[0][3].WADDR8
wraddress[8] => segment[0][2].WADDR8
wraddress[8] => segment[0][1].WADDR8
wraddress[8] => segment[0][0].WADDR8
wraddress[9] => segment[0][7].WADDR9
wraddress[9] => segment[0][6].WADDR9
wraddress[9] => segment[0][5].WADDR9
wraddress[9] => segment[0][4].WADDR9
wraddress[9] => segment[0][3].WADDR9
wraddress[9] => segment[0][2].WADDR9
wraddress[9] => segment[0][1].WADDR9
wraddress[9] => segment[0][0].WADDR9
inclock => segment[0][7].CLK0
inclock => segment[0][6].CLK0
inclock => segment[0][5].CLK0
inclock => segment[0][4].CLK0
inclock => segment[0][3].CLK0
inclock => segment[0][2].CLK0
inclock => segment[0][1].CLK0
inclock => segment[0][0].CLK0
rden => segment[0][7].RE
rden => segment[0][6].RE
rden => segment[0][5].RE
rden => segment[0][4].RE
rden => segment[0][3].RE
rden => segment[0][2].RE
rden => segment[0][1].RE
rden => segment[0][0].RE
rdaddress[0] => segment[0][7].RADDR
rdaddress[0] => segment[0][6].RADDR
rdaddress[0] => segment[0][5].RADDR
rdaddress[0] => segment[0][4].RADDR
rdaddress[0] => segment[0][3].RADDR
rdaddress[0] => segment[0][2].RADDR
rdaddress[0] => segment[0][1].RADDR
rdaddress[0] => segment[0][0].RADDR
rdaddress[1] => segment[0][7].RADDR1
rdaddress[1] => segment[0][6].RADDR1
rdaddress[1] => segment[0][5].RADDR1
rdaddress[1] => segment[0][4].RADDR1
rdaddress[1] => segment[0][3].RADDR1
rdaddress[1] => segment[0][2].RADDR1
rdaddress[1] => segment[0][1].RADDR1
rdaddress[1] => segment[0][0].RADDR1
rdaddress[2] => segment[0][7].RADDR2
rdaddress[2] => segment[0][6].RADDR2
rdaddress[2] => segment[0][5].RADDR2
rdaddress[2] => segment[0][4].RADDR2
rdaddress[2] => segment[0][3].RADDR2
rdaddress[2] => segment[0][2].RADDR2
rdaddress[2] => segment[0][1].RADDR2
rdaddress[2] => segment[0][0].RADDR2
rdaddress[3] => segment[0][7].RADDR3
rdaddress[3] => segment[0][6].RADDR3
rdaddress[3] => segment[0][5].RADDR3
rdaddress[3] => segment[0][4].RADDR3
rdaddress[3] => segment[0][3].RADDR3
rdaddress[3] => segment[0][2].RADDR3
rdaddress[3] => segment[0][1].RADDR3
rdaddress[3] => segment[0][0].RADDR3
rdaddress[4] => segment[0][7].RADDR4
rdaddress[4] => segment[0][6].RADDR4
rdaddress[4] => segment[0][5].RADDR4
rdaddress[4] => segment[0][4].RADDR4
rdaddress[4] => segment[0][3].RADDR4
rdaddress[4] => segment[0][2].RADDR4
rdaddress[4] => segment[0][1].RADDR4
rdaddress[4] => segment[0][0].RADDR4
rdaddress[5] => segment[0][7].RADDR5
rdaddress[5] => segment[0][6].RADDR5
rdaddress[5] => segment[0][5].RADDR5
rdaddress[5] => segment[0][4].RADDR5
rdaddress[5] => segment[0][3].RADDR5
rdaddress[5] => segment[0][2].RADDR5
rdaddress[5] => segment[0][1].RADDR5
rdaddress[5] => segment[0][0].RADDR5
rdaddress[6] => segment[0][7].RADDR6
rdaddress[6] => segment[0][6].RADDR6
rdaddress[6] => segment[0][5].RADDR6
rdaddress[6] => segment[0][4].RADDR6
rdaddress[6] => segment[0][3].RADDR6
rdaddress[6] => segment[0][2].RADDR6
rdaddress[6] => segment[0][1].RADDR6
rdaddress[6] => segment[0][0].RADDR6
rdaddress[7] => segment[0][7].RADDR7
rdaddress[7] => segment[0][6].RADDR7
rdaddress[7] => segment[0][5].RADDR7
rdaddress[7] => segment[0][4].RADDR7
rdaddress[7] => segment[0][3].RADDR7
rdaddress[7] => segment[0][2].RADDR7
rdaddress[7] => segment[0][1].RADDR7
rdaddress[7] => segment[0][0].RADDR7
rdaddress[8] => segment[0][7].RADDR8
rdaddress[8] => segment[0][6].RADDR8
rdaddress[8] => segment[0][5].RADDR8
rdaddress[8] => segment[0][4].RADDR8
rdaddress[8] => segment[0][3].RADDR8
rdaddress[8] => segment[0][2].RADDR8
rdaddress[8] => segment[0][1].RADDR8
rdaddress[8] => segment[0][0].RADDR8
rdaddress[9] => segment[0][7].RADDR9
rdaddress[9] => segment[0][6].RADDR9
rdaddress[9] => segment[0][5].RADDR9
rdaddress[9] => segment[0][4].RADDR9
rdaddress[9] => segment[0][3].RADDR9
rdaddress[9] => segment[0][2].RADDR9
rdaddress[9] => segment[0][1].RADDR9
rdaddress[9] => segment[0][0].RADDR9
outclock => segment[0][7].CLK1
outclock => segment[0][6].CLK1
outclock => segment[0][5].CLK1
outclock => segment[0][4].CLK1
outclock => segment[0][3].CLK1
outclock => segment[0][2].CLK1
outclock => segment[0][1].CLK1
outclock => segment[0][0].CLK1
outclocken => segment[0][7].ENA1
outclocken => segment[0][6].ENA1
outclocken => segment[0][5].ENA1
outclocken => segment[0][4].ENA1
outclocken => segment[0][3].ENA1
outclocken => segment[0][2].ENA1
outclocken => segment[0][1].ENA1
outclocken => segment[0][0].ENA1
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT
q[6] <= segment[0][6].DATAOUT
q[7] <= segment[0][7].DATAOUT


|N105_system|N_105_system:inst|onchip_ram:the_onchip_ram|onchip_ram_lane0_module:onchip_ram_lane0
clk => clk~0.IN1
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
rdaddress[0] => read_address[0].IN1
rdaddress[1] => read_address[1].IN1
rdaddress[2] => read_address[2].IN1
rdaddress[3] => read_address[3].IN1
rdaddress[4] => read_address[4].IN1
rdaddress[5] => read_address[5].IN1
rdaddress[6] => read_address[6].IN1
rdaddress[7] => read_address[7].IN1
rdaddress[8] => read_address[8].IN1
rdaddress[9] => read_address[9].IN1
rdclken => rdclken~0.IN1
wraddress[0] => wraddress[0]~9.IN1
wraddress[1] => wraddress[1]~8.IN1
wraddress[2] => wraddress[2]~7.IN1
wraddress[3] => wraddress[3]~6.IN1
wraddress[4] => wraddress[4]~5.IN1
wraddress[5] => wraddress[5]~4.IN1
wraddress[6] => wraddress[6]~3.IN1
wraddress[7] => wraddress[7]~2.IN1
wraddress[8] => wraddress[8]~1.IN1
wraddress[9] => wraddress[9]~0.IN1
wrclock => wrclock~0.IN1
wren => wren~0.IN1
q[0] <= lpm_ram_dp:lpm_ram_dp_component.q
q[1] <= lpm_ram_dp:lpm_ram_dp_component.q
q[2] <= lpm_ram_dp:lpm_ram_dp_component.q
q[3] <= lpm_ram_dp:lpm_ram_dp_component.q
q[4] <= lpm_ram_dp:lpm_ram_dp_component.q
q[5] <= lpm_ram_dp:lpm_ram_dp_component.q
q[6] <= lpm_ram_dp:lpm_ram_dp_component.q
q[7] <= lpm_ram_dp:lpm_ram_dp_component.q


|N105_system|N_105_system:inst|onchip_ram:the_onchip_ram|onchip_ram_lane0_module:onchip_ram_lane0|lpm_ram_dp:lpm_ram_dp_component
data[0] => altdpram:sram.data[0]
data[1] => altdpram:sram.data[1]
data[2] => altdpram:sram.data[2]
data[3] => altdpram:sram.data[3]
data[4] => altdpram:sram.data[4]
data[5] => altdpram:sram.data[5]
data[6] => altdpram:sram.data[6]
data[7] => altdpram:sram.data[7]
rdaddress[0] => altdpram:sram.rdaddress[0]
rdaddress[1] => altdpram:sram.rdaddress[1]
rdaddress[2] => altdpram:sram.rdaddress[2]
rdaddress[3] => altdpram:sram.rdaddress[3]
rdaddress[4] => altdpram:sram.rdaddress[4]
rdaddress[5] => altdpram:sram.rdaddress[5]
rdaddress[6] => altdpram:sram.rdaddress[6]
rdaddress[7] => altdpram:sram.rdaddress[7]
rdaddress[8] => altdpram:sram.rdaddress[8]
rdaddress[9] => altdpram:sram.rdaddress[9]
wraddress[0] => altdpram:sram.wraddress[0]
wraddress[1] => altdpram:sram.wraddress[1]
wraddress[2] => altdpram:sram.wraddress[2]
wraddress[3] => altdpram:sram.wraddress[3]
wraddress[4] => altdpram:sram.wraddress[4]
wraddress[5] => altdpram:sram.wraddress[5]
wraddress[6] => altdpram:sram.wraddress[6]
wraddress[7] => altdpram:sram.wraddress[7]
wraddress[8] => altdpram:sram.wraddress[8]
wraddress[9] => altdpram:sram.wraddress[9]
rdclock => altdpram:sram.outclock
rdclken => altdpram:sram.outclocken
wrclock => altdpram:sram.inclock
wren => altdpram:sram.wren
q[0] <= altdpram:sram.q[0]
q[1] <= altdpram:sram.q[1]
q[2] <= altdpram:sram.q[2]
q[3] <= altdpram:sram.q[3]
q[4] <= altdpram:sram.q[4]
q[5] <= altdpram:sram.q[5]
q[6] <= altdpram:sram.q[6]
q[7] <= altdpram:sram.q[7]


|N105_system|N_105_system:inst|onchip_ram:the_onchip_ram|onchip_ram_lane0_module:onchip_ram_lane0|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram
wren => segment[0][7].WE
wren => segment[0][6].WE
wren => segment[0][5].WE
wren => segment[0][4].WE
wren => segment[0][3].WE
wren => segment[0][2].WE
wren => segment[0][1].WE
wren => segment[0][0].WE
data[0] => segment[0][0].DATAIN
data[1] => segment[0][1].DATAIN
data[2] => segment[0][2].DATAIN
data[3] => segment[0][3].DATAIN
data[4] => segment[0][4].DATAIN
data[5] => segment[0][5].DATAIN
data[6] => segment[0][6].DATAIN
data[7] => segment[0][7].DATAIN
wraddress[0] => segment[0][7].WADDR
wraddress[0] => segment[0][6].WADDR
wraddress[0] => segment[0][5].WADDR
wraddress[0] => segment[0][4].WADDR
wraddress[0] => segment[0][3].WADDR
wraddress[0] => segment[0][2].WADDR
wraddress[0] => segment[0][1].WADDR
wraddress[0] => segment[0][0].WADDR
wraddress[1] => segment[0][7].WADDR1
wraddress[1] => segment[0][6].WADDR1
wraddress[1] => segment[0][5].WADDR1
wraddress[1] => segment[0][4].WADDR1
wraddress[1] => segment[0][3].WADDR1
wraddress[1] => segment[0][2].WADDR1
wraddress[1] => segment[0][1].WADDR1
wraddress[1] => segment[0][0].WADDR1
wraddress[2] => segment[0][7].WADDR2
wraddress[2] => segment[0][6].WADDR2
wraddress[2] => segment[0][5].WADDR2
wraddress[2] => segment[0][4].WADDR2
wraddress[2] => segment[0][3].WADDR2
wraddress[2] => segment[0][2].WADDR2
wraddress[2] => segment[0][1].WADDR2
wraddress[2] => segment[0][0].WADDR2
wraddress[3] => segment[0][7].WADDR3
wraddress[3] => segment[0][6].WADDR3
wraddress[3] => segment[0][5].WADDR3
wraddress[3] => segment[0][4].WADDR3
wraddress[3] => segment[0][3].WADDR3
wraddress[3] => segment[0][2].WADDR3
wraddress[3] => segment[0][1].WADDR3
wraddress[3] => segment[0][0].WADDR3
wraddress[4] => segment[0][7].WADDR4
wraddress[4] => segment[0][6].WADDR4
wraddress[4] => segment[0][5].WADDR4
wraddress[4] => segment[0][4].WADDR4
wraddress[4] => segment[0][3].WADDR4
wraddress[4] => segment[0][2].WADDR4
wraddress[4] => segment[0][1].WADDR4
wraddress[4] => segment[0][0].WADDR4
wraddress[5] => segment[0][7].WADDR5
wraddress[5] => segment[0][6].WADDR5
wraddress[5] => segment[0][5].WADDR5
wraddress[5] => segment[0][4].WADDR5
wraddress[5] => segment[0][3].WADDR5
wraddress[5] => segment[0][2].WADDR5
wraddress[5] => segment[0][1].WADDR5
wraddress[5] => segment[0][0].WADDR5
wraddress[6] => segment[0][7].WADDR6
wraddress[6] => segment[0][6].WADDR6
wraddress[6] => segment[0][5].WADDR6
wraddress[6] => segment[0][4].WADDR6
wraddress[6] => segment[0][3].WADDR6
wraddress[6] => segment[0][2].WADDR6
wraddress[6] => segment[0][1].WADDR6
wraddress[6] => segment[0][0].WADDR6
wraddress[7] => segment[0][7].WADDR7
wraddress[7] => segment[0][6].WADDR7
wraddress[7] => segment[0][5].WADDR7
wraddress[7] => segment[0][4].WADDR7
wraddress[7] => segment[0][3].WADDR7
wraddress[7] => segment[0][2].WADDR7
wraddress[7] => segment[0][1].WADDR7
wraddress[7] => segment[0][0].WADDR7
wraddress[8] => segment[0][7].WADDR8
wraddress[8] => segment[0][6].WADDR8
wraddress[8] => segment[0][5].WADDR8
wraddress[8] => segment[0][4].WADDR8
wraddress[8] => segment[0][3].WADDR8
wraddress[8] => segment[0][2].WADDR8
wraddress[8] => segment[0][1].WADDR8
wraddress[8] => segment[0][0].WADDR8
wraddress[9] => segment[0][7].WADDR9
wraddress[9] => segment[0][6].WADDR9
wraddress[9] => segment[0][5].WADDR9
wraddress[9] => segment[0][4].WADDR9
wraddress[9] => segment[0][3].WADDR9
wraddress[9] => segment[0][2].WADDR9
wraddress[9] => segment[0][1].WADDR9
wraddress[9] => segment[0][0].WADDR9
inclock => segment[0][7].CLK0
inclock => segment[0][6].CLK0
inclock => segment[0][5].CLK0
inclock => segment[0][4].CLK0
inclock => segment[0][3].CLK0
inclock => segment[0][2].CLK0
inclock => segment[0][1].CLK0
inclock => segment[0][0].CLK0
rden => segment[0][7].RE
rden => segment[0][6].RE
rden => segment[0][5].RE
rden => segment[0][4].RE
rden => segment[0][3].RE
rden => segment[0][2].RE
rden => segment[0][1].RE
rden => segment[0][0].RE
rdaddress[0] => segment[0][7].RADDR
rdaddress[0] => segment[0][6].RADDR
rdaddress[0] => segment[0][5].RADDR
rdaddress[0] => segment[0][4].RADDR
rdaddress[0] => segment[0][3].RADDR
rdaddress[0] => segment[0][2].RADDR
rdaddress[0] => segment[0][1].RADDR
rdaddress[0] => segment[0][0].RADDR
rdaddress[1] => segment[0][7].RADDR1
rdaddress[1] => segment[0][6].RADDR1
rdaddress[1] => segment[0][5].RADDR1
rdaddress[1] => segment[0][4].RADDR1
rdaddress[1] => segment[0][3].RADDR1
rdaddress[1] => segment[0][2].RADDR1
rdaddress[1] => segment[0][1].RADDR1
rdaddress[1] => segment[0][0].RADDR1
rdaddress[2] => segment[0][7].RADDR2
rdaddress[2] => segment[0][6].RADDR2
rdaddress[2] => segment[0][5].RADDR2
rdaddress[2] => segment[0][4].RADDR2
rdaddress[2] => segment[0][3].RADDR2
rdaddress[2] => segment[0][2].RADDR2
rdaddress[2] => segment[0][1].RADDR2
rdaddress[2] => segment[0][0].RADDR2
rdaddress[3] => segment[0][7].RADDR3
rdaddress[3] => segment[0][6].RADDR3
rdaddress[3] => segment[0][5].RADDR3
rdaddress[3] => segment[0][4].RADDR3
rdaddress[3] => segment[0][3].RADDR3
rdaddress[3] => segment[0][2].RADDR3
rdaddress[3] => segment[0][1].RADDR3
rdaddress[3] => segment[0][0].RADDR3
rdaddress[4] => segment[0][7].RADDR4
rdaddress[4] => segment[0][6].RADDR4
rdaddress[4] => segment[0][5].RADDR4
rdaddress[4] => segment[0][4].RADDR4
rdaddress[4] => segment[0][3].RADDR4
rdaddress[4] => segment[0][2].RADDR4
rdaddress[4] => segment[0][1].RADDR4
rdaddress[4] => segment[0][0].RADDR4
rdaddress[5] => segment[0][7].RADDR5
rdaddress[5] => segment[0][6].RADDR5
rdaddress[5] => segment[0][5].RADDR5
rdaddress[5] => segment[0][4].RADDR5
rdaddress[5] => segment[0][3].RADDR5
rdaddress[5] => segment[0][2].RADDR5
rdaddress[5] => segment[0][1].RADDR5
rdaddress[5] => segment[0][0].RADDR5
rdaddress[6] => segment[0][7].RADDR6
rdaddress[6] => segment[0][6].RADDR6
rdaddress[6] => segment[0][5].RADDR6
rdaddress[6] => segment[0][4].RADDR6
rdaddress[6] => segment[0][3].RADDR6
rdaddress[6] => segment[0][2].RADDR6
rdaddress[6] => segment[0][1].RADDR6
rdaddress[6] => segment[0][0].RADDR6
rdaddress[7] => segment[0][7].RADDR7
rdaddress[7] => segment[0][6].RADDR7
rdaddress[7] => segment[0][5].RADDR7
rdaddress[7] => segment[0][4].RADDR7
rdaddress[7] => segment[0][3].RADDR7
rdaddress[7] => segment[0][2].RADDR7
rdaddress[7] => segment[0][1].RADDR7
rdaddress[7] => segment[0][0].RADDR7
rdaddress[8] => segment[0][7].RADDR8
rdaddress[8] => segment[0][6].RADDR8
rdaddress[8] => segment[0][5].RADDR8
rdaddress[8] => segment[0][4].RADDR8
rdaddress[8] => segment[0][3].RADDR8
rdaddress[8] => segment[0][2].RADDR8
rdaddress[8] => segment[0][1].RADDR8
rdaddress[8] => segment[0][0].RADDR8
rdaddress[9] => segment[0][7].RADDR9
rdaddress[9] => segment[0][6].RADDR9
rdaddress[9] => segment[0][5].RADDR9
rdaddress[9] => segment[0][4].RADDR9
rdaddress[9] => segment[0][3].RADDR9
rdaddress[9] => segment[0][2].RADDR9
rdaddress[9] => segment[0][1].RADDR9
rdaddress[9] => segment[0][0].RADDR9
outclock => segment[0][7].CLK1
outclock => segment[0][6].CLK1
outclock => segment[0][5].CLK1
outclock => segment[0][4].CLK1
outclock => segment[0][3].CLK1
outclock => segment[0][2].CLK1
outclock => segment[0][1].CLK1
outclock => segment[0][0].CLK1
outclocken => segment[0][7].ENA1
outclocken => segment[0][6].ENA1
outclocken => segment[0][5].ENA1
outclocken => segment[0][4].ENA1
outclocken => segment[0][3].ENA1
outclocken => segment[0][2].ENA1
outclocken => segment[0][1].ENA1
outclocken => segment[0][0].ENA1
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT
q[6] <= segment[0][6].DATAOUT
q[7] <= segment[0][7].DATAOUT


|N105_system|N_105_system:inst|onchip_rom_s1_arbitrator:the_onchip_rom_s1
clk => d1_onchip_rom_s1_end_xfer~reg0.CLK
clk => uoccl_n105_0_instruction_master_read_data_valid_onchip_rom_s1_shift_register.CLK
d2_reset_n => onchip_rom_s1_reset_n.DATAIN
d2_reset_n => d1_onchip_rom_s1_end_xfer~reg0.PRESET
d2_reset_n => uoccl_n105_0_instruction_master_read_data_valid_onchip_rom_s1_shift_register.ACLR
onchip_rom_s1_readdata[0] => onchip_rom_s1_readdata_from_sa[0].DATAIN
onchip_rom_s1_readdata[1] => onchip_rom_s1_readdata_from_sa[1].DATAIN
onchip_rom_s1_readdata[2] => onchip_rom_s1_readdata_from_sa[2].DATAIN
onchip_rom_s1_readdata[3] => onchip_rom_s1_readdata_from_sa[3].DATAIN
onchip_rom_s1_readdata[4] => onchip_rom_s1_readdata_from_sa[4].DATAIN
onchip_rom_s1_readdata[5] => onchip_rom_s1_readdata_from_sa[5].DATAIN
onchip_rom_s1_readdata[6] => onchip_rom_s1_readdata_from_sa[6].DATAIN
onchip_rom_s1_readdata[7] => onchip_rom_s1_readdata_from_sa[7].DATAIN
onchip_rom_s1_readdata[8] => onchip_rom_s1_readdata_from_sa[8].DATAIN
onchip_rom_s1_readdata[9] => onchip_rom_s1_readdata_from_sa[9].DATAIN
onchip_rom_s1_readdata[10] => onchip_rom_s1_readdata_from_sa[10].DATAIN
onchip_rom_s1_readdata[11] => onchip_rom_s1_readdata_from_sa[11].DATAIN
onchip_rom_s1_readdata[12] => onchip_rom_s1_readdata_from_sa[12].DATAIN
onchip_rom_s1_readdata[13] => onchip_rom_s1_readdata_from_sa[13].DATAIN
onchip_rom_s1_readdata[14] => onchip_rom_s1_readdata_from_sa[14].DATAIN
onchip_rom_s1_readdata[15] => onchip_rom_s1_readdata_from_sa[15].DATAIN
uoccl_n105_0_instruction_master_address_to_slave[1] => onchip_rom_s1_address[0].DATAIN
uoccl_n105_0_instruction_master_address_to_slave[2] => onchip_rom_s1_address[1].DATAIN
uoccl_n105_0_instruction_master_address_to_slave[3] => onchip_rom_s1_address[2].DATAIN
uoccl_n105_0_instruction_master_address_to_slave[4] => onchip_rom_s1_address[3].DATAIN
uoccl_n105_0_instruction_master_address_to_slave[5] => onchip_rom_s1_address[4].DATAIN
uoccl_n105_0_instruction_master_address_to_slave[6] => onchip_rom_s1_address[5].DATAIN
uoccl_n105_0_instruction_master_address_to_slave[7] => onchip_rom_s1_address[6].DATAIN
uoccl_n105_0_instruction_master_address_to_slave[8] => onchip_rom_s1_address[7].DATAIN
uoccl_n105_0_instruction_master_address_to_slave[9] => onchip_rom_s1_address[8].DATAIN
uoccl_n105_0_instruction_master_address_to_slave[10] => onchip_rom_s1_address[9].DATAIN
uoccl_n105_0_instruction_master_address_to_slave[11] => i~0.IN4
uoccl_n105_0_instruction_master_address_to_slave[12] => i~0.IN3
uoccl_n105_0_instruction_master_address_to_slave[13] => i~0.IN2
uoccl_n105_0_instruction_master_address_to_slave[14] => i~0.IN1
uoccl_n105_0_instruction_master_address_to_slave[15] => i~0.IN0
uoccl_n105_0_instruction_master_read => i5.IN0
uoccl_n105_0_instruction_master_read => i22.IN0
uoccl_n105_0_instruction_master_read => i25.IN0
d1_onchip_rom_s1_end_xfer <= d1_onchip_rom_s1_end_xfer~reg0.DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_address[0] <= uoccl_n105_0_instruction_master_address_to_slave[1].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_address[1] <= uoccl_n105_0_instruction_master_address_to_slave[2].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_address[2] <= uoccl_n105_0_instruction_master_address_to_slave[3].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_address[3] <= uoccl_n105_0_instruction_master_address_to_slave[4].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_address[4] <= uoccl_n105_0_instruction_master_address_to_slave[5].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_address[5] <= uoccl_n105_0_instruction_master_address_to_slave[6].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_address[6] <= uoccl_n105_0_instruction_master_address_to_slave[7].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_address[7] <= uoccl_n105_0_instruction_master_address_to_slave[8].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_address[8] <= uoccl_n105_0_instruction_master_address_to_slave[9].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_address[9] <= uoccl_n105_0_instruction_master_address_to_slave[10].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_readdata_from_sa[0] <= onchip_rom_s1_readdata[0].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_readdata_from_sa[1] <= onchip_rom_s1_readdata[1].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_readdata_from_sa[2] <= onchip_rom_s1_readdata[2].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_readdata_from_sa[3] <= onchip_rom_s1_readdata[3].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_readdata_from_sa[4] <= onchip_rom_s1_readdata[4].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_readdata_from_sa[5] <= onchip_rom_s1_readdata[5].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_readdata_from_sa[6] <= onchip_rom_s1_readdata[6].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_readdata_from_sa[7] <= onchip_rom_s1_readdata[7].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_readdata_from_sa[8] <= onchip_rom_s1_readdata[8].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_readdata_from_sa[9] <= onchip_rom_s1_readdata[9].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_readdata_from_sa[10] <= onchip_rom_s1_readdata[10].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_readdata_from_sa[11] <= onchip_rom_s1_readdata[11].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_readdata_from_sa[12] <= onchip_rom_s1_readdata[12].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_readdata_from_sa[13] <= onchip_rom_s1_readdata[13].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_readdata_from_sa[14] <= onchip_rom_s1_readdata[14].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_readdata_from_sa[15] <= onchip_rom_s1_readdata[15].DB_MAX_OUTPUT_PORT_TYPE
onchip_rom_s1_reset_n <= d2_reset_n.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_granted_onchip_rom_s1 <= i24.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_qualified_request_onchip_rom_s1 <= i24.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_read_data_valid_onchip_rom_s1 <= uoccl_n105_0_instruction_master_read_data_valid_onchip_rom_s1_shift_register.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 <= i5.DB_MAX_OUTPUT_PORT_TYPE


|N105_system|N_105_system:inst|onchip_rom:the_onchip_rom
address[0] => onchip_rom_lane0_address[0].IN1
address[1] => onchip_rom_lane0_address[1].IN1
address[2] => onchip_rom_lane0_address[2].IN1
address[3] => onchip_rom_lane0_address[3].IN1
address[4] => onchip_rom_lane0_address[4].IN1
address[5] => onchip_rom_lane0_address[5].IN1
address[6] => onchip_rom_lane0_address[6].IN1
address[7] => onchip_rom_lane0_address[7].IN1
address[8] => onchip_rom_lane0_address[8].IN1
address[9] => onchip_rom_lane0_address[9].IN1
clk => clk~0.IN1
reset_n => reset_n~0.IN1
readdata[0] <= onchip_rom_lane0_module:onchip_rom_lane0.q
readdata[1] <= onchip_rom_lane0_module:onchip_rom_lane0.q
readdata[2] <= onchip_rom_lane0_module:onchip_rom_lane0.q
readdata[3] <= onchip_rom_lane0_module:onchip_rom_lane0.q
readdata[4] <= onchip_rom_lane0_module:onchip_rom_lane0.q
readdata[5] <= onchip_rom_lane0_module:onchip_rom_lane0.q
readdata[6] <= onchip_rom_lane0_module:onchip_rom_lane0.q
readdata[7] <= onchip_rom_lane0_module:onchip_rom_lane0.q
readdata[8] <= onchip_rom_lane0_module:onchip_rom_lane0.q
readdata[9] <= onchip_rom_lane0_module:onchip_rom_lane0.q
readdata[10] <= onchip_rom_lane0_module:onchip_rom_lane0.q
readdata[11] <= onchip_rom_lane0_module:onchip_rom_lane0.q
readdata[12] <= onchip_rom_lane0_module:onchip_rom_lane0.q
readdata[13] <= onchip_rom_lane0_module:onchip_rom_lane0.q
readdata[14] <= onchip_rom_lane0_module:onchip_rom_lane0.q
readdata[15] <= onchip_rom_lane0_module:onchip_rom_lane0.q


|N105_system|N_105_system:inst|onchip_rom:the_onchip_rom|onchip_rom_lane0_module:onchip_rom_lane0
address[0] => read_address[0].IN1
address[1] => read_address[1].IN1
address[2] => read_address[2].IN1
address[3] => read_address[3].IN1
address[4] => read_address[4].IN1
address[5] => read_address[5].IN1
address[6] => read_address[6].IN1
address[7] => read_address[7].IN1
address[8] => read_address[8].IN1
address[9] => read_address[9].IN1
clk => clk~0.IN1
q[0] <= lpm_rom:lpm_rom_component.q
q[1] <= lpm_rom:lpm_rom_component.q
q[2] <= lpm_rom:lpm_rom_component.q
q[3] <= lpm_rom:lpm_rom_component.q
q[4] <= lpm_rom:lpm_rom_component.q
q[5] <= lpm_rom:lpm_rom_component.q
q[6] <= lpm_rom:lpm_rom_component.q
q[7] <= lpm_rom:lpm_rom_component.q
q[8] <= lpm_rom:lpm_rom_component.q
q[9] <= lpm_rom:lpm_rom_component.q
q[10] <= lpm_rom:lpm_rom_component.q
q[11] <= lpm_rom:lpm_rom_component.q
q[12] <= lpm_rom:lpm_rom_component.q
q[13] <= lpm_rom:lpm_rom_component.q
q[14] <= lpm_rom:lpm_rom_component.q
q[15] <= lpm_rom:lpm_rom_component.q


|N105_system|N_105_system:inst|onchip_rom:the_onchip_rom|onchip_rom_lane0_module:onchip_rom_lane0|lpm_rom:lpm_rom_component
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
address[8] => altrom:srom.address[8]
address[9] => altrom:srom.address[9]
inclock => altrom:srom.clocki
memenab => otri[15].OE
memenab => otri[14].OE
memenab => otri[13].OE
memenab => otri[12].OE
memenab => otri[11].OE
memenab => otri[10].OE
memenab => otri[9].OE
memenab => otri[8].OE
memenab => otri[7].OE
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= otri[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= otri[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= otri[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= otri[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= otri[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= otri[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= otri[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= otri[15].DB_MAX_OUTPUT_PORT_TYPE


|N105_system|N_105_system:inst|onchip_rom:the_onchip_rom|onchip_rom_lane0_module:onchip_rom_lane0|lpm_rom:lpm_rom_component|altrom:srom
address[0] => segment[0][15].WADDR
address[0] => segment[0][15].RADDR
address[0] => segment[0][14].WADDR
address[0] => segment[0][14].RADDR
address[0] => segment[0][13].WADDR
address[0] => segment[0][13].RADDR
address[0] => segment[0][12].WADDR
address[0] => segment[0][12].RADDR
address[0] => segment[0][11].WADDR
address[0] => segment[0][11].RADDR
address[0] => segment[0][10].WADDR
address[0] => segment[0][10].RADDR
address[0] => segment[0][9].WADDR
address[0] => segment[0][9].RADDR
address[0] => segment[0][8].WADDR
address[0] => segment[0][8].RADDR
address[0] => segment[0][7].WADDR
address[0] => segment[0][7].RADDR
address[0] => segment[0][6].WADDR
address[0] => segment[0][6].RADDR
address[0] => segment[0][5].WADDR
address[0] => segment[0][5].RADDR
address[0] => segment[0][4].WADDR
address[0] => segment[0][4].RADDR
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][15].WADDR1
address[1] => segment[0][15].RADDR1
address[1] => segment[0][14].WADDR1
address[1] => segment[0][14].RADDR1
address[1] => segment[0][13].WADDR1
address[1] => segment[0][13].RADDR1
address[1] => segment[0][12].WADDR1
address[1] => segment[0][12].RADDR1
address[1] => segment[0][11].WADDR1
address[1] => segment[0][11].RADDR1
address[1] => segment[0][10].WADDR1
address[1] => segment[0][10].RADDR1
address[1] => segment[0][9].WADDR1
address[1] => segment[0][9].RADDR1
address[1] => segment[0][8].WADDR1
address[1] => segment[0][8].RADDR1
address[1] => segment[0][7].WADDR1
address[1] => segment[0][7].RADDR1
address[1] => segment[0][6].WADDR1
address[1] => segment[0][6].RADDR1
address[1] => segment[0][5].WADDR1
address[1] => segment[0][5].RADDR1
address[1] => segment[0][4].WADDR1
address[1] => segment[0][4].RADDR1
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][15].WADDR2
address[2] => segment[0][15].RADDR2
address[2] => segment[0][14].WADDR2
address[2] => segment[0][14].RADDR2
address[2] => segment[0][13].WADDR2
address[2] => segment[0][13].RADDR2
address[2] => segment[0][12].WADDR2
address[2] => segment[0][12].RADDR2
address[2] => segment[0][11].WADDR2
address[2] => segment[0][11].RADDR2
address[2] => segment[0][10].WADDR2
address[2] => segment[0][10].RADDR2
address[2] => segment[0][9].WADDR2
address[2] => segment[0][9].RADDR2
address[2] => segment[0][8].WADDR2
address[2] => segment[0][8].RADDR2
address[2] => segment[0][7].WADDR2
address[2] => segment[0][7].RADDR2
address[2] => segment[0][6].WADDR2
address[2] => segment[0][6].RADDR2
address[2] => segment[0][5].WADDR2
address[2] => segment[0][5].RADDR2
address[2] => segment[0][4].WADDR2
address[2] => segment[0][4].RADDR2
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][15].WADDR3
address[3] => segment[0][15].RADDR3
address[3] => segment[0][14].WADDR3
address[3] => segment[0][14].RADDR3
address[3] => segment[0][13].WADDR3
address[3] => segment[0][13].RADDR3
address[3] => segment[0][12].WADDR3
address[3] => segment[0][12].RADDR3
address[3] => segment[0][11].WADDR3
address[3] => segment[0][11].RADDR3
address[3] => segment[0][10].WADDR3
address[3] => segment[0][10].RADDR3
address[3] => segment[0][9].WADDR3
address[3] => segment[0][9].RADDR3
address[3] => segment[0][8].WADDR3
address[3] => segment[0][8].RADDR3
address[3] => segment[0][7].WADDR3
address[3] => segment[0][7].RADDR3
address[3] => segment[0][6].WADDR3
address[3] => segment[0][6].RADDR3
address[3] => segment[0][5].WADDR3
address[3] => segment[0][5].RADDR3
address[3] => segment[0][4].WADDR3
address[3] => segment[0][4].RADDR3
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][15].WADDR4
address[4] => segment[0][15].RADDR4
address[4] => segment[0][14].WADDR4
address[4] => segment[0][14].RADDR4
address[4] => segment[0][13].WADDR4
address[4] => segment[0][13].RADDR4
address[4] => segment[0][12].WADDR4
address[4] => segment[0][12].RADDR4
address[4] => segment[0][11].WADDR4
address[4] => segment[0][11].RADDR4
address[4] => segment[0][10].WADDR4
address[4] => segment[0][10].RADDR4
address[4] => segment[0][9].WADDR4
address[4] => segment[0][9].RADDR4
address[4] => segment[0][8].WADDR4
address[4] => segment[0][8].RADDR4
address[4] => segment[0][7].WADDR4
address[4] => segment[0][7].RADDR4
address[4] => segment[0][6].WADDR4
address[4] => segment[0][6].RADDR4
address[4] => segment[0][5].WADDR4
address[4] => segment[0][5].RADDR4
address[4] => segment[0][4].WADDR4
address[4] => segment[0][4].RADDR4
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][15].WADDR5
address[5] => segment[0][15].RADDR5
address[5] => segment[0][14].WADDR5
address[5] => segment[0][14].RADDR5
address[5] => segment[0][13].WADDR5
address[5] => segment[0][13].RADDR5
address[5] => segment[0][12].WADDR5
address[5] => segment[0][12].RADDR5
address[5] => segment[0][11].WADDR5
address[5] => segment[0][11].RADDR5
address[5] => segment[0][10].WADDR5
address[5] => segment[0][10].RADDR5
address[5] => segment[0][9].WADDR5
address[5] => segment[0][9].RADDR5
address[5] => segment[0][8].WADDR5
address[5] => segment[0][8].RADDR5
address[5] => segment[0][7].WADDR5
address[5] => segment[0][7].RADDR5
address[5] => segment[0][6].WADDR5
address[5] => segment[0][6].RADDR5
address[5] => segment[0][5].WADDR5
address[5] => segment[0][5].RADDR5
address[5] => segment[0][4].WADDR5
address[5] => segment[0][4].RADDR5
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][15].WADDR6
address[6] => segment[0][15].RADDR6
address[6] => segment[0][14].WADDR6
address[6] => segment[0][14].RADDR6
address[6] => segment[0][13].WADDR6
address[6] => segment[0][13].RADDR6
address[6] => segment[0][12].WADDR6
address[6] => segment[0][12].RADDR6
address[6] => segment[0][11].WADDR6
address[6] => segment[0][11].RADDR6
address[6] => segment[0][10].WADDR6
address[6] => segment[0][10].RADDR6
address[6] => segment[0][9].WADDR6
address[6] => segment[0][9].RADDR6
address[6] => segment[0][8].WADDR6
address[6] => segment[0][8].RADDR6
address[6] => segment[0][7].WADDR6
address[6] => segment[0][7].RADDR6
address[6] => segment[0][6].WADDR6
address[6] => segment[0][6].RADDR6
address[6] => segment[0][5].WADDR6
address[6] => segment[0][5].RADDR6
address[6] => segment[0][4].WADDR6
address[6] => segment[0][4].RADDR6
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[0][15].WADDR7
address[7] => segment[0][15].RADDR7
address[7] => segment[0][14].WADDR7
address[7] => segment[0][14].RADDR7
address[7] => segment[0][13].WADDR7
address[7] => segment[0][13].RADDR7
address[7] => segment[0][12].WADDR7
address[7] => segment[0][12].RADDR7
address[7] => segment[0][11].WADDR7
address[7] => segment[0][11].RADDR7
address[7] => segment[0][10].WADDR7
address[7] => segment[0][10].RADDR7
address[7] => segment[0][9].WADDR7
address[7] => segment[0][9].RADDR7
address[7] => segment[0][8].WADDR7
address[7] => segment[0][8].RADDR7
address[7] => segment[0][7].WADDR7
address[7] => segment[0][7].RADDR7
address[7] => segment[0][6].WADDR7
address[7] => segment[0][6].RADDR7
address[7] => segment[0][5].WADDR7
address[7] => segment[0][5].RADDR7
address[7] => segment[0][4].WADDR7
address[7] => segment[0][4].RADDR7
address[7] => segment[0][3].WADDR7
address[7] => segment[0][3].RADDR7
address[7] => segment[0][2].WADDR7
address[7] => segment[0][2].RADDR7
address[7] => segment[0][1].WADDR7
address[7] => segment[0][1].RADDR7
address[7] => segment[0][0].WADDR7
address[7] => segment[0][0].RADDR7
address[8] => segment[0][15].WADDR8
address[8] => segment[0][15].RADDR8
address[8] => segment[0][14].WADDR8
address[8] => segment[0][14].RADDR8
address[8] => segment[0][13].WADDR8
address[8] => segment[0][13].RADDR8
address[8] => segment[0][12].WADDR8
address[8] => segment[0][12].RADDR8
address[8] => segment[0][11].WADDR8
address[8] => segment[0][11].RADDR8
address[8] => segment[0][10].WADDR8
address[8] => segment[0][10].RADDR8
address[8] => segment[0][9].WADDR8
address[8] => segment[0][9].RADDR8
address[8] => segment[0][8].WADDR8
address[8] => segment[0][8].RADDR8
address[8] => segment[0][7].WADDR8
address[8] => segment[0][7].RADDR8
address[8] => segment[0][6].WADDR8
address[8] => segment[0][6].RADDR8
address[8] => segment[0][5].WADDR8
address[8] => segment[0][5].RADDR8
address[8] => segment[0][4].WADDR8
address[8] => segment[0][4].RADDR8
address[8] => segment[0][3].WADDR8
address[8] => segment[0][3].RADDR8
address[8] => segment[0][2].WADDR8
address[8] => segment[0][2].RADDR8
address[8] => segment[0][1].WADDR8
address[8] => segment[0][1].RADDR8
address[8] => segment[0][0].WADDR8
address[8] => segment[0][0].RADDR8
address[9] => segment[0][15].WADDR9
address[9] => segment[0][15].RADDR9
address[9] => segment[0][14].WADDR9
address[9] => segment[0][14].RADDR9
address[9] => segment[0][13].WADDR9
address[9] => segment[0][13].RADDR9
address[9] => segment[0][12].WADDR9
address[9] => segment[0][12].RADDR9
address[9] => segment[0][11].WADDR9
address[9] => segment[0][11].RADDR9
address[9] => segment[0][10].WADDR9
address[9] => segment[0][10].RADDR9
address[9] => segment[0][9].WADDR9
address[9] => segment[0][9].RADDR9
address[9] => segment[0][8].WADDR9
address[9] => segment[0][8].RADDR9
address[9] => segment[0][7].WADDR9
address[9] => segment[0][7].RADDR9
address[9] => segment[0][6].WADDR9
address[9] => segment[0][6].RADDR9
address[9] => segment[0][5].WADDR9
address[9] => segment[0][5].RADDR9
address[9] => segment[0][4].WADDR9
address[9] => segment[0][4].RADDR9
address[9] => segment[0][3].WADDR9
address[9] => segment[0][3].RADDR9
address[9] => segment[0][2].WADDR9
address[9] => segment[0][2].RADDR9
address[9] => segment[0][1].WADDR9
address[9] => segment[0][1].RADDR9
address[9] => segment[0][0].WADDR9
address[9] => segment[0][0].RADDR9
clocki => segment[0][15].CLK0
clocki => segment[0][14].CLK0
clocki => segment[0][13].CLK0
clocki => segment[0][12].CLK0
clocki => segment[0][11].CLK0
clocki => segment[0][10].CLK0
clocki => segment[0][9].CLK0
clocki => segment[0][8].CLK0
clocki => segment[0][7].CLK0
clocki => segment[0][6].CLK0
clocki => segment[0][5].CLK0
clocki => segment[0][4].CLK0
clocki => segment[0][3].CLK0
clocki => segment[0][2].CLK0
clocki => segment[0][1].CLK0
clocki => segment[0][0].CLK0
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT
q[6] <= segment[0][6].DATAOUT
q[7] <= segment[0][7].DATAOUT
q[8] <= segment[0][8].DATAOUT
q[9] <= segment[0][9].DATAOUT
q[10] <= segment[0][10].DATAOUT
q[11] <= segment[0][11].DATAOUT
q[12] <= segment[0][12].DATAOUT
q[13] <= segment[0][13].DATAOUT
q[14] <= segment[0][14].DATAOUT
q[15] <= segment[0][15].DATAOUT


|N105_system|N_105_system:inst|uoccl_n105_0_data_master_arbitrator:the_uoccl_n105_0_data_master
d1_lcd_16207_0_control_slave_end_xfer => i15.IN1
lcd_16207_0_control_slave_readdata_from_sa[0] => i62.IN1
lcd_16207_0_control_slave_readdata_from_sa[1] => i63.IN1
lcd_16207_0_control_slave_readdata_from_sa[2] => i64.IN1
lcd_16207_0_control_slave_readdata_from_sa[3] => i65.IN1
lcd_16207_0_control_slave_readdata_from_sa[4] => i66.IN1
lcd_16207_0_control_slave_readdata_from_sa[5] => i67.IN1
lcd_16207_0_control_slave_readdata_from_sa[6] => i68.IN1
lcd_16207_0_control_slave_readdata_from_sa[7] => i69.IN1
lcd_16207_0_control_slave_wait_counter_eq_0 => i15.IN0
onchip_ram_s1_readdata_from_sa[0] => i71.IN1
onchip_ram_s1_readdata_from_sa[1] => i72.IN1
onchip_ram_s1_readdata_from_sa[2] => i73.IN1
onchip_ram_s1_readdata_from_sa[3] => i74.IN1
onchip_ram_s1_readdata_from_sa[4] => i75.IN1
onchip_ram_s1_readdata_from_sa[5] => i76.IN1
onchip_ram_s1_readdata_from_sa[6] => i77.IN1
onchip_ram_s1_readdata_from_sa[7] => i78.IN1
onchip_ram_s1_readdata_from_sa[8] => i79.IN1
onchip_ram_s1_readdata_from_sa[9] => i80.IN1
onchip_ram_s1_readdata_from_sa[10] => i81.IN1
onchip_ram_s1_readdata_from_sa[11] => i82.IN1
onchip_ram_s1_readdata_from_sa[12] => i83.IN1
onchip_ram_s1_readdata_from_sa[13] => i84.IN1
onchip_ram_s1_readdata_from_sa[14] => i85.IN1
onchip_ram_s1_readdata_from_sa[15] => i86.IN0
uoccl_n105_0_data_master_address[0] => uoccl_n105_0_data_master_address_to_slave[0].DATAIN
uoccl_n105_0_data_master_address[1] => uoccl_n105_0_data_master_address_to_slave[1].DATAIN
uoccl_n105_0_data_master_address[2] => uoccl_n105_0_data_master_address_to_slave[2].DATAIN
uoccl_n105_0_data_master_address[3] => uoccl_n105_0_data_master_address_to_slave[3].DATAIN
uoccl_n105_0_data_master_address[4] => uoccl_n105_0_data_master_address_to_slave[4].DATAIN
uoccl_n105_0_data_master_address[5] => uoccl_n105_0_data_master_address_to_slave[5].DATAIN
uoccl_n105_0_data_master_address[6] => uoccl_n105_0_data_master_address_to_slave[6].DATAIN
uoccl_n105_0_data_master_address[7] => uoccl_n105_0_data_master_address_to_slave[7].DATAIN
uoccl_n105_0_data_master_address[8] => uoccl_n105_0_data_master_address_to_slave[8].DATAIN
uoccl_n105_0_data_master_address[9] => uoccl_n105_0_data_master_address_to_slave[9].DATAIN
uoccl_n105_0_data_master_address[10] => uoccl_n105_0_data_master_address_to_slave[10].DATAIN
uoccl_n105_0_data_master_address[15] => uoccl_n105_0_data_master_address_to_slave[15].DATAIN
uoccl_n105_0_data_master_qualified_request_lcd_16207_0_control_slave => i13.IN0
uoccl_n105_0_data_master_qualified_request_lcd_16207_0_control_slave => i6.IN0
uoccl_n105_0_data_master_qualified_request_onchip_ram_s1 => i19.IN0
uoccl_n105_0_data_master_qualified_request_onchip_ram_s1 => i31.IN1
uoccl_n105_0_data_master_qualified_request_onchip_ram_s1 => i25.IN1
uoccl_n105_0_data_master_read => i9.IN0
uoccl_n105_0_data_master_read => i26.IN0
uoccl_n105_0_data_master_read => i25.IN0
uoccl_n105_0_data_master_read => i6.IN1
uoccl_n105_0_data_master_read_data_valid_onchip_ram_s1 => i19.IN1
uoccl_n105_0_data_master_read_data_valid_onchip_ram_s1 => i26.IN1
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave => i62.IN0
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave => i63.IN0
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave => i64.IN0
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave => i65.IN0
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave => i66.IN0
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave => i67.IN0
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave => i68.IN0
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave => i69.IN0
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave => i95.IN0
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave => i96.IN0
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave => i97.IN0
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave => i98.IN0
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave => i99.IN0
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave => i100.IN0
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave => i101.IN0
uoccl_n105_0_data_master_requests_lcd_16207_0_control_slave => i102.IN0
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i71.IN0
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i72.IN0
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i73.IN0
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i74.IN0
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i75.IN0
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i76.IN0
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i77.IN0
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i78.IN0
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i79.IN0
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i80.IN0
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i81.IN0
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i82.IN0
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i83.IN0
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i84.IN0
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i85.IN0
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i86.IN1
uoccl_n105_0_data_master_requests_onchip_ram_s1 => i21.IN0
uoccl_n105_0_data_master_write => i16.IN1
uoccl_n105_0_data_master_write => i32.IN0
uoccl_n105_0_data_master_write => i31.IN0
uoccl_n105_0_data_master_write => i13.IN1
uoccl_n105_0_data_master_address_to_slave[0] <= uoccl_n105_0_data_master_address[0].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_address_to_slave[1] <= uoccl_n105_0_data_master_address[1].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_address_to_slave[2] <= uoccl_n105_0_data_master_address[2].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_address_to_slave[3] <= uoccl_n105_0_data_master_address[3].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_address_to_slave[4] <= uoccl_n105_0_data_master_address[4].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_address_to_slave[5] <= uoccl_n105_0_data_master_address[5].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_address_to_slave[6] <= uoccl_n105_0_data_master_address[6].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_address_to_slave[7] <= uoccl_n105_0_data_master_address[7].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_address_to_slave[8] <= uoccl_n105_0_data_master_address[8].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_address_to_slave[9] <= uoccl_n105_0_data_master_address[9].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_address_to_slave[10] <= uoccl_n105_0_data_master_address[10].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_address_to_slave[11] <= <GND>
uoccl_n105_0_data_master_address_to_slave[12] <= <GND>
uoccl_n105_0_data_master_address_to_slave[13] <= <GND>
uoccl_n105_0_data_master_address_to_slave[14] <= <GND>
uoccl_n105_0_data_master_address_to_slave[15] <= uoccl_n105_0_data_master_address[15].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_readdata[0] <= i87.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_readdata[1] <= i88.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_readdata[2] <= i89.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_readdata[3] <= i90.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_readdata[4] <= i91.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_readdata[5] <= i92.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_readdata[6] <= i93.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_readdata[7] <= i94.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_readdata[8] <= i95.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_readdata[9] <= i96.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_readdata[10] <= i97.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_readdata[11] <= i98.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_readdata[12] <= i99.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_readdata[13] <= i100.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_readdata[14] <= i101.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_readdata[15] <= i102.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_data_master_waitrequest <= i33.DB_MAX_OUTPUT_PORT_TYPE


|N105_system|N_105_system:inst|uoccl_n105_0_instruction_master_arbitrator:the_uoccl_n105_0_instruction_master
d2_reset_n => uoccl_n105_0_instruction_master_reset.DATAIN
onchip_rom_s1_readdata_from_sa[0] => i35.IN1
onchip_rom_s1_readdata_from_sa[1] => i36.IN1
onchip_rom_s1_readdata_from_sa[2] => i37.IN1
onchip_rom_s1_readdata_from_sa[3] => i38.IN1
onchip_rom_s1_readdata_from_sa[4] => i39.IN1
onchip_rom_s1_readdata_from_sa[5] => i40.IN1
onchip_rom_s1_readdata_from_sa[6] => i41.IN1
onchip_rom_s1_readdata_from_sa[7] => i42.IN1
onchip_rom_s1_readdata_from_sa[8] => i43.IN1
onchip_rom_s1_readdata_from_sa[9] => i44.IN1
onchip_rom_s1_readdata_from_sa[10] => i45.IN1
onchip_rom_s1_readdata_from_sa[11] => i46.IN1
onchip_rom_s1_readdata_from_sa[12] => i47.IN1
onchip_rom_s1_readdata_from_sa[13] => i48.IN1
onchip_rom_s1_readdata_from_sa[14] => i49.IN1
onchip_rom_s1_readdata_from_sa[15] => i50.IN0
uoccl_n105_0_instruction_master_address[0] => uoccl_n105_0_instruction_master_address_to_slave[0].DATAIN
uoccl_n105_0_instruction_master_address[1] => uoccl_n105_0_instruction_master_address_to_slave[1].DATAIN
uoccl_n105_0_instruction_master_address[2] => uoccl_n105_0_instruction_master_address_to_slave[2].DATAIN
uoccl_n105_0_instruction_master_address[3] => uoccl_n105_0_instruction_master_address_to_slave[3].DATAIN
uoccl_n105_0_instruction_master_address[4] => uoccl_n105_0_instruction_master_address_to_slave[4].DATAIN
uoccl_n105_0_instruction_master_address[5] => uoccl_n105_0_instruction_master_address_to_slave[5].DATAIN
uoccl_n105_0_instruction_master_address[6] => uoccl_n105_0_instruction_master_address_to_slave[6].DATAIN
uoccl_n105_0_instruction_master_address[7] => uoccl_n105_0_instruction_master_address_to_slave[7].DATAIN
uoccl_n105_0_instruction_master_address[8] => uoccl_n105_0_instruction_master_address_to_slave[8].DATAIN
uoccl_n105_0_instruction_master_address[9] => uoccl_n105_0_instruction_master_address_to_slave[9].DATAIN
uoccl_n105_0_instruction_master_address[10] => uoccl_n105_0_instruction_master_address_to_slave[10].DATAIN
uoccl_n105_0_instruction_master_qualified_request_onchip_rom_s1 => i4.IN0
uoccl_n105_0_instruction_master_qualified_request_onchip_rom_s1 => i9.IN0
uoccl_n105_0_instruction_master_read => i10.IN1
uoccl_n105_0_instruction_master_read => i9.IN1
uoccl_n105_0_instruction_master_read_data_valid_onchip_rom_s1 => i4.IN1
uoccl_n105_0_instruction_master_read_data_valid_onchip_rom_s1 => i10.IN0
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i35.IN0
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i36.IN0
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i37.IN0
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i38.IN0
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i39.IN0
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i40.IN0
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i41.IN0
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i42.IN0
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i43.IN0
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i44.IN0
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i45.IN0
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i46.IN0
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i47.IN0
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i48.IN0
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i49.IN0
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i50.IN1
uoccl_n105_0_instruction_master_requests_onchip_rom_s1 => i6.IN0
uoccl_n105_0_instruction_master_address_to_slave[0] <= uoccl_n105_0_instruction_master_address[0].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_address_to_slave[1] <= uoccl_n105_0_instruction_master_address[1].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_address_to_slave[2] <= uoccl_n105_0_instruction_master_address[2].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_address_to_slave[3] <= uoccl_n105_0_instruction_master_address[3].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_address_to_slave[4] <= uoccl_n105_0_instruction_master_address[4].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_address_to_slave[5] <= uoccl_n105_0_instruction_master_address[5].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_address_to_slave[6] <= uoccl_n105_0_instruction_master_address[6].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_address_to_slave[7] <= uoccl_n105_0_instruction_master_address[7].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_address_to_slave[8] <= uoccl_n105_0_instruction_master_address[8].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_address_to_slave[9] <= uoccl_n105_0_instruction_master_address[9].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_address_to_slave[10] <= uoccl_n105_0_instruction_master_address[10].DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_address_to_slave[11] <= <GND>
uoccl_n105_0_instruction_master_address_to_slave[12] <= <GND>
uoccl_n105_0_instruction_master_address_to_slave[13] <= <GND>
uoccl_n105_0_instruction_master_address_to_slave[14] <= <GND>
uoccl_n105_0_instruction_master_address_to_slave[15] <= <GND>
uoccl_n105_0_instruction_master_readdata[0] <= i35.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_readdata[1] <= i36.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_readdata[2] <= i37.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_readdata[3] <= i38.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_readdata[4] <= i39.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_readdata[5] <= i40.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_readdata[6] <= i41.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_readdata[7] <= i42.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_readdata[8] <= i43.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_readdata[9] <= i44.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_readdata[10] <= i45.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_readdata[11] <= i46.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_readdata[12] <= i47.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_readdata[13] <= i48.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_readdata[14] <= i49.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_readdata[15] <= i50.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_reset <= d2_reset_n.DB_MAX_OUTPUT_PORT_TYPE
uoccl_n105_0_instruction_master_waitrequest <= i12.DB_MAX_OUTPUT_PORT_TYPE


|N105_system|N_105_system:inst|uoccl_n105_0:the_uoccl_n105_0
clk => clk~0.IN1
readdata_instr_fetch[0] => readdata_instr_fetch[0]~15.IN1
readdata_instr_fetch[1] => readdata_instr_fetch[1]~14.IN1
readdata_instr_fetch[2] => readdata_instr_fetch[2]~13.IN1
readdata_instr_fetch[3] => readdata_instr_fetch[3]~12.IN1
readdata_instr_fetch[4] => readdata_instr_fetch[4]~11.IN1
readdata_instr_fetch[5] => readdata_instr_fetch[5]~10.IN1
readdata_instr_fetch[6] => readdata_instr_fetch[6]~9.IN1
readdata_instr_fetch[7] => readdata_instr_fetch[7]~8.IN1
readdata_instr_fetch[8] => readdata_instr_fetch[8]~7.IN1
readdata_instr_fetch[9] => readdata_instr_fetch[9]~6.IN1
readdata_instr_fetch[10] => readdata_instr_fetch[10]~5.IN1
readdata_instr_fetch[11] => readdata_instr_fetch[11]~4.IN1
readdata_instr_fetch[12] => readdata_instr_fetch[12]~3.IN1
readdata_instr_fetch[13] => readdata_instr_fetch[13]~2.IN1
readdata_instr_fetch[14] => readdata_instr_fetch[14]~1.IN1
readdata_instr_fetch[15] => readdata_instr_fetch[15]~0.IN1
readdata_mem_access[0] => readdata_mem_access[0]~15.IN1
readdata_mem_access[1] => readdata_mem_access[1]~14.IN1
readdata_mem_access[2] => readdata_mem_access[2]~13.IN1
readdata_mem_access[3] => readdata_mem_access[3]~12.IN1
readdata_mem_access[4] => readdata_mem_access[4]~11.IN1
readdata_mem_access[5] => readdata_mem_access[5]~10.IN1
readdata_mem_access[6] => readdata_mem_access[6]~9.IN1
readdata_mem_access[7] => readdata_mem_access[7]~8.IN1
readdata_mem_access[8] => readdata_mem_access[8]~7.IN1
readdata_mem_access[9] => readdata_mem_access[9]~6.IN1
readdata_mem_access[10] => readdata_mem_access[10]~5.IN1
readdata_mem_access[11] => readdata_mem_access[11]~4.IN1
readdata_mem_access[12] => readdata_mem_access[12]~3.IN1
readdata_mem_access[13] => readdata_mem_access[13]~2.IN1
readdata_mem_access[14] => readdata_mem_access[14]~1.IN1
readdata_mem_access[15] => readdata_mem_access[15]~0.IN1
reset => reset~0.IN1
waitrequest_instr_fetch => waitrequest_instr_fetch~0.IN1
waitrequest_mem_access => waitrequest_mem_access~0.IN1
address_instr_fetch[0] <= cpu:the_cpu.address_instr_fetch
address_instr_fetch[1] <= cpu:the_cpu.address_instr_fetch
address_instr_fetch[2] <= cpu:the_cpu.address_instr_fetch
address_instr_fetch[3] <= cpu:the_cpu.address_instr_fetch
address_instr_fetch[4] <= cpu:the_cpu.address_instr_fetch
address_instr_fetch[5] <= cpu:the_cpu.address_instr_fetch
address_instr_fetch[6] <= cpu:the_cpu.address_instr_fetch
address_instr_fetch[7] <= cpu:the_cpu.address_instr_fetch
address_instr_fetch[8] <= cpu:the_cpu.address_instr_fetch
address_instr_fetch[9] <= cpu:the_cpu.address_instr_fetch
address_instr_fetch[10] <= cpu:the_cpu.address_instr_fetch
address_instr_fetch[11] <= cpu:the_cpu.address_instr_fetch
address_instr_fetch[12] <= cpu:the_cpu.address_instr_fetch
address_instr_fetch[13] <= cpu:the_cpu.address_instr_fetch
address_instr_fetch[14] <= cpu:the_cpu.address_instr_fetch
address_instr_fetch[15] <= cpu:the_cpu.address_instr_fetch
address_mem_access[0] <= cpu:the_cpu.address_mem_access
address_mem_access[1] <= cpu:the_cpu.address_mem_access
address_mem_access[2] <= cpu:the_cpu.address_mem_access
address_mem_access[3] <= cpu:the_cpu.address_mem_access
address_mem_access[4] <= cpu:the_cpu.address_mem_access
address_mem_access[5] <= cpu:the_cpu.address_mem_access
address_mem_access[6] <= cpu:the_cpu.address_mem_access
address_mem_access[7] <= cpu:the_cpu.address_mem_access
address_mem_access[8] <= cpu:the_cpu.address_mem_access
address_mem_access[9] <= cpu:the_cpu.address_mem_access
address_mem_access[10] <= cpu:the_cpu.address_mem_access
address_mem_access[11] <= cpu:the_cpu.address_mem_access
address_mem_access[12] <= cpu:the_cpu.address_mem_access
address_mem_access[13] <= cpu:the_cpu.address_mem_access
address_mem_access[14] <= cpu:the_cpu.address_mem_access
address_mem_access[15] <= cpu:the_cpu.address_mem_access
byteenable_instr_fetch[0] <= cpu:the_cpu.byteenable_instr_fetch
byteenable_instr_fetch[1] <= cpu:the_cpu.byteenable_instr_fetch
byteenable_instr_fetch[2] <= cpu:the_cpu.byteenable_instr_fetch
byteenable_instr_fetch[3] <= cpu:the_cpu.byteenable_instr_fetch
byteenable_mem_access[0] <= cpu:the_cpu.byteenable_mem_access
byteenable_mem_access[1] <= cpu:the_cpu.byteenable_mem_access
byteenable_mem_access[2] <= cpu:the_cpu.byteenable_mem_access
byteenable_mem_access[3] <= cpu:the_cpu.byteenable_mem_access
read_instr_fetch <= cpu:the_cpu.read_instr_fetch
read_mem_access <= cpu:the_cpu.read_mem_access
write_mem_access <= cpu:the_cpu.write_mem_access
writedata_mem_access[0] <= cpu:the_cpu.writedata_mem_access
writedata_mem_access[1] <= cpu:the_cpu.writedata_mem_access
writedata_mem_access[2] <= cpu:the_cpu.writedata_mem_access
writedata_mem_access[3] <= cpu:the_cpu.writedata_mem_access
writedata_mem_access[4] <= cpu:the_cpu.writedata_mem_access
writedata_mem_access[5] <= cpu:the_cpu.writedata_mem_access
writedata_mem_access[6] <= cpu:the_cpu.writedata_mem_access
writedata_mem_access[7] <= cpu:the_cpu.writedata_mem_access
writedata_mem_access[8] <= cpu:the_cpu.writedata_mem_access
writedata_mem_access[9] <= cpu:the_cpu.writedata_mem_access
writedata_mem_access[10] <= cpu:the_cpu.writedata_mem_access
writedata_mem_access[11] <= cpu:the_cpu.writedata_mem_access
writedata_mem_access[12] <= cpu:the_cpu.writedata_mem_access
writedata_mem_access[13] <= cpu:the_cpu.writedata_mem_access
writedata_mem_access[14] <= cpu:the_cpu.writedata_mem_access
writedata_mem_access[15] <= cpu:the_cpu.writedata_mem_access


|N105_system|N_105_system:inst|uoccl_n105_0:the_uoccl_n105_0|cpu:the_cpu
clk => clk~0.IN5
reset => reset~0.IN4
waitrequest_mem_access => waitrequest_mem_access~0.IN1
address_mem_access[0] <= mem_access_unit:the_mem_access_unit.address
address_mem_access[1] <= mem_access_unit:the_mem_access_unit.address
address_mem_access[2] <= mem_access_unit:the_mem_access_unit.address
address_mem_access[3] <= mem_access_unit:the_mem_access_unit.address
address_mem_access[4] <= mem_access_unit:the_mem_access_unit.address
address_mem_access[5] <= mem_access_unit:the_mem_access_unit.address
address_mem_access[6] <= mem_access_unit:the_mem_access_unit.address
address_mem_access[7] <= mem_access_unit:the_mem_access_unit.address
address_mem_access[8] <= mem_access_unit:the_mem_access_unit.address
address_mem_access[9] <= mem_access_unit:the_mem_access_unit.address
address_mem_access[10] <= mem_access_unit:the_mem_access_unit.address
address_mem_access[11] <= mem_access_unit:the_mem_access_unit.address
address_mem_access[12] <= mem_access_unit:the_mem_access_unit.address
address_mem_access[13] <= mem_access_unit:the_mem_access_unit.address
address_mem_access[14] <= mem_access_unit:the_mem_access_unit.address
address_mem_access[15] <= mem_access_unit:the_mem_access_unit.address
byteenable_mem_access[0] <= mem_access_unit:the_mem_access_unit.byteenable
byteenable_mem_access[1] <= mem_access_unit:the_mem_access_unit.byteenable
byteenable_mem_access[2] <= mem_access_unit:the_mem_access_unit.byteenable
byteenable_mem_access[3] <= mem_access_unit:the_mem_access_unit.byteenable
read_mem_access <= mem_access_unit:the_mem_access_unit.read
readdata_mem_access[0] => readdata_mem_access[0]~15.IN1
readdata_mem_access[1] => readdata_mem_access[1]~14.IN1
readdata_mem_access[2] => readdata_mem_access[2]~13.IN1
readdata_mem_access[3] => readdata_mem_access[3]~12.IN1
readdata_mem_access[4] => readdata_mem_access[4]~11.IN1
readdata_mem_access[5] => readdata_mem_access[5]~10.IN1
readdata_mem_access[6] => readdata_mem_access[6]~9.IN1
readdata_mem_access[7] => readdata_mem_access[7]~8.IN1
readdata_mem_access[8] => readdata_mem_access[8]~7.IN1
readdata_mem_access[9] => readdata_mem_access[9]~6.IN1
readdata_mem_access[10] => readdata_mem_access[10]~5.IN1
readdata_mem_access[11] => readdata_mem_access[11]~4.IN1
readdata_mem_access[12] => readdata_mem_access[12]~3.IN1
readdata_mem_access[13] => readdata_mem_access[13]~2.IN1
readdata_mem_access[14] => readdata_mem_access[14]~1.IN1
readdata_mem_access[15] => readdata_mem_access[15]~0.IN1
write_mem_access <= mem_access_unit:the_mem_access_unit.write
writedata_mem_access[0] <= mem_access_unit:the_mem_access_unit.writedata
writedata_mem_access[1] <= mem_access_unit:the_mem_access_unit.writedata
writedata_mem_access[2] <= mem_access_unit:the_mem_access_unit.writedata
writedata_mem_access[3] <= mem_access_unit:the_mem_access_unit.writedata
writedata_mem_access[4] <= mem_access_unit:the_mem_access_unit.writedata
writedata_mem_access[5] <= mem_access_unit:the_mem_access_unit.writedata
writedata_mem_access[6] <= mem_access_unit:the_mem_access_unit.writedata
writedata_mem_access[7] <= mem_access_unit:the_mem_access_unit.writedata
writedata_mem_access[8] <= mem_access_unit:the_mem_access_unit.writedata
writedata_mem_access[9] <= mem_access_unit:the_mem_access_unit.writedata
writedata_mem_access[10] <= mem_access_unit:the_mem_access_unit.writedata
writedata_mem_access[11] <= mem_access_unit:the_mem_access_unit.writedata
writedata_mem_access[12] <= mem_access_unit:the_mem_access_unit.writedata
writedata_mem_access[13] <= mem_access_unit:the_mem_access_unit.writedata
writedata_mem_access[14] <= mem_access_unit:the_mem_access_unit.writedata
writedata_mem_access[15] <= mem_access_unit:the_mem_access_unit.writedata
waitrequest_instr_fetch => waitrequest_instr_fetch~0.IN1
address_instr_fetch[0] <= instruction_fetch:the_instruction_fetch.address
address_instr_fetch[1] <= instruction_fetch:the_instruction_fetch.address
address_instr_fetch[2] <= instruction_fetch:the_instruction_fetch.address
address_instr_fetch[3] <= instruction_fetch:the_instruction_fetch.address
address_instr_fetch[4] <= instruction_fetch:the_instruction_fetch.address
address_instr_fetch[5] <= instruction_fetch:the_instruction_fetch.address
address_instr_fetch[6] <= instruction_fetch:the_instruction_fetch.address
address_instr_fetch[7] <= instruction_fetch:the_instruction_fetch.address
address_instr_fetch[8] <= instruction_fetch:the_instruction_fetch.address
address_instr_fetch[9] <= instruction_fetch:the_instruction_fetch.address
address_instr_fetch[10] <= instruction_fetch:the_instruction_fetch.address
address_instr_fetch[11] <= instruction_fetch:the_instruction_fetch.address
address_instr_fetch[12] <= instruction_fetch:the_instruction_fetch.address
address_instr_fetch[13] <= instruction_fetch:the_instruction_fetch.address
address_instr_fetch[14] <= instruction_fetch:the_instruction_fetch.address
address_instr_fetch[15] <= instruction_fetch:the_instruction_fetch.address
byteenable_instr_fetch[0] <= instruction_fetch:the_instruction_fetch.byteenable
byteenable_instr_fetch[1] <= instruction_fetch:the_instruction_fetch.byteenable
byteenable_instr_fetch[2] <= instruction_fetch:the_instruction_fetch.byteenable
byteenable_instr_fetch[3] <= instruction_fetch:the_instruction_fetch.byteenable
read_instr_fetch <= instruction_fetch:the_instruction_fetch.read
readdata_instr_fetch[0] => readdata_instr_fetch[0]~15.IN1
readdata_instr_fetch[1] => readdata_instr_fetch[1]~14.IN1
readdata_instr_fetch[2] => readdata_instr_fetch[2]~13.IN1
readdata_instr_fetch[3] => readdata_instr_fetch[3]~12.IN1
readdata_instr_fetch[4] => readdata_instr_fetch[4]~11.IN1
readdata_instr_fetch[5] => readdata_instr_fetch[5]~10.IN1
readdata_instr_fetch[6] => readdata_instr_fetch[6]~9.IN1
readdata_instr_fetch[7] => readdata_instr_fetch[7]~8.IN1
readdata_instr_fetch[8] => readdata_instr_fetch[8]~7.IN1
readdata_instr_fetch[9] => readdata_instr_fetch[9]~6.IN1
readdata_instr_fetch[10] => readdata_instr_fetch[10]~5.IN1
readdata_instr_fetch[11] => readdata_instr_fetch[11]~4.IN1
readdata_instr_fetch[12] => readdata_instr_fetch[12]~3.IN1
readdata_instr_fetch[13] => readdata_instr_fetch[13]~2.IN1
readdata_instr_fetch[14] => readdata_instr_fetch[14]~1.IN1
readdata_instr_fetch[15] => readdata_instr_fetch[15]~0.IN1


|N105_system|N_105_system:inst|uoccl_n105_0:the_uoccl_n105_0|cpu:the_cpu|instruction_fetch:the_instruction_fetch
pc[0] => address[0].DATAIN
pc[1] => address[1].DATAIN
pc[2] => address[2].DATAIN
pc[3] => address[3].DATAIN
pc[4] => address[4].DATAIN
pc[5] => address[5].DATAIN
pc[6] => address[6].DATAIN
pc[7] => address[7].DATAIN
pc[8] => address[8].DATAIN
pc[9] => address[9].DATAIN
pc[10] => address[10].DATAIN
pc[11] => address[11].DATAIN
pc[12] => address[12].DATAIN
pc[13] => address[13].DATAIN
pc[14] => address[14].DATAIN
pc[15] => address[15].DATAIN
next_instruction[0] <= readdata[0].DB_MAX_OUTPUT_PORT_TYPE
next_instruction[1] <= readdata[1].DB_MAX_OUTPUT_PORT_TYPE
next_instruction[2] <= readdata[2].DB_MAX_OUTPUT_PORT_TYPE
next_instruction[3] <= readdata[3].DB_MAX_OUTPUT_PORT_TYPE
next_instruction[4] <= readdata[4].DB_MAX_OUTPUT_PORT_TYPE
next_instruction[5] <= readdata[5].DB_MAX_OUTPUT_PORT_TYPE
next_instruction[6] <= readdata[6].DB_MAX_OUTPUT_PORT_TYPE
next_instruction[7] <= readdata[7].DB_MAX_OUTPUT_PORT_TYPE
next_instruction[8] <= readdata[8].DB_MAX_OUTPUT_PORT_TYPE
next_instruction[9] <= readdata[9].DB_MAX_OUTPUT_PORT_TYPE
next_instruction[10] <= readdata[10].DB_MAX_OUTPUT_PORT_TYPE
next_instruction[11] <= readdata[11].DB_MAX_OUTPUT_PORT_TYPE
next_instruction[12] <= readdata[12].DB_MAX_OUTPUT_PORT_TYPE
next_instruction[13] <= readdata[13].DB_MAX_OUTPUT_PORT_TYPE
next_instruction[14] <= readdata[14].DB_MAX_OUTPUT_PORT_TYPE
next_instruction[15] <= readdata[15].DB_MAX_OUTPUT_PORT_TYPE
instruction_ready <= waitrequest.DB_MAX_OUTPUT_PORT_TYPE
waitrequest => instruction_ready.DATAIN
readdata[0] => next_instruction[0].DATAIN
readdata[1] => next_instruction[1].DATAIN
readdata[2] => next_instruction[2].DATAIN
readdata[3] => next_instruction[3].DATAIN
readdata[4] => next_instruction[4].DATAIN
readdata[5] => next_instruction[5].DATAIN
readdata[6] => next_instruction[6].DATAIN
readdata[7] => next_instruction[7].DATAIN
readdata[8] => next_instruction[8].DATAIN
readdata[9] => next_instruction[9].DATAIN
readdata[10] => next_instruction[10].DATAIN
readdata[11] => next_instruction[11].DATAIN
readdata[12] => next_instruction[12].DATAIN
readdata[13] => next_instruction[13].DATAIN
readdata[14] => next_instruction[14].DATAIN
readdata[15] => next_instruction[15].DATAIN
address[0] <= pc[0].DB_MAX_OUTPUT_PORT_TYPE
address[1] <= pc[1].DB_MAX_OUTPUT_PORT_TYPE
address[2] <= pc[2].DB_MAX_OUTPUT_PORT_TYPE
address[3] <= pc[3].DB_MAX_OUTPUT_PORT_TYPE
address[4] <= pc[4].DB_MAX_OUTPUT_PORT_TYPE
address[5] <= pc[5].DB_MAX_OUTPUT_PORT_TYPE
address[6] <= pc[6].DB_MAX_OUTPUT_PORT_TYPE
address[7] <= pc[7].DB_MAX_OUTPUT_PORT_TYPE
address[8] <= pc[8].DB_MAX_OUTPUT_PORT_TYPE
address[9] <= pc[9].DB_MAX_OUTPUT_PORT_TYPE
address[10] <= pc[10].DB_MAX_OUTPUT_PORT_TYPE
address[11] <= pc[11].DB_MAX_OUTPUT_PORT_TYPE
address[12] <= pc[12].DB_MAX_OUTPUT_PORT_TYPE
address[13] <= pc[13].DB_MAX_OUTPUT_PORT_TYPE
address[14] <= pc[14].DB_MAX_OUTPUT_PORT_TYPE
address[15] <= pc[15].DB_MAX_OUTPUT_PORT_TYPE
byteenable[0] <= <VCC>
byteenable[1] <= <VCC>
byteenable[2] <= <GND>
byteenable[3] <= <GND>
read <= <VCC>


|N105_system|N_105_system:inst|uoccl_n105_0:the_uoccl_n105_0|cpu:the_cpu|instruction_decode:the_instruction_decode
clk => instruction[14].CLK
clk => instruction[13].CLK
clk => instruction[12].CLK
clk => instruction[11].CLK
clk => instruction[10].CLK
clk => instruction[9].CLK
clk => instruction[8].CLK
clk => instruction[7].CLK
clk => instruction[6].CLK
clk => instruction[5].CLK
clk => instruction[4].CLK
clk => instruction[3].CLK
clk => instruction[2].CLK
clk => instruction[1].CLK
clk => instruction[0].CLK
clk => skip.CLK
clk => instruction[15].CLK
reset => i20.OUTPUTSELECT
reset => i21.OUTPUTSELECT
reset => i22.OUTPUTSELECT
reset => i23.OUTPUTSELECT
reset => i24.OUTPUTSELECT
reset => i25.OUTPUTSELECT
reset => i26.OUTPUTSELECT
reset => i27.OUTPUTSELECT
reset => i28.OUTPUTSELECT
reset => i29.OUTPUTSELECT
reset => i30.OUTPUTSELECT
reset => i31.OUTPUTSELECT
reset => i32.OUTPUTSELECT
reset => i33.OUTPUTSELECT
reset => i34.OUTPUTSELECT
reset => i35.OUTPUTSELECT
reset => i187.OUTPUTSELECT
advance_pipeline => i4.OUTPUTSELECT
advance_pipeline => i5.OUTPUTSELECT
advance_pipeline => i6.OUTPUTSELECT
advance_pipeline => i7.OUTPUTSELECT
advance_pipeline => i8.OUTPUTSELECT
advance_pipeline => i9.OUTPUTSELECT
advance_pipeline => i10.OUTPUTSELECT
advance_pipeline => i11.OUTPUTSELECT
advance_pipeline => i12.OUTPUTSELECT
advance_pipeline => i13.OUTPUTSELECT
advance_pipeline => i14.OUTPUTSELECT
advance_pipeline => i15.OUTPUTSELECT
advance_pipeline => i16.OUTPUTSELECT
advance_pipeline => i17.OUTPUTSELECT
advance_pipeline => i18.OUTPUTSELECT
advance_pipeline => i19.OUTPUTSELECT
advance_pipeline => i185.OUTPUTSELECT
ld_st_coming <= i63.DB_MAX_OUTPUT_PORT_TYPE
next_instruction[0] => i19.DATAB
next_instruction[1] => i18.DATAB
next_instruction[2] => i17.DATAB
next_instruction[3] => i16.DATAB
next_instruction[3] => i~1.IN1
next_instruction[4] => i15.DATAB
next_instruction[4] => i~1.IN0
next_instruction[5] => i14.DATAB
next_instruction[6] => i13.DATAB
next_instruction[7] => i12.DATAB
next_instruction[8] => i11.DATAB
next_instruction[9] => i10.DATAB
next_instruction[10] => i9.DATAB
next_instruction[11] => i8.DATAB
next_instruction[12] => i7.DATAB
next_instruction[13] => i6.DATAB
next_instruction[14] => i5.DATAB
next_instruction[15] => i4.DATAB
condition_flags[0] => i169.IN1
condition_flags[0] => i176.DATAB
condition_flags[1] => i162.IN0
condition_flags[1] => i169.IN0
condition_flags[1] => i175.DATAB
condition_flags[2] => i161.IN0
condition_flags[2] => i171.DATAB
condition_flags[3] => i161.IN1
condition_flags[3] => i174.DATAB
set_cond_en <= i118.DB_MAX_OUTPUT_PORT_TYPE
alu_opcode[0] <= instruction[0].DB_MAX_OUTPUT_PORT_TYPE
alu_opcode[1] <= instruction[1].DB_MAX_OUTPUT_PORT_TYPE
alu_opcode[2] <= instruction[2].DB_MAX_OUTPUT_PORT_TYPE
alu_opcode[3] <= instruction[3].DB_MAX_OUTPUT_PORT_TYPE
imm7[0] <= instruction[5].DB_MAX_OUTPUT_PORT_TYPE
imm7[1] <= instruction[6].DB_MAX_OUTPUT_PORT_TYPE
imm7[2] <= instruction[7].DB_MAX_OUTPUT_PORT_TYPE
imm7[3] <= instruction[8].DB_MAX_OUTPUT_PORT_TYPE
imm7[4] <= instruction[9].DB_MAX_OUTPUT_PORT_TYPE
imm7[5] <= instruction[10].DB_MAX_OUTPUT_PORT_TYPE
imm7[6] <= instruction[11].DB_MAX_OUTPUT_PORT_TYPE
imm11[0] <= instruction[5].DB_MAX_OUTPUT_PORT_TYPE
imm11[1] <= instruction[6].DB_MAX_OUTPUT_PORT_TYPE
imm11[2] <= instruction[7].DB_MAX_OUTPUT_PORT_TYPE
imm11[3] <= instruction[8].DB_MAX_OUTPUT_PORT_TYPE
imm11[4] <= instruction[9].DB_MAX_OUTPUT_PORT_TYPE
imm11[5] <= instruction[10].DB_MAX_OUTPUT_PORT_TYPE
imm11[6] <= instruction[11].DB_MAX_OUTPUT_PORT_TYPE
imm11[7] <= instruction[12].DB_MAX_OUTPUT_PORT_TYPE
imm11[8] <= instruction[13].DB_MAX_OUTPUT_PORT_TYPE
imm11[9] <= instruction[14].DB_MAX_OUTPUT_PORT_TYPE
imm11[10] <= instruction[15].DB_MAX_OUTPUT_PORT_TYPE
index_a[0] <= instruction[12].DB_MAX_OUTPUT_PORT_TYPE
index_a[1] <= instruction[13].DB_MAX_OUTPUT_PORT_TYPE
index_a[2] <= instruction[14].DB_MAX_OUTPUT_PORT_TYPE
index_a[3] <= instruction[15].DB_MAX_OUTPUT_PORT_TYPE
index_b[0] <= instruction[8].DB_MAX_OUTPUT_PORT_TYPE
index_b[1] <= instruction[9].DB_MAX_OUTPUT_PORT_TYPE
index_b[2] <= instruction[10].DB_MAX_OUTPUT_PORT_TYPE
index_b[3] <= instruction[11].DB_MAX_OUTPUT_PORT_TYPE
alu_en <= i127.DB_MAX_OUTPUT_PORT_TYPE
br_unit_en <= i132.DB_MAX_OUTPUT_PORT_TYPE
load_n_store <= i136.DB_MAX_OUTPUT_PORT_TYPE
return_en <= i142.DB_MAX_OUTPUT_PORT_TYPE
bsr_en <= i148.DB_MAX_OUTPUT_PORT_TYPE


|N105_system|N_105_system:inst|uoccl_n105_0:the_uoccl_n105_0|cpu:the_cpu|mem_access_unit:the_mem_access_unit
clk => read~reg0.CLK
clk => write~reg0.CLK
clk => mem_is_busy~reg0.CLK
reset => i62.OUTPUTSELECT
load_n_store => i63.IN1
load_n_store => i65.IN1
contents_a[0] => writedata[0].DATAIN
contents_a[1] => writedata[1].DATAIN
contents_a[2] => writedata[2].DATAIN
contents_a[3] => writedata[3].DATAIN
contents_a[4] => writedata[4].DATAIN
contents_a[5] => writedata[5].DATAIN
contents_a[6] => writedata[6].DATAIN
contents_a[7] => writedata[7].DATAIN
contents_a[8] => writedata[8].DATAIN
contents_a[9] => writedata[9].DATAIN
contents_a[10] => writedata[10].DATAIN
contents_a[11] => writedata[11].DATAIN
contents_a[12] => writedata[12].DATAIN
contents_a[13] => writedata[13].DATAIN
contents_a[14] => writedata[14].DATAIN
contents_a[15] => writedata[15].DATAIN
contents_b[0] => address[0].DATAIN
contents_b[1] => address[1].DATAIN
contents_b[2] => address[2].DATAIN
contents_b[3] => address[3].DATAIN
contents_b[4] => address[4].DATAIN
contents_b[5] => address[5].DATAIN
contents_b[6] => address[6].DATAIN
contents_b[7] => address[7].DATAIN
contents_b[8] => address[8].DATAIN
contents_b[9] => address[9].DATAIN
contents_b[10] => address[10].DATAIN
contents_b[11] => address[11].DATAIN
contents_b[12] => address[12].DATAIN
contents_b[13] => address[13].DATAIN
contents_b[14] => address[14].DATAIN
contents_b[15] => address[15].DATAIN
ld_st_coming => i56.IN0
advance_pipeline => i56.IN1
load_result[0] <= readdata[0].DB_MAX_OUTPUT_PORT_TYPE
load_result[1] <= readdata[1].DB_MAX_OUTPUT_PORT_TYPE
load_result[2] <= readdata[2].DB_MAX_OUTPUT_PORT_TYPE
load_result[3] <= readdata[3].DB_MAX_OUTPUT_PORT_TYPE
load_result[4] <= readdata[4].DB_MAX_OUTPUT_PORT_TYPE
load_result[5] <= readdata[5].DB_MAX_OUTPUT_PORT_TYPE
load_result[6] <= readdata[6].DB_MAX_OUTPUT_PORT_TYPE
load_result[7] <= readdata[7].DB_MAX_OUTPUT_PORT_TYPE
load_result[8] <= readdata[8].DB_MAX_OUTPUT_PORT_TYPE
load_result[9] <= readdata[9].DB_MAX_OUTPUT_PORT_TYPE
load_result[10] <= readdata[10].DB_MAX_OUTPUT_PORT_TYPE
load_result[11] <= readdata[11].DB_MAX_OUTPUT_PORT_TYPE
load_result[12] <= readdata[12].DB_MAX_OUTPUT_PORT_TYPE
load_result[13] <= readdata[13].DB_MAX_OUTPUT_PORT_TYPE
load_result[14] <= readdata[14].DB_MAX_OUTPUT_PORT_TYPE
load_result[15] <= readdata[15].DB_MAX_OUTPUT_PORT_TYPE
mem_is_busy <= mem_is_busy~reg0.DB_MAX_OUTPUT_PORT_TYPE
waitrequest => i59.IN1
readdata[0] => load_result[0].DATAIN
readdata[1] => load_result[1].DATAIN
readdata[2] => load_result[2].DATAIN
readdata[3] => load_result[3].DATAIN
readdata[4] => load_result[4].DATAIN
readdata[5] => load_result[5].DATAIN
readdata[6] => load_result[6].DATAIN
readdata[7] => load_result[7].DATAIN
readdata[8] => load_result[8].DATAIN
readdata[9] => load_result[9].DATAIN
readdata[10] => load_result[10].DATAIN
readdata[11] => load_result[11].DATAIN
readdata[12] => load_result[12].DATAIN
readdata[13] => load_result[13].DATAIN
readdata[14] => load_result[14].DATAIN
readdata[15] => load_result[15].DATAIN
address[0] <= contents_b[0].DB_MAX_OUTPUT_PORT_TYPE
address[1] <= contents_b[1].DB_MAX_OUTPUT_PORT_TYPE
address[2] <= contents_b[2].DB_MAX_OUTPUT_PORT_TYPE
address[3] <= contents_b[3].DB_MAX_OUTPUT_PORT_TYPE
address[4] <= contents_b[4].DB_MAX_OUTPUT_PORT_TYPE
address[5] <= contents_b[5].DB_MAX_OUTPUT_PORT_TYPE
address[6] <= contents_b[6].DB_MAX_OUTPUT_PORT_TYPE
address[7] <= contents_b[7].DB_MAX_OUTPUT_PORT_TYPE
address[8] <= contents_b[8].DB_MAX_OUTPUT_PORT_TYPE
address[9] <= contents_b[9].DB_MAX_OUTPUT_PORT_TYPE
address[10] <= contents_b[10].DB_MAX_OUTPUT_PORT_TYPE
address[11] <= contents_b[11].DB_MAX_OUTPUT_PORT_TYPE
address[12] <= contents_b[12].DB_MAX_OUTPUT_PORT_TYPE
address[13] <= contents_b[13].DB_MAX_OUTPUT_PORT_TYPE
address[14] <= contents_b[14].DB_MAX_OUTPUT_PORT_TYPE
address[15] <= contents_b[15].DB_MAX_OUTPUT_PORT_TYPE
byteenable[0] <= <VCC>
byteenable[1] <= <VCC>
byteenable[2] <= <GND>
byteenable[3] <= <GND>
read <= read~reg0.DB_MAX_OUTPUT_PORT_TYPE
write <= write~reg0.DB_MAX_OUTPUT_PORT_TYPE
writedata[0] <= contents_a[0].DB_MAX_OUTPUT_PORT_TYPE
writedata[1] <= contents_a[1].DB_MAX_OUTPUT_PORT_TYPE
writedata[2] <= contents_a[2].DB_MAX_OUTPUT_PORT_TYPE
writedata[3] <= contents_a[3].DB_MAX_OUTPUT_PORT_TYPE
writedata[4] <= contents_a[4].DB_MAX_OUTPUT_PORT_TYPE
writedata[5] <= contents_a[5].DB_MAX_OUTPUT_PORT_TYPE
writedata[6] <= contents_a[6].DB_MAX_OUTPUT_PORT_TYPE
writedata[7] <= contents_a[7].DB_MAX_OUTPUT_PORT_TYPE
writedata[8] <= contents_a[8].DB_MAX_OUTPUT_PORT_TYPE
writedata[9] <= contents_a[9].DB_MAX_OUTPUT_PORT_TYPE
writedata[10] <= contents_a[10].DB_MAX_OUTPUT_PORT_TYPE
writedata[11] <= contents_a[11].DB_MAX_OUTPUT_PORT_TYPE
writedata[12] <= contents_a[12].DB_MAX_OUTPUT_PORT_TYPE
writedata[13] <= contents_a[13].DB_MAX_OUTPUT_PORT_TYPE
writedata[14] <= contents_a[14].DB_MAX_OUTPUT_PORT_TYPE
writedata[15] <= contents_a[15].DB_MAX_OUTPUT_PORT_TYPE


|N105_system|N_105_system:inst|uoccl_n105_0:the_uoccl_n105_0|cpu:the_cpu|alu:the_alu
contents_a[0] => contents_a[0]~15.IN1
contents_a[1] => contents_a[1]~14.IN1
contents_a[2] => contents_a[2]~13.IN1
contents_a[3] => contents_a[3]~12.IN1
contents_a[4] => contents_a[4]~11.IN1
contents_a[5] => contents_a[5]~10.IN1
contents_a[6] => contents_a[6]~9.IN1
contents_a[7] => contents_a[7]~8.IN1
contents_a[8] => contents_a[8]~7.IN1
contents_a[9] => contents_a[9]~6.IN1
contents_a[10] => contents_a[10]~5.IN1
contents_a[11] => contents_a[11]~4.IN1
contents_a[12] => contents_a[12]~3.IN1
contents_a[13] => contents_a[13]~2.IN1
contents_a[14] => contents_a[14]~1.IN1
contents_a[15] => contents_a[15]~0.IN1
contents_b[0] => i41.IN1
contents_b[0] => i59.IN1
contents_b[0] => i77.IN1
contents_b[0] => i~6.IN32
contents_b[0] => i351.DATAB
contents_b[0] => i~9.IN32
contents_b[1] => i42.IN1
contents_b[1] => i60.IN1
contents_b[1] => i78.IN1
contents_b[1] => i~6.IN31
contents_b[1] => i350.DATAB
contents_b[1] => i~9.IN31
contents_b[2] => i43.IN1
contents_b[2] => i61.IN1
contents_b[2] => i79.IN1
contents_b[2] => i~6.IN30
contents_b[2] => i349.DATAB
contents_b[2] => i~9.IN30
contents_b[3] => i44.IN1
contents_b[3] => i62.IN1
contents_b[3] => i80.IN1
contents_b[3] => i~6.IN29
contents_b[3] => i348.DATAB
contents_b[3] => i~9.IN29
contents_b[4] => i45.IN1
contents_b[4] => i63.IN1
contents_b[4] => i81.IN1
contents_b[4] => i~6.IN28
contents_b[4] => i347.DATAB
contents_b[4] => i~9.IN28
contents_b[5] => i46.IN1
contents_b[5] => i64.IN1
contents_b[5] => i82.IN1
contents_b[5] => i~6.IN27
contents_b[5] => i346.DATAB
contents_b[5] => i~9.IN27
contents_b[6] => i47.IN1
contents_b[6] => i65.IN1
contents_b[6] => i83.IN1
contents_b[6] => i~6.IN26
contents_b[6] => i345.DATAB
contents_b[6] => i~9.IN26
contents_b[7] => i48.IN1
contents_b[7] => i66.IN1
contents_b[7] => i84.IN1
contents_b[7] => i~6.IN25
contents_b[7] => i344.DATAB
contents_b[7] => i~9.IN25
contents_b[8] => i49.IN1
contents_b[8] => i67.IN1
contents_b[8] => i85.IN1
contents_b[8] => i~6.IN24
contents_b[8] => i343.DATAB
contents_b[8] => i~9.IN24
contents_b[9] => i50.IN1
contents_b[9] => i68.IN1
contents_b[9] => i86.IN1
contents_b[9] => i~6.IN23
contents_b[9] => i342.DATAB
contents_b[9] => i~9.IN23
contents_b[10] => i51.IN1
contents_b[10] => i69.IN1
contents_b[10] => i87.IN1
contents_b[10] => i~6.IN22
contents_b[10] => i341.DATAB
contents_b[10] => i~9.IN22
contents_b[11] => i52.IN1
contents_b[11] => i70.IN1
contents_b[11] => i88.IN1
contents_b[11] => i~6.IN21
contents_b[11] => i340.DATAB
contents_b[11] => i~9.IN21
contents_b[12] => i53.IN1
contents_b[12] => i71.IN1
contents_b[12] => i89.IN1
contents_b[12] => i~6.IN20
contents_b[12] => i339.DATAB
contents_b[12] => i~9.IN20
contents_b[13] => i54.IN1
contents_b[13] => i72.IN1
contents_b[13] => i90.IN1
contents_b[13] => i~6.IN19
contents_b[13] => i338.DATAB
contents_b[13] => i~9.IN19
contents_b[14] => i55.IN1
contents_b[14] => i73.IN1
contents_b[14] => i91.IN1
contents_b[14] => i~6.IN18
contents_b[14] => i337.DATAB
contents_b[14] => i~9.IN18
contents_b[15] => i56.IN1
contents_b[15] => i74.IN1
contents_b[15] => i92.IN1
contents_b[15] => i~6.IN17
contents_b[15] => i336.DATAB
contents_b[15] => i~9.IN17
contents_b[15] => i458.IN1
imm7[0] => i~13.IN29
imm7[0] => i266.DATAB
imm7[0] => i~16.IN32
imm7[0] => i~15.IN32
imm7[1] => i~13.IN28
imm7[1] => i265.DATAB
imm7[1] => i~16.IN31
imm7[1] => i~15.IN31
imm7[2] => i~13.IN27
imm7[2] => i264.DATAB
imm7[2] => i~16.IN30
imm7[2] => i~15.IN30
imm7[3] => imm4[0].IN1
imm7[4] => imm4[1].IN1
imm7[5] => imm4[2].IN1
imm7[6] => imm4[3].IN1
opcode[0] => opcode[0]~1.IN1
opcode[1] => opcode[1]~0.IN1
opcode[2] => i~0.IN2
opcode[2] => i~1.IN2
opcode[2] => i~2.IN2
opcode[2] => i~3.IN2
opcode[2] => i~10.IN0
opcode[2] => i~17.IN0
opcode[2] => i~14.IN2
opcode[2] => i~12.IN2
opcode[2] => i~11.IN2
opcode[2] => i~8.IN2
opcode[2] => i~7.IN2
opcode[2] => i~5.IN2
opcode[2] => i~4.IN2
opcode[2] => i~19.IN2
opcode[3] => i~0.IN3
opcode[3] => i~1.IN3
opcode[3] => i~2.IN3
opcode[3] => i~3.IN3
opcode[3] => i~4.IN3
opcode[3] => i~5.IN3
opcode[3] => i~7.IN3
opcode[3] => i~8.IN3
opcode[3] => i~17.IN1
opcode[3] => i~14.IN3
opcode[3] => i~12.IN3
opcode[3] => i~11.IN3
opcode[3] => i~10.IN1
opcode[3] => i~19.IN3
result[0] <= i419.DB_MAX_OUTPUT_PORT_TYPE
result[1] <= i418.DB_MAX_OUTPUT_PORT_TYPE
result[2] <= i417.DB_MAX_OUTPUT_PORT_TYPE
result[3] <= i416.DB_MAX_OUTPUT_PORT_TYPE
result[4] <= i415.DB_MAX_OUTPUT_PORT_TYPE
result[5] <= i414.DB_MAX_OUTPUT_PORT_TYPE
result[6] <= i413.DB_MAX_OUTPUT_PORT_TYPE
result[7] <= i412.DB_MAX_OUTPUT_PORT_TYPE
result[8] <= i411.DB_MAX_OUTPUT_PORT_TYPE
result[9] <= i410.DB_MAX_OUTPUT_PORT_TYPE
result[10] <= i409.DB_MAX_OUTPUT_PORT_TYPE
result[11] <= i408.DB_MAX_OUTPUT_PORT_TYPE
result[12] <= i407.DB_MAX_OUTPUT_PORT_TYPE
result[13] <= i406.DB_MAX_OUTPUT_PORT_TYPE
result[14] <= i405.DB_MAX_OUTPUT_PORT_TYPE
result[15] <= i404.DB_MAX_OUTPUT_PORT_TYPE
flags[0] <= i438.DB_MAX_OUTPUT_PORT_TYPE
flags[1] <= i~18.DB_MAX_OUTPUT_PORT_TYPE
flags[2] <= i495.DB_MAX_OUTPUT_PORT_TYPE
flags[3] <= i404.DB_MAX_OUTPUT_PORT_TYPE


|N105_system|N_105_system:inst|uoccl_n105_0:the_uoccl_n105_0|cpu:the_cpu|alu:the_alu|shifter:the_shifter
contents_a[0] => i43.DATAA
contents_a[0] => i75.DATAB
contents_a[0] => i91.DATAA
contents_a[0] => i187.DATAB
contents_a[1] => i42.DATAA
contents_a[1] => i74.DATAB
contents_a[1] => i90.DATAA
contents_a[1] => i186.DATAB
contents_a[2] => i41.DATAA
contents_a[2] => i73.DATAB
contents_a[2] => i89.DATAA
contents_a[2] => i185.DATAB
contents_a[3] => i40.DATAA
contents_a[3] => i72.DATAB
contents_a[3] => i88.DATAA
contents_a[3] => i184.DATAB
contents_a[4] => i39.DATAA
contents_a[4] => i71.DATAB
contents_a[4] => i87.DATAA
contents_a[4] => i183.DATAB
contents_a[5] => i38.DATAA
contents_a[5] => i70.DATAB
contents_a[5] => i86.DATAA
contents_a[5] => i182.DATAB
contents_a[6] => i37.DATAA
contents_a[6] => i69.DATAB
contents_a[6] => i85.DATAA
contents_a[6] => i181.DATAB
contents_a[7] => i36.DATAA
contents_a[7] => i68.DATAB
contents_a[7] => i84.DATAA
contents_a[7] => i180.DATAB
contents_a[8] => i35.DATAA
contents_a[8] => i67.DATAB
contents_a[8] => i83.DATAA
contents_a[8] => i179.DATAB
contents_a[9] => i34.DATAA
contents_a[9] => i66.DATAB
contents_a[9] => i82.DATAA
contents_a[9] => i178.DATAB
contents_a[10] => i33.DATAA
contents_a[10] => i65.DATAB
contents_a[10] => i81.DATAA
contents_a[10] => i177.DATAB
contents_a[11] => i32.DATAA
contents_a[11] => i64.DATAB
contents_a[11] => i80.DATAA
contents_a[11] => i176.DATAB
contents_a[12] => i31.DATAA
contents_a[12] => i63.DATAB
contents_a[12] => i79.DATAA
contents_a[12] => i175.DATAB
contents_a[13] => i30.DATAA
contents_a[13] => i62.DATAB
contents_a[13] => i78.DATAA
contents_a[13] => i174.DATAB
contents_a[14] => i29.DATAA
contents_a[14] => i61.DATAB
contents_a[14] => i77.DATAA
contents_a[14] => i173.DATAB
contents_a[15] => i29.DATAB
contents_a[15] => i30.DATAB
contents_a[15] => i31.DATAB
contents_a[15] => i32.DATAB
contents_a[15] => i33.DATAB
contents_a[15] => i34.DATAB
contents_a[15] => i35.DATAB
contents_a[15] => i36.DATAB
contents_a[15] => i37.DATAB
contents_a[15] => i38.DATAB
contents_a[15] => i39.DATAB
contents_a[15] => i40.DATAB
contents_a[15] => i41.DATAB
contents_a[15] => i42.DATAB
contents_a[15] => i43.DATAB
contents_a[15] => i76.DATAA
contents_a[15] => i172.DATAB
imm4[0] => i155.OUTPUTSELECT
imm4[0] => i156.OUTPUTSELECT
imm4[0] => i157.OUTPUTSELECT
imm4[0] => i158.OUTPUTSELECT
imm4[0] => i159.OUTPUTSELECT
imm4[0] => i160.OUTPUTSELECT
imm4[0] => i161.OUTPUTSELECT
imm4[0] => i162.OUTPUTSELECT
imm4[0] => i163.OUTPUTSELECT
imm4[0] => i164.OUTPUTSELECT
imm4[0] => i165.OUTPUTSELECT
imm4[0] => i166.OUTPUTSELECT
imm4[0] => i167.OUTPUTSELECT
imm4[0] => i168.OUTPUTSELECT
imm4[0] => i169.OUTPUTSELECT
imm4[0] => i170.OUTPUTSELECT
imm4[0] => i~3.IN3
imm4[1] => i137.OUTPUTSELECT
imm4[1] => i138.OUTPUTSELECT
imm4[1] => i139.OUTPUTSELECT
imm4[1] => i140.OUTPUTSELECT
imm4[1] => i141.OUTPUTSELECT
imm4[1] => i142.OUTPUTSELECT
imm4[1] => i143.OUTPUTSELECT
imm4[1] => i144.OUTPUTSELECT
imm4[1] => i145.OUTPUTSELECT
imm4[1] => i146.OUTPUTSELECT
imm4[1] => i147.OUTPUTSELECT
imm4[1] => i148.OUTPUTSELECT
imm4[1] => i149.OUTPUTSELECT
imm4[1] => i150.OUTPUTSELECT
imm4[1] => i151.OUTPUTSELECT
imm4[1] => i152.OUTPUTSELECT
imm4[1] => i153.OUTPUTSELECT
imm4[1] => i~3.IN2
imm4[2] => i117.OUTPUTSELECT
imm4[2] => i118.OUTPUTSELECT
imm4[2] => i119.OUTPUTSELECT
imm4[2] => i120.OUTPUTSELECT
imm4[2] => i121.OUTPUTSELECT
imm4[2] => i122.OUTPUTSELECT
imm4[2] => i123.OUTPUTSELECT
imm4[2] => i124.OUTPUTSELECT
imm4[2] => i125.OUTPUTSELECT
imm4[2] => i126.OUTPUTSELECT
imm4[2] => i127.OUTPUTSELECT
imm4[2] => i128.OUTPUTSELECT
imm4[2] => i129.OUTPUTSELECT
imm4[2] => i130.OUTPUTSELECT
imm4[2] => i131.OUTPUTSELECT
imm4[2] => i132.OUTPUTSELECT
imm4[2] => i133.OUTPUTSELECT
imm4[2] => i134.OUTPUTSELECT
imm4[2] => i135.OUTPUTSELECT
imm4[2] => i~3.IN1
imm4[3] => i93.OUTPUTSELECT
imm4[3] => i94.OUTPUTSELECT
imm4[3] => i95.OUTPUTSELECT
imm4[3] => i96.OUTPUTSELECT
imm4[3] => i97.OUTPUTSELECT
imm4[3] => i98.OUTPUTSELECT
imm4[3] => i99.OUTPUTSELECT
imm4[3] => i100.OUTPUTSELECT
imm4[3] => i101.OUTPUTSELECT
imm4[3] => i102.OUTPUTSELECT
imm4[3] => i103.OUTPUTSELECT
imm4[3] => i104.OUTPUTSELECT
imm4[3] => i105.OUTPUTSELECT
imm4[3] => i106.OUTPUTSELECT
imm4[3] => i107.OUTPUTSELECT
imm4[3] => i108.OUTPUTSELECT
imm4[3] => i109.OUTPUTSELECT
imm4[3] => i110.OUTPUTSELECT
imm4[3] => i111.OUTPUTSELECT
imm4[3] => i112.OUTPUTSELECT
imm4[3] => i113.OUTPUTSELECT
imm4[3] => i114.OUTPUTSELECT
imm4[3] => i115.OUTPUTSELECT
imm4[3] => i~3.IN0
opcode[0] => i~0.IN1
opcode[0] => i~2.IN1
opcode[0] => i~1.IN1
opcode[1] => i~0.IN0
opcode[1] => i~1.IN0
opcode[1] => i~2.IN0
shift_result[0] <= i187.DB_MAX_OUTPUT_PORT_TYPE
shift_result[1] <= i186.DB_MAX_OUTPUT_PORT_TYPE
shift_result[2] <= i185.DB_MAX_OUTPUT_PORT_TYPE
shift_result[3] <= i184.DB_MAX_OUTPUT_PORT_TYPE
shift_result[4] <= i183.DB_MAX_OUTPUT_PORT_TYPE
shift_result[5] <= i182.DB_MAX_OUTPUT_PORT_TYPE
shift_result[6] <= i181.DB_MAX_OUTPUT_PORT_TYPE
shift_result[7] <= i180.DB_MAX_OUTPUT_PORT_TYPE
shift_result[8] <= i179.DB_MAX_OUTPUT_PORT_TYPE
shift_result[9] <= i178.DB_MAX_OUTPUT_PORT_TYPE
shift_result[10] <= i177.DB_MAX_OUTPUT_PORT_TYPE
shift_result[11] <= i176.DB_MAX_OUTPUT_PORT_TYPE
shift_result[12] <= i175.DB_MAX_OUTPUT_PORT_TYPE
shift_result[13] <= i174.DB_MAX_OUTPUT_PORT_TYPE
shift_result[14] <= i173.DB_MAX_OUTPUT_PORT_TYPE
shift_result[15] <= i172.DB_MAX_OUTPUT_PORT_TYPE


|N105_system|N_105_system:inst|uoccl_n105_0:the_uoccl_n105_0|cpu:the_cpu|branch_unit:the_branch_unit
clk => pc[14]~reg0.CLK
clk => pc[13]~reg0.CLK
clk => pc[12]~reg0.CLK
clk => pc[11]~reg0.CLK
clk => pc[10]~reg0.CLK
clk => pc[9]~reg0.CLK
clk => pc[8]~reg0.CLK
clk => pc[7]~reg0.CLK
clk => pc[6]~reg0.CLK
clk => pc[5]~reg0.CLK
clk => pc[4]~reg0.CLK
clk => pc[3]~reg0.CLK
clk => pc[2]~reg0.CLK
clk => pc[1]~reg0.CLK
clk => pc[0]~reg0.CLK
clk => pc[15]~reg0.CLK
reset => pc[14]~reg0.ACLR
reset => pc[13]~reg0.ACLR
reset => pc[12]~reg0.ACLR
reset => pc[11]~reg0.ACLR
reset => pc[10]~reg0.ACLR
reset => pc[9]~reg0.ACLR
reset => pc[8]~reg0.ACLR
reset => pc[7]~reg0.ACLR
reset => pc[6]~reg0.ACLR
reset => pc[5]~reg0.ACLR
reset => pc[4]~reg0.ACLR
reset => pc[3]~reg0.ACLR
reset => pc[2]~reg0.ACLR
reset => pc[1]~reg0.ACLR
reset => pc[0]~reg0.ACLR
reset => pc[15]~reg0.ACLR
return_en => i24.OUTPUTSELECT
return_en => i25.OUTPUTSELECT
return_en => i26.OUTPUTSELECT
return_en => i27.OUTPUTSELECT
return_en => i28.OUTPUTSELECT
return_en => i29.OUTPUTSELECT
return_en => i30.OUTPUTSELECT
return_en => i31.OUTPUTSELECT
return_en => i32.OUTPUTSELECT
return_en => i33.OUTPUTSELECT
return_en => i34.OUTPUTSELECT
return_en => i35.OUTPUTSELECT
return_en => i36.OUTPUTSELECT
return_en => i37.OUTPUTSELECT
return_en => i38.OUTPUTSELECT
return_en => i39.OUTPUTSELECT
return_addr[0] => i39.DATAB
return_addr[1] => i38.DATAB
return_addr[2] => i37.DATAB
return_addr[3] => i36.DATAB
return_addr[4] => i35.DATAB
return_addr[5] => i34.DATAB
return_addr[6] => i33.DATAB
return_addr[7] => i32.DATAB
return_addr[8] => i31.DATAB
return_addr[9] => i30.DATAB
return_addr[10] => i29.DATAB
return_addr[11] => i28.DATAB
return_addr[12] => i27.DATAB
return_addr[13] => i26.DATAB
return_addr[14] => i25.DATAB
return_addr[15] => i24.DATAB
imm11[0] => i~1.IN32
imm11[1] => i~1.IN31
imm11[2] => i~1.IN30
imm11[3] => i~1.IN29
imm11[4] => i~1.IN28
imm11[5] => i~1.IN27
imm11[6] => i~1.IN26
imm11[7] => i~1.IN25
imm11[8] => i~1.IN24
imm11[9] => i~1.IN23
imm11[10] => i~1.IN18
imm11[10] => i~1.IN19
imm11[10] => i~1.IN20
imm11[10] => i~1.IN21
imm11[10] => i~1.IN22
advance_pipeline => pc[15]~reg0.ENA
advance_pipeline => pc[14]~reg0.ENA
advance_pipeline => pc[13]~reg0.ENA
advance_pipeline => pc[12]~reg0.ENA
advance_pipeline => pc[11]~reg0.ENA
advance_pipeline => pc[10]~reg0.ENA
advance_pipeline => pc[9]~reg0.ENA
advance_pipeline => pc[8]~reg0.ENA
advance_pipeline => pc[7]~reg0.ENA
advance_pipeline => pc[6]~reg0.ENA
advance_pipeline => pc[5]~reg0.ENA
advance_pipeline => pc[4]~reg0.ENA
advance_pipeline => pc[3]~reg0.ENA
advance_pipeline => pc[2]~reg0.ENA
advance_pipeline => pc[1]~reg0.ENA
br_unit_en => i41.OUTPUTSELECT
br_unit_en => i42.OUTPUTSELECT
br_unit_en => i43.OUTPUTSELECT
br_unit_en => i44.OUTPUTSELECT
br_unit_en => i45.OUTPUTSELECT
br_unit_en => i46.OUTPUTSELECT
br_unit_en => i47.OUTPUTSELECT
br_unit_en => i48.OUTPUTSELECT
br_unit_en => i49.OUTPUTSELECT
br_unit_en => i50.OUTPUTSELECT
br_unit_en => i51.OUTPUTSELECT
br_unit_en => i52.OUTPUTSELECT
br_unit_en => i53.OUTPUTSELECT
br_unit_en => i54.OUTPUTSELECT
br_unit_en => i55.OUTPUTSELECT
new_return_addr[0] <= pc[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
new_return_addr[1] <= i~0.DB_MAX_OUTPUT_PORT_TYPE
new_return_addr[2] <= i~0.DB_MAX_OUTPUT_PORT_TYPE
new_return_addr[3] <= i~0.DB_MAX_OUTPUT_PORT_TYPE
new_return_addr[4] <= i~0.DB_MAX_OUTPUT_PORT_TYPE
new_return_addr[5] <= i~0.DB_MAX_OUTPUT_PORT_TYPE
new_return_addr[6] <= i~0.DB_MAX_OUTPUT_PORT_TYPE
new_return_addr[7] <= i~0.DB_MAX_OUTPUT_PORT_TYPE
new_return_addr[8] <= i~0.DB_MAX_OUTPUT_PORT_TYPE
new_return_addr[9] <= i~0.DB_MAX_OUTPUT_PORT_TYPE
new_return_addr[10] <= i~0.DB_MAX_OUTPUT_PORT_TYPE
new_return_addr[11] <= i~0.DB_MAX_OUTPUT_PORT_TYPE
new_return_addr[12] <= i~0.DB_MAX_OUTPUT_PORT_TYPE
new_return_addr[13] <= i~0.DB_MAX_OUTPUT_PORT_TYPE
new_return_addr[14] <= i~0.DB_MAX_OUTPUT_PORT_TYPE
new_return_addr[15] <= i~0.DB_MAX_OUTPUT_PORT_TYPE
pc[0] <= pc[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc[1] <= pc[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc[2] <= pc[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc[3] <= pc[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc[4] <= pc[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc[5] <= pc[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc[6] <= pc[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc[7] <= pc[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc[8] <= pc[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc[9] <= pc[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc[10] <= pc[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc[11] <= pc[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc[12] <= pc[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc[13] <= pc[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc[14] <= pc[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc[15] <= pc[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|N105_system|N_105_system:inst|uoccl_n105_0:the_uoccl_n105_0|cpu:the_cpu|condition_unit:the_condition_unit
clk => flags[2]~reg0.CLK
clk => flags[1]~reg0.CLK
clk => flags[0]~reg0.CLK
clk => flags[3]~reg0.CLK
flags_in[0] => flags[0]~reg0.DATAIN
flags_in[1] => flags[1]~reg0.DATAIN
flags_in[2] => flags[2]~reg0.DATAIN
flags_in[3] => flags[3]~reg0.DATAIN
set_cond_en => flags[2]~reg0.ENA
set_cond_en => flags[1]~reg0.ENA
set_cond_en => flags[0]~reg0.ENA
set_cond_en => flags[3]~reg0.ENA
flags[0] <= flags[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
flags[1] <= flags[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
flags[2] <= flags[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
flags[3] <= flags[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|N105_system|N_105_system:inst|uoccl_n105_0:the_uoccl_n105_0|cpu:the_cpu|reg_fetch:the_reg_fetch
clk => register_file[0][14].CLK
clk => register_file[0][13].CLK
clk => register_file[0][12].CLK
clk => register_file[0][11].CLK
clk => register_file[0][10].CLK
clk => register_file[0][9].CLK
clk => register_file[0][8].CLK
clk => register_file[0][7].CLK
clk => register_file[0][6].CLK
clk => register_file[0][5].CLK
clk => register_file[0][4].CLK
clk => register_file[0][3].CLK
clk => register_file[0][2].CLK
clk => register_file[0][1].CLK
clk => register_file[0][0].CLK
clk => register_file[1][15].CLK
clk => register_file[1][14].CLK
clk => register_file[1][13].CLK
clk => register_file[1][12].CLK
clk => register_file[1][11].CLK
clk => register_file[1][10].CLK
clk => register_file[1][9].CLK
clk => register_file[1][8].CLK
clk => register_file[1][7].CLK
clk => register_file[1][6].CLK
clk => register_file[1][5].CLK
clk => register_file[1][4].CLK
clk => register_file[1][3].CLK
clk => register_file[1][2].CLK
clk => register_file[1][1].CLK
clk => register_file[1][0].CLK
clk => register_file[2][15].CLK
clk => register_file[2][14].CLK
clk => register_file[2][13].CLK
clk => register_file[2][12].CLK
clk => register_file[2][11].CLK
clk => register_file[2][10].CLK
clk => register_file[2][9].CLK
clk => register_file[2][8].CLK
clk => register_file[2][7].CLK
clk => register_file[2][6].CLK
clk => register_file[2][5].CLK
clk => register_file[2][4].CLK
clk => register_file[2][3].CLK
clk => register_file[2][2].CLK
clk => register_file[2][1].CLK
clk => register_file[2][0].CLK
clk => register_file[3][15].CLK
clk => register_file[3][14].CLK
clk => register_file[3][13].CLK
clk => register_file[3][12].CLK
clk => register_file[3][11].CLK
clk => register_file[3][10].CLK
clk => register_file[3][9].CLK
clk => register_file[3][8].CLK
clk => register_file[3][7].CLK
clk => register_file[3][6].CLK
clk => register_file[3][5].CLK
clk => register_file[3][4].CLK
clk => register_file[3][3].CLK
clk => register_file[3][2].CLK
clk => register_file[3][1].CLK
clk => register_file[3][0].CLK
clk => register_file[4][15].CLK
clk => register_file[4][14].CLK
clk => register_file[4][13].CLK
clk => register_file[4][12].CLK
clk => register_file[4][11].CLK
clk => register_file[4][10].CLK
clk => register_file[4][9].CLK
clk => register_file[4][8].CLK
clk => register_file[4][7].CLK
clk => register_file[4][6].CLK
clk => register_file[4][5].CLK
clk => register_file[4][4].CLK
clk => register_file[4][3].CLK
clk => register_file[4][2].CLK
clk => register_file[4][1].CLK
clk => register_file[4][0].CLK
clk => register_file[5][15].CLK
clk => register_file[5][14].CLK
clk => register_file[5][13].CLK
clk => register_file[5][12].CLK
clk => register_file[5][11].CLK
clk => register_file[5][10].CLK
clk => register_file[5][9].CLK
clk => register_file[5][8].CLK
clk => register_file[5][7].CLK
clk => register_file[5][6].CLK
clk => register_file[5][5].CLK
clk => register_file[5][4].CLK
clk => register_file[5][3].CLK
clk => register_file[5][2].CLK
clk => register_file[5][1].CLK
clk => register_file[5][0].CLK
clk => register_file[6][15].CLK
clk => register_file[6][14].CLK
clk => register_file[6][13].CLK
clk => register_file[6][12].CLK
clk => register_file[6][11].CLK
clk => register_file[6][10].CLK
clk => register_file[6][9].CLK
clk => register_file[6][8].CLK
clk => register_file[6][7].CLK
clk => register_file[6][6].CLK
clk => register_file[6][5].CLK
clk => register_file[6][4].CLK
clk => register_file[6][3].CLK
clk => register_file[6][2].CLK
clk => register_file[6][1].CLK
clk => register_file[6][0].CLK
clk => register_file[7][15].CLK
clk => register_file[7][14].CLK
clk => register_file[7][13].CLK
clk => register_file[7][12].CLK
clk => register_file[7][11].CLK
clk => register_file[7][10].CLK
clk => register_file[7][9].CLK
clk => register_file[7][8].CLK
clk => register_file[7][7].CLK
clk => register_file[7][6].CLK
clk => register_file[7][5].CLK
clk => register_file[7][4].CLK
clk => register_file[7][3].CLK
clk => register_file[7][2].CLK
clk => register_file[7][1].CLK
clk => register_file[7][0].CLK
clk => register_file[8][15].CLK
clk => register_file[8][14].CLK
clk => register_file[8][13].CLK
clk => register_file[8][12].CLK
clk => register_file[8][11].CLK
clk => register_file[8][10].CLK
clk => register_file[8][9].CLK
clk => register_file[8][8].CLK
clk => register_file[8][7].CLK
clk => register_file[8][6].CLK
clk => register_file[8][5].CLK
clk => register_file[8][4].CLK
clk => register_file[8][3].CLK
clk => register_file[8][2].CLK
clk => register_file[8][1].CLK
clk => register_file[8][0].CLK
clk => register_file[9][15].CLK
clk => register_file[9][14].CLK
clk => register_file[9][13].CLK
clk => register_file[9][12].CLK
clk => register_file[9][11].CLK
clk => register_file[9][10].CLK
clk => register_file[9][9].CLK
clk => register_file[9][8].CLK
clk => register_file[9][7].CLK
clk => register_file[9][6].CLK
clk => register_file[9][5].CLK
clk => register_file[9][4].CLK
clk => register_file[9][3].CLK
clk => register_file[9][2].CLK
clk => register_file[9][1].CLK
clk => register_file[9][0].CLK
clk => register_file[10][15].CLK
clk => register_file[10][14].CLK
clk => register_file[10][13].CLK
clk => register_file[10][12].CLK
clk => register_file[10][11].CLK
clk => register_file[10][10].CLK
clk => register_file[10][9].CLK
clk => register_file[10][8].CLK
clk => register_file[10][7].CLK
clk => register_file[10][6].CLK
clk => register_file[10][5].CLK
clk => register_file[10][4].CLK
clk => register_file[10][3].CLK
clk => register_file[10][2].CLK
clk => register_file[10][1].CLK
clk => register_file[10][0].CLK
clk => register_file[11][15].CLK
clk => register_file[11][14].CLK
clk => register_file[11][13].CLK
clk => register_file[11][12].CLK
clk => register_file[11][11].CLK
clk => register_file[11][10].CLK
clk => register_file[11][9].CLK
clk => register_file[11][8].CLK
clk => register_file[11][7].CLK
clk => register_file[11][6].CLK
clk => register_file[11][5].CLK
clk => register_file[11][4].CLK
clk => register_file[11][3].CLK
clk => register_file[11][2].CLK
clk => register_file[11][1].CLK
clk => register_file[11][0].CLK
clk => register_file[12][15].CLK
clk => register_file[12][14].CLK
clk => register_file[12][13].CLK
clk => register_file[12][12].CLK
clk => register_file[12][11].CLK
clk => register_file[12][10].CLK
clk => register_file[12][9].CLK
clk => register_file[12][8].CLK
clk => register_file[12][7].CLK
clk => register_file[12][6].CLK
clk => register_file[12][5].CLK
clk => register_file[12][4].CLK
clk => register_file[12][3].CLK
clk => register_file[12][2].CLK
clk => register_file[12][1].CLK
clk => register_file[12][0].CLK
clk => register_file[13][15].CLK
clk => register_file[13][14].CLK
clk => register_file[13][13].CLK
clk => register_file[13][12].CLK
clk => register_file[13][11].CLK
clk => register_file[13][10].CLK
clk => register_file[13][9].CLK
clk => register_file[13][8].CLK
clk => register_file[13][7].CLK
clk => register_file[13][6].CLK
clk => register_file[13][5].CLK
clk => register_file[13][4].CLK
clk => register_file[13][3].CLK
clk => register_file[13][2].CLK
clk => register_file[13][1].CLK
clk => register_file[13][0].CLK
clk => register_file[14][15].CLK
clk => register_file[14][14].CLK
clk => register_file[14][13].CLK
clk => register_file[14][12].CLK
clk => register_file[14][11].CLK
clk => register_file[14][10].CLK
clk => register_file[14][9].CLK
clk => register_file[14][8].CLK
clk => register_file[14][7].CLK
clk => register_file[14][6].CLK
clk => register_file[14][5].CLK
clk => register_file[14][4].CLK
clk => register_file[14][3].CLK
clk => register_file[14][2].CLK
clk => register_file[14][1].CLK
clk => register_file[14][0].CLK
clk => register_file[15][15].CLK
clk => register_file[15][14].CLK
clk => register_file[15][13].CLK
clk => register_file[15][12].CLK
clk => register_file[15][11].CLK
clk => register_file[15][10].CLK
clk => register_file[15][9].CLK
clk => register_file[15][8].CLK
clk => register_file[15][7].CLK
clk => register_file[15][6].CLK
clk => register_file[15][5].CLK
clk => register_file[15][4].CLK
clk => register_file[15][3].CLK
clk => register_file[15][2].CLK
clk => register_file[15][1].CLK
clk => register_file[15][0].CLK
clk => register_file[0][15].CLK
br_unit_en => i4.IN1
br_unit_en => i967.OUTPUTSELECT
br_unit_en => i968.OUTPUTSELECT
br_unit_en => i969.OUTPUTSELECT
br_unit_en => i970.OUTPUTSELECT
br_unit_en => i971.OUTPUTSELECT
br_unit_en => i972.OUTPUTSELECT
br_unit_en => i973.OUTPUTSELECT
br_unit_en => i974.OUTPUTSELECT
br_unit_en => i975.OUTPUTSELECT
br_unit_en => i976.OUTPUTSELECT
br_unit_en => i977.OUTPUTSELECT
br_unit_en => i978.OUTPUTSELECT
br_unit_en => i979.OUTPUTSELECT
br_unit_en => i980.OUTPUTSELECT
br_unit_en => i981.OUTPUTSELECT
br_unit_en => i982.OUTPUTSELECT
index_a[0] => i~0.IN3
index_a[0] => i~2.IN3
index_a[0] => i~4.IN3
index_a[0] => i~6.IN3
index_a[0] => i~8.IN3
index_a[0] => i~10.IN3
index_a[0] => i~12.IN3
index_a[0] => i~14.IN3
index_a[0] => i~15.IN3
index_a[0] => i~13.IN3
index_a[0] => i~11.IN3
index_a[0] => i~9.IN3
index_a[0] => i~7.IN3
index_a[0] => i~5.IN3
index_a[0] => i~3.IN3
index_a[0] => i~1.IN3
index_a[1] => i~0.IN2
index_a[1] => i~1.IN2
index_a[1] => i~4.IN2
index_a[1] => i~5.IN2
index_a[1] => i~8.IN2
index_a[1] => i~9.IN2
index_a[1] => i~12.IN2
index_a[1] => i~13.IN2
index_a[1] => i~15.IN2
index_a[1] => i~14.IN2
index_a[1] => i~11.IN2
index_a[1] => i~10.IN2
index_a[1] => i~7.IN2
index_a[1] => i~6.IN2
index_a[1] => i~3.IN2
index_a[1] => i~2.IN2
index_a[2] => i~0.IN1
index_a[2] => i~1.IN1
index_a[2] => i~2.IN1
index_a[2] => i~3.IN1
index_a[2] => i~8.IN1
index_a[2] => i~9.IN1
index_a[2] => i~10.IN1
index_a[2] => i~11.IN1
index_a[2] => i~15.IN1
index_a[2] => i~14.IN1
index_a[2] => i~13.IN1
index_a[2] => i~12.IN1
index_a[2] => i~7.IN1
index_a[2] => i~6.IN1
index_a[2] => i~5.IN1
index_a[2] => i~4.IN1
index_a[3] => i~0.IN0
index_a[3] => i~1.IN0
index_a[3] => i~2.IN0
index_a[3] => i~3.IN0
index_a[3] => i~4.IN0
index_a[3] => i~5.IN0
index_a[3] => i~6.IN0
index_a[3] => i~7.IN0
index_a[3] => i~15.IN0
index_a[3] => i~14.IN0
index_a[3] => i~13.IN0
index_a[3] => i~12.IN0
index_a[3] => i~11.IN0
index_a[3] => i~10.IN0
index_a[3] => i~9.IN0
index_a[3] => i~8.IN0
index_b[0] => i~16.IN0
index_b[0] => i~18.IN0
index_b[0] => i~20.IN0
index_b[0] => i~22.IN0
index_b[0] => i~24.IN0
index_b[0] => i~26.IN0
index_b[0] => i~28.IN0
index_b[0] => i~30.IN0
index_b[0] => i~31.IN0
index_b[0] => i~29.IN0
index_b[0] => i~27.IN0
index_b[0] => i~25.IN0
index_b[0] => i~23.IN0
index_b[0] => i~21.IN0
index_b[0] => i~19.IN0
index_b[0] => i~17.IN0
index_b[1] => i~16.IN1
index_b[1] => i~17.IN1
index_b[1] => i~20.IN1
index_b[1] => i~21.IN1
index_b[1] => i~24.IN1
index_b[1] => i~25.IN1
index_b[1] => i~28.IN1
index_b[1] => i~29.IN1
index_b[1] => i~31.IN1
index_b[1] => i~30.IN1
index_b[1] => i~27.IN1
index_b[1] => i~26.IN1
index_b[1] => i~23.IN1
index_b[1] => i~22.IN1
index_b[1] => i~19.IN1
index_b[1] => i~18.IN1
index_b[2] => i~16.IN2
index_b[2] => i~17.IN2
index_b[2] => i~18.IN2
index_b[2] => i~19.IN2
index_b[2] => i~24.IN2
index_b[2] => i~25.IN2
index_b[2] => i~26.IN2
index_b[2] => i~27.IN2
index_b[2] => i~31.IN2
index_b[2] => i~30.IN2
index_b[2] => i~29.IN2
index_b[2] => i~28.IN2
index_b[2] => i~23.IN2
index_b[2] => i~22.IN2
index_b[2] => i~21.IN2
index_b[2] => i~20.IN2
index_b[3] => i~16.IN3
index_b[3] => i~17.IN3
index_b[3] => i~18.IN3
index_b[3] => i~19.IN3
index_b[3] => i~20.IN3
index_b[3] => i~21.IN3
index_b[3] => i~22.IN3
index_b[3] => i~23.IN3
index_b[3] => i~31.IN3
index_b[3] => i~30.IN3
index_b[3] => i~29.IN3
index_b[3] => i~28.IN3
index_b[3] => i~27.IN3
index_b[3] => i~26.IN3
index_b[3] => i~25.IN3
index_b[3] => i~24.IN3
dest_contents[0] => i966.DATAB
dest_contents[0] => i982.DATAB
dest_contents[0] => register_file[0][0].DATAIN
dest_contents[0] => register_file[1][0].DATAIN
dest_contents[0] => register_file[2][0].DATAIN
dest_contents[0] => register_file[3][0].DATAIN
dest_contents[0] => register_file[4][0].DATAIN
dest_contents[0] => register_file[5][0].DATAIN
dest_contents[0] => register_file[6][0].DATAIN
dest_contents[0] => register_file[7][0].DATAIN
dest_contents[0] => register_file[8][0].DATAIN
dest_contents[0] => register_file[9][0].DATAIN
dest_contents[0] => register_file[10][0].DATAIN
dest_contents[0] => register_file[11][0].DATAIN
dest_contents[0] => register_file[12][0].DATAIN
dest_contents[0] => register_file[13][0].DATAIN
dest_contents[0] => register_file[14][0].DATAIN
dest_contents[1] => i965.DATAB
dest_contents[1] => i981.DATAB
dest_contents[1] => register_file[0][1].DATAIN
dest_contents[1] => register_file[1][1].DATAIN
dest_contents[1] => register_file[2][1].DATAIN
dest_contents[1] => register_file[3][1].DATAIN
dest_contents[1] => register_file[4][1].DATAIN
dest_contents[1] => register_file[5][1].DATAIN
dest_contents[1] => register_file[6][1].DATAIN
dest_contents[1] => register_file[7][1].DATAIN
dest_contents[1] => register_file[8][1].DATAIN
dest_contents[1] => register_file[9][1].DATAIN
dest_contents[1] => register_file[10][1].DATAIN
dest_contents[1] => register_file[11][1].DATAIN
dest_contents[1] => register_file[12][1].DATAIN
dest_contents[1] => register_file[13][1].DATAIN
dest_contents[1] => register_file[14][1].DATAIN
dest_contents[2] => i964.DATAB
dest_contents[2] => i980.DATAB
dest_contents[2] => register_file[0][2].DATAIN
dest_contents[2] => register_file[1][2].DATAIN
dest_contents[2] => register_file[2][2].DATAIN
dest_contents[2] => register_file[3][2].DATAIN
dest_contents[2] => register_file[4][2].DATAIN
dest_contents[2] => register_file[5][2].DATAIN
dest_contents[2] => register_file[6][2].DATAIN
dest_contents[2] => register_file[7][2].DATAIN
dest_contents[2] => register_file[8][2].DATAIN
dest_contents[2] => register_file[9][2].DATAIN
dest_contents[2] => register_file[10][2].DATAIN
dest_contents[2] => register_file[11][2].DATAIN
dest_contents[2] => register_file[12][2].DATAIN
dest_contents[2] => register_file[13][2].DATAIN
dest_contents[2] => register_file[14][2].DATAIN
dest_contents[3] => i963.DATAB
dest_contents[3] => i979.DATAB
dest_contents[3] => register_file[0][3].DATAIN
dest_contents[3] => register_file[1][3].DATAIN
dest_contents[3] => register_file[2][3].DATAIN
dest_contents[3] => register_file[3][3].DATAIN
dest_contents[3] => register_file[4][3].DATAIN
dest_contents[3] => register_file[5][3].DATAIN
dest_contents[3] => register_file[6][3].DATAIN
dest_contents[3] => register_file[7][3].DATAIN
dest_contents[3] => register_file[8][3].DATAIN
dest_contents[3] => register_file[9][3].DATAIN
dest_contents[3] => register_file[10][3].DATAIN
dest_contents[3] => register_file[11][3].DATAIN
dest_contents[3] => register_file[12][3].DATAIN
dest_contents[3] => register_file[13][3].DATAIN
dest_contents[3] => register_file[14][3].DATAIN
dest_contents[4] => i962.DATAB
dest_contents[4] => i978.DATAB
dest_contents[4] => register_file[0][4].DATAIN
dest_contents[4] => register_file[1][4].DATAIN
dest_contents[4] => register_file[2][4].DATAIN
dest_contents[4] => register_file[3][4].DATAIN
dest_contents[4] => register_file[4][4].DATAIN
dest_contents[4] => register_file[5][4].DATAIN
dest_contents[4] => register_file[6][4].DATAIN
dest_contents[4] => register_file[7][4].DATAIN
dest_contents[4] => register_file[8][4].DATAIN
dest_contents[4] => register_file[9][4].DATAIN
dest_contents[4] => register_file[10][4].DATAIN
dest_contents[4] => register_file[11][4].DATAIN
dest_contents[4] => register_file[12][4].DATAIN
dest_contents[4] => register_file[13][4].DATAIN
dest_contents[4] => register_file[14][4].DATAIN
dest_contents[5] => i961.DATAB
dest_contents[5] => i977.DATAB
dest_contents[5] => register_file[0][5].DATAIN
dest_contents[5] => register_file[1][5].DATAIN
dest_contents[5] => register_file[2][5].DATAIN
dest_contents[5] => register_file[3][5].DATAIN
dest_contents[5] => register_file[4][5].DATAIN
dest_contents[5] => register_file[5][5].DATAIN
dest_contents[5] => register_file[6][5].DATAIN
dest_contents[5] => register_file[7][5].DATAIN
dest_contents[5] => register_file[8][5].DATAIN
dest_contents[5] => register_file[9][5].DATAIN
dest_contents[5] => register_file[10][5].DATAIN
dest_contents[5] => register_file[11][5].DATAIN
dest_contents[5] => register_file[12][5].DATAIN
dest_contents[5] => register_file[13][5].DATAIN
dest_contents[5] => register_file[14][5].DATAIN
dest_contents[6] => i960.DATAB
dest_contents[6] => i976.DATAB
dest_contents[6] => register_file[0][6].DATAIN
dest_contents[6] => register_file[1][6].DATAIN
dest_contents[6] => register_file[2][6].DATAIN
dest_contents[6] => register_file[3][6].DATAIN
dest_contents[6] => register_file[4][6].DATAIN
dest_contents[6] => register_file[5][6].DATAIN
dest_contents[6] => register_file[6][6].DATAIN
dest_contents[6] => register_file[7][6].DATAIN
dest_contents[6] => register_file[8][6].DATAIN
dest_contents[6] => register_file[9][6].DATAIN
dest_contents[6] => register_file[10][6].DATAIN
dest_contents[6] => register_file[11][6].DATAIN
dest_contents[6] => register_file[12][6].DATAIN
dest_contents[6] => register_file[13][6].DATAIN
dest_contents[6] => register_file[14][6].DATAIN
dest_contents[7] => i959.DATAB
dest_contents[7] => i975.DATAB
dest_contents[7] => register_file[0][7].DATAIN
dest_contents[7] => register_file[1][7].DATAIN
dest_contents[7] => register_file[2][7].DATAIN
dest_contents[7] => register_file[3][7].DATAIN
dest_contents[7] => register_file[4][7].DATAIN
dest_contents[7] => register_file[5][7].DATAIN
dest_contents[7] => register_file[6][7].DATAIN
dest_contents[7] => register_file[7][7].DATAIN
dest_contents[7] => register_file[8][7].DATAIN
dest_contents[7] => register_file[9][7].DATAIN
dest_contents[7] => register_file[10][7].DATAIN
dest_contents[7] => register_file[11][7].DATAIN
dest_contents[7] => register_file[12][7].DATAIN
dest_contents[7] => register_file[13][7].DATAIN
dest_contents[7] => register_file[14][7].DATAIN
dest_contents[8] => i958.DATAB
dest_contents[8] => i974.DATAB
dest_contents[8] => register_file[0][8].DATAIN
dest_contents[8] => register_file[1][8].DATAIN
dest_contents[8] => register_file[2][8].DATAIN
dest_contents[8] => register_file[3][8].DATAIN
dest_contents[8] => register_file[4][8].DATAIN
dest_contents[8] => register_file[5][8].DATAIN
dest_contents[8] => register_file[6][8].DATAIN
dest_contents[8] => register_file[7][8].DATAIN
dest_contents[8] => register_file[8][8].DATAIN
dest_contents[8] => register_file[9][8].DATAIN
dest_contents[8] => register_file[10][8].DATAIN
dest_contents[8] => register_file[11][8].DATAIN
dest_contents[8] => register_file[12][8].DATAIN
dest_contents[8] => register_file[13][8].DATAIN
dest_contents[8] => register_file[14][8].DATAIN
dest_contents[9] => i957.DATAB
dest_contents[9] => i973.DATAB
dest_contents[9] => register_file[0][9].DATAIN
dest_contents[9] => register_file[1][9].DATAIN
dest_contents[9] => register_file[2][9].DATAIN
dest_contents[9] => register_file[3][9].DATAIN
dest_contents[9] => register_file[4][9].DATAIN
dest_contents[9] => register_file[5][9].DATAIN
dest_contents[9] => register_file[6][9].DATAIN
dest_contents[9] => register_file[7][9].DATAIN
dest_contents[9] => register_file[8][9].DATAIN
dest_contents[9] => register_file[9][9].DATAIN
dest_contents[9] => register_file[10][9].DATAIN
dest_contents[9] => register_file[11][9].DATAIN
dest_contents[9] => register_file[12][9].DATAIN
dest_contents[9] => register_file[13][9].DATAIN
dest_contents[9] => register_file[14][9].DATAIN
dest_contents[10] => i956.DATAB
dest_contents[10] => i972.DATAB
dest_contents[10] => register_file[0][10].DATAIN
dest_contents[10] => register_file[1][10].DATAIN
dest_contents[10] => register_file[2][10].DATAIN
dest_contents[10] => register_file[3][10].DATAIN
dest_contents[10] => register_file[4][10].DATAIN
dest_contents[10] => register_file[5][10].DATAIN
dest_contents[10] => register_file[6][10].DATAIN
dest_contents[10] => register_file[7][10].DATAIN
dest_contents[10] => register_file[8][10].DATAIN
dest_contents[10] => register_file[9][10].DATAIN
dest_contents[10] => register_file[10][10].DATAIN
dest_contents[10] => register_file[11][10].DATAIN
dest_contents[10] => register_file[12][10].DATAIN
dest_contents[10] => register_file[13][10].DATAIN
dest_contents[10] => register_file[14][10].DATAIN
dest_contents[11] => i955.DATAB
dest_contents[11] => i971.DATAB
dest_contents[11] => register_file[0][11].DATAIN
dest_contents[11] => register_file[1][11].DATAIN
dest_contents[11] => register_file[2][11].DATAIN
dest_contents[11] => register_file[3][11].DATAIN
dest_contents[11] => register_file[4][11].DATAIN
dest_contents[11] => register_file[5][11].DATAIN
dest_contents[11] => register_file[6][11].DATAIN
dest_contents[11] => register_file[7][11].DATAIN
dest_contents[11] => register_file[8][11].DATAIN
dest_contents[11] => register_file[9][11].DATAIN
dest_contents[11] => register_file[10][11].DATAIN
dest_contents[11] => register_file[11][11].DATAIN
dest_contents[11] => register_file[12][11].DATAIN
dest_contents[11] => register_file[13][11].DATAIN
dest_contents[11] => register_file[14][11].DATAIN
dest_contents[12] => i954.DATAB
dest_contents[12] => i970.DATAB
dest_contents[12] => register_file[0][12].DATAIN
dest_contents[12] => register_file[1][12].DATAIN
dest_contents[12] => register_file[2][12].DATAIN
dest_contents[12] => register_file[3][12].DATAIN
dest_contents[12] => register_file[4][12].DATAIN
dest_contents[12] => register_file[5][12].DATAIN
dest_contents[12] => register_file[6][12].DATAIN
dest_contents[12] => register_file[7][12].DATAIN
dest_contents[12] => register_file[8][12].DATAIN
dest_contents[12] => register_file[9][12].DATAIN
dest_contents[12] => register_file[10][12].DATAIN
dest_contents[12] => register_file[11][12].DATAIN
dest_contents[12] => register_file[12][12].DATAIN
dest_contents[12] => register_file[13][12].DATAIN
dest_contents[12] => register_file[14][12].DATAIN
dest_contents[13] => i953.DATAB
dest_contents[13] => i969.DATAB
dest_contents[13] => register_file[0][13].DATAIN
dest_contents[13] => register_file[1][13].DATAIN
dest_contents[13] => register_file[2][13].DATAIN
dest_contents[13] => register_file[3][13].DATAIN
dest_contents[13] => register_file[4][13].DATAIN
dest_contents[13] => register_file[5][13].DATAIN
dest_contents[13] => register_file[6][13].DATAIN
dest_contents[13] => register_file[7][13].DATAIN
dest_contents[13] => register_file[8][13].DATAIN
dest_contents[13] => register_file[9][13].DATAIN
dest_contents[13] => register_file[10][13].DATAIN
dest_contents[13] => register_file[11][13].DATAIN
dest_contents[13] => register_file[12][13].DATAIN
dest_contents[13] => register_file[13][13].DATAIN
dest_contents[13] => register_file[14][13].DATAIN
dest_contents[14] => i952.DATAB
dest_contents[14] => i968.DATAB
dest_contents[14] => register_file[0][14].DATAIN
dest_contents[14] => register_file[1][14].DATAIN
dest_contents[14] => register_file[2][14].DATAIN
dest_contents[14] => register_file[3][14].DATAIN
dest_contents[14] => register_file[4][14].DATAIN
dest_contents[14] => register_file[5][14].DATAIN
dest_contents[14] => register_file[6][14].DATAIN
dest_contents[14] => register_file[7][14].DATAIN
dest_contents[14] => register_file[8][14].DATAIN
dest_contents[14] => register_file[9][14].DATAIN
dest_contents[14] => register_file[10][14].DATAIN
dest_contents[14] => register_file[11][14].DATAIN
dest_contents[14] => register_file[12][14].DATAIN
dest_contents[14] => register_file[13][14].DATAIN
dest_contents[14] => register_file[14][14].DATAIN
dest_contents[15] => i951.DATAB
dest_contents[15] => i967.DATAB
dest_contents[15] => register_file[1][15].DATAIN
dest_contents[15] => register_file[2][15].DATAIN
dest_contents[15] => register_file[3][15].DATAIN
dest_contents[15] => register_file[4][15].DATAIN
dest_contents[15] => register_file[5][15].DATAIN
dest_contents[15] => register_file[6][15].DATAIN
dest_contents[15] => register_file[7][15].DATAIN
dest_contents[15] => register_file[8][15].DATAIN
dest_contents[15] => register_file[9][15].DATAIN
dest_contents[15] => register_file[10][15].DATAIN
dest_contents[15] => register_file[11][15].DATAIN
dest_contents[15] => register_file[12][15].DATAIN
dest_contents[15] => register_file[13][15].DATAIN
dest_contents[15] => register_file[14][15].DATAIN
dest_contents[15] => register_file[0][15].DATAIN
write_en => i662.IN1
read_n_write => i4.IN0
read_n_write => i309.OUTPUTSELECT
read_n_write => i310.OUTPUTSELECT
read_n_write => i311.OUTPUTSELECT
read_n_write => i312.OUTPUTSELECT
read_n_write => i313.OUTPUTSELECT
read_n_write => i314.OUTPUTSELECT
read_n_write => i315.OUTPUTSELECT
read_n_write => i316.OUTPUTSELECT
read_n_write => i317.OUTPUTSELECT
read_n_write => i318.OUTPUTSELECT
read_n_write => i319.OUTPUTSELECT
read_n_write => i320.OUTPUTSELECT
read_n_write => i321.OUTPUTSELECT
read_n_write => i322.OUTPUTSELECT
read_n_write => i323.OUTPUTSELECT
read_n_write => i324.OUTPUTSELECT
read_n_write => i645.OUTPUTSELECT
read_n_write => i646.OUTPUTSELECT
read_n_write => i647.OUTPUTSELECT
read_n_write => i648.OUTPUTSELECT
read_n_write => i649.OUTPUTSELECT
read_n_write => i650.OUTPUTSELECT
read_n_write => i651.OUTPUTSELECT
read_n_write => i652.OUTPUTSELECT
read_n_write => i653.OUTPUTSELECT
read_n_write => i654.OUTPUTSELECT
read_n_write => i655.OUTPUTSELECT
read_n_write => i656.OUTPUTSELECT
read_n_write => i657.OUTPUTSELECT
read_n_write => i658.OUTPUTSELECT
read_n_write => i659.OUTPUTSELECT
read_n_write => i660.OUTPUTSELECT
read_n_write => i662.IN0


|N105_system|N_105_system:inst|uoccl_n105_0:the_uoccl_n105_0|cpu:the_cpu|write_back:the_write_back
alu_result[0] => i35.DATAB
alu_result[1] => i34.DATAB
alu_result[2] => i33.DATAB
alu_result[3] => i32.DATAB
alu_result[4] => i31.DATAB
alu_result[5] => i30.DATAB
alu_result[6] => i29.DATAB
alu_result[7] => i28.DATAB
alu_result[8] => i27.DATAB
alu_result[9] => i26.DATAB
alu_result[10] => i25.DATAB
alu_result[11] => i24.DATAB
alu_result[12] => i23.DATAB
alu_result[13] => i22.DATAB
alu_result[14] => i21.DATAB
alu_result[15] => i20.DATAB
alu_en => i20.OUTPUTSELECT
alu_en => i21.OUTPUTSELECT
alu_en => i22.OUTPUTSELECT
alu_en => i23.OUTPUTSELECT
alu_en => i24.OUTPUTSELECT
alu_en => i25.OUTPUTSELECT
alu_en => i26.OUTPUTSELECT
alu_en => i27.OUTPUTSELECT
alu_en => i28.OUTPUTSELECT
alu_en => i29.OUTPUTSELECT
alu_en => i30.OUTPUTSELECT
alu_en => i31.OUTPUTSELECT
alu_en => i32.OUTPUTSELECT
alu_en => i33.OUTPUTSELECT
alu_en => i34.OUTPUTSELECT
alu_en => i35.OUTPUTSELECT
alu_en => i36.IN0
load_result[0] => i19.DATAA
load_result[1] => i18.DATAA
load_result[2] => i17.DATAA
load_result[3] => i16.DATAA
load_result[4] => i15.DATAA
load_result[5] => i14.DATAA
load_result[6] => i13.DATAA
load_result[7] => i12.DATAA
load_result[8] => i11.DATAA
load_result[9] => i10.DATAA
load_result[10] => i9.DATAA
load_result[11] => i8.DATAA
load_result[12] => i7.DATAA
load_result[13] => i6.DATAA
load_result[14] => i5.DATAA
load_result[15] => i4.DATAA
load_en => i36.IN1
bsr_en => i4.OUTPUTSELECT
bsr_en => i5.OUTPUTSELECT
bsr_en => i6.OUTPUTSELECT
bsr_en => i7.OUTPUTSELECT
bsr_en => i8.OUTPUTSELECT
bsr_en => i9.OUTPUTSELECT
bsr_en => i10.OUTPUTSELECT
bsr_en => i11.OUTPUTSELECT
bsr_en => i12.OUTPUTSELECT
bsr_en => i13.OUTPUTSELECT
bsr_en => i14.OUTPUTSELECT
bsr_en => i15.OUTPUTSELECT
bsr_en => i16.OUTPUTSELECT
bsr_en => i17.OUTPUTSELECT
bsr_en => i18.OUTPUTSELECT
bsr_en => i19.OUTPUTSELECT
bsr_en => i37.IN0
ret_addr[0] => i19.DATAB
ret_addr[1] => i18.DATAB
ret_addr[2] => i17.DATAB
ret_addr[3] => i16.DATAB
ret_addr[4] => i15.DATAB
ret_addr[5] => i14.DATAB
ret_addr[6] => i13.DATAB
ret_addr[7] => i12.DATAB
ret_addr[8] => i11.DATAB
ret_addr[9] => i10.DATAB
ret_addr[10] => i9.DATAB
ret_addr[11] => i8.DATAB
ret_addr[12] => i7.DATAB
ret_addr[13] => i6.DATAB
ret_addr[14] => i5.DATAB
ret_addr[15] => i4.DATAB
dest_contents[0] <= i35.DB_MAX_OUTPUT_PORT_TYPE
dest_contents[1] <= i34.DB_MAX_OUTPUT_PORT_TYPE
dest_contents[2] <= i33.DB_MAX_OUTPUT_PORT_TYPE
dest_contents[3] <= i32.DB_MAX_OUTPUT_PORT_TYPE
dest_contents[4] <= i31.DB_MAX_OUTPUT_PORT_TYPE
dest_contents[5] <= i30.DB_MAX_OUTPUT_PORT_TYPE
dest_contents[6] <= i29.DB_MAX_OUTPUT_PORT_TYPE
dest_contents[7] <= i28.DB_MAX_OUTPUT_PORT_TYPE
dest_contents[8] <= i27.DB_MAX_OUTPUT_PORT_TYPE
dest_contents[9] <= i26.DB_MAX_OUTPUT_PORT_TYPE
dest_contents[10] <= i25.DB_MAX_OUTPUT_PORT_TYPE
dest_contents[11] <= i24.DB_MAX_OUTPUT_PORT_TYPE
dest_contents[12] <= i23.DB_MAX_OUTPUT_PORT_TYPE
dest_contents[13] <= i22.DB_MAX_OUTPUT_PORT_TYPE
dest_contents[14] <= i21.DB_MAX_OUTPUT_PORT_TYPE
dest_contents[15] <= i20.DB_MAX_OUTPUT_PORT_TYPE
write_en <= i37.DB_MAX_OUTPUT_PORT_TYPE


|N105_system|debouncer:inst1
CLK => sync[0].CLK
CLK => previous.CLK
CLK => count[15].CLK
CLK => count[14].CLK
CLK => count[13].CLK
CLK => count[12].CLK
CLK => count[11].CLK
CLK => count[10].CLK
CLK => count[9].CLK
CLK => count[8].CLK
CLK => count[7].CLK
CLK => count[6].CLK
CLK => count[5].CLK
CLK => count[4].CLK
CLK => count[3].CLK
CLK => count[2].CLK
CLK => count[1].CLK
CLK => count[0].CLK
CLK => reset_n~reg0.CLK
CLK => sync[1].CLK
SWITCH => sync[0].DATAIN
reset_n <= reset_n~reg0.DB_MAX_OUTPUT_PORT_TYPE


