N-105 readme


This document provides a brief introduction to the N-105 processor. Any questions or comments should be made to Daniel Hulme (dh286) and Rosemary Francis (rmf30). 

To include the N-105 processor in a system design you need to put this in your SOPC Builder Library path. Start SOPC Builder and select 'SOPC Builder Setup...' from the File menu. In the "Additional directories containing SOPC Builder components / kits" box, you need to type (assuming ecad-labs is mapped to drive letter X) "x:\Summer2004\N_105". After restarting SOPC Builder, the N-105 processor should appear in the list of installed components on the left. Before you can generate the project in SOPC Builder you will need to uncheck and recheck the "use" box for the n105 component because there is a bug in the system!

The N-105 is intended as a simple example of a working processor to be used to teach processor design. It is loosely based on the design choices of Altera's Nios processor, but contains no derived code, and has a different, smaller, instruction set. The N-105 has a 16-bit architecture.

The N-105 has a two-stage pipeline: instruction fetch, and everything else. It is designed around separate instruction and data memories, but uses the Avalon bus, so could be easily adapted for a shared memory.

The N-105 instruction mnemonics are a subset of Nios's, but the instruction format is much simpler.

15   11  8 7 5 4  0
+----+----+---+----+
| rA | rB |   | op |
+----+----+---+----+

The opcode is 5 bits long, providing 32 possible operations. 16 of these are used for ALU operations, and there are 6 additional instructions (load, store, branch, branch subroutine, return, and a conditional). This leaves 10 opcodes for future expansion or custom instructions. The binary opcodes are given in a separate document. For instructions, such as ADDI, that take an immediate and one register, bits 5 to 11 provide a 7-bit signed or unsigned immediate. Branching instructions use an 11-bit immediate that is the signed halfword offset from the instruction following the branch. 

Branch delay slot behaviour is the same as for the Nios processor (i.e. the instruction following the BR, BSR, or RET is executed before the branch), which removes the need to flush the pipeline for a branch. The condition codes for the IFS operation are the same (in binary and assembler mnemonics) as for the Nios, and are placed in bits 8 to 11.

Architecture-wise, the N-105 is very simple: only about 800 lines of Verilog. It has no MMU (memory management unit), FPU (floating point unit), caches, interrupts or exceptions. There are 16 16-bit registers and a 15-bit program counter. Register 15 is used as the link register for BSR and RET instructions. Much of the simplicity of the N-105 is made possible by the Avalon bus, as it provides a simple interface to an easy-to-use bus architecture. This simplicity makes the N-105 code short enough to fit into a lecture handout, which was one of the original goals.
