The changes made to the Xi5 bits for assisting experimental work are the addition of clocks and timestamping. The design of these was driven by the requests made by experimenters who wished to measure the performance of the switch and investigate different cell scheduling mechanisms. The timer clock TC was added to enable controlled generation of CPU interrupts in particular to aid with rate based scheduling disciplines. Timestamping in the data portion of cells was added to enable delay measurements.
The width of the clocks was chosen to be 16 bits because when a stream
of cells is passing through the port controller from a particular
connection, the clock(s) will respectively be used to measure
(timestamp) and schedule the cells for transmission according to a
negotiated rate. For a given cell the time spent at the port
controller is measured by the difference (modulo the clock size)
between the time of its arrival and the time of its departure on the
FRC. If the clock is insufficiently wide then it may roll over
completely whilst the cell is at the port controller, and the
measurement of the cell's residence time at the port controller will
be incorrect by one full clock period. With a clock of width 16 bits,
and a frame pulse every 3
, cells from a periodic (CBR) source
of greater than 
Kb/s, the clock will never roll over completely
within the interarrival time of two cells. It will therefore be
sufficient to use the FRC for delay measurements and the TC for
scheduling to ensure that all streams are accurately measured.
A stream of cells transmitted through the network with the timestamping VCI bits set up appropriately will permit the measurement of jitter and delay at each node (switch) traversed by the stream. This will be particularly valuable for cell level scheduling experiments, where different scheduling algorithms will be compared. These algorithms will aim to ensure that each class of traffic meets its QOS requirements, and that the overall performance requirements of the ATM multiplexer at a port controller are met. Implementing the delay stamping in hardware saves approximately 10 instructions per cell in the fiq for experiments in which cell delays must be measured. It has the additional advantage that it can be selectively enabled for a particular connection and for a particular port controller, by setting up the delay stamping VCIs appropriately.